1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: interrupt-controller@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma-controller@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 reg-names = "pm", "asb", "rpivid_asb"; 117 clocks = <&clocks BCM2835_CLOCK_V3D>, 118 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 119 <&clocks BCM2835_CLOCK_H264>, 120 <&clocks BCM2835_CLOCK_ISP>; 121 clock-names = "v3d", "peri_image", "h264", "isp"; 122 system-power-controller; 123 }; 124 125 rng@7e104000 { 126 compatible = "brcm,bcm2711-rng200"; 127 reg = <0x7e104000 0x28>; 128 }; 129 130 uart2: serial@7e201400 { 131 compatible = "arm,pl011", "arm,primecell"; 132 reg = <0x7e201400 0x200>; 133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&clocks BCM2835_CLOCK_UART>, 135 <&clocks BCM2835_CLOCK_VPU>; 136 clock-names = "uartclk", "apb_pclk"; 137 arm,primecell-periphid = <0x00341011>; 138 status = "disabled"; 139 }; 140 141 uart3: serial@7e201600 { 142 compatible = "arm,pl011", "arm,primecell"; 143 reg = <0x7e201600 0x200>; 144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&clocks BCM2835_CLOCK_UART>, 146 <&clocks BCM2835_CLOCK_VPU>; 147 clock-names = "uartclk", "apb_pclk"; 148 arm,primecell-periphid = <0x00341011>; 149 status = "disabled"; 150 }; 151 152 uart4: serial@7e201800 { 153 compatible = "arm,pl011", "arm,primecell"; 154 reg = <0x7e201800 0x200>; 155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clocks BCM2835_CLOCK_UART>, 157 <&clocks BCM2835_CLOCK_VPU>; 158 clock-names = "uartclk", "apb_pclk"; 159 arm,primecell-periphid = <0x00341011>; 160 status = "disabled"; 161 }; 162 163 uart5: serial@7e201a00 { 164 compatible = "arm,pl011", "arm,primecell"; 165 reg = <0x7e201a00 0x200>; 166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&clocks BCM2835_CLOCK_UART>, 168 <&clocks BCM2835_CLOCK_VPU>; 169 clock-names = "uartclk", "apb_pclk"; 170 arm,primecell-periphid = <0x00341011>; 171 status = "disabled"; 172 }; 173 174 spi3: spi@7e204600 { 175 compatible = "brcm,bcm2835-spi"; 176 reg = <0x7e204600 0x0200>; 177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clocks BCM2835_CLOCK_VPU>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 }; 183 184 spi4: spi@7e204800 { 185 compatible = "brcm,bcm2835-spi"; 186 reg = <0x7e204800 0x0200>; 187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clocks BCM2835_CLOCK_VPU>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 spi5: spi@7e204a00 { 195 compatible = "brcm,bcm2835-spi"; 196 reg = <0x7e204a00 0x0200>; 197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clocks BCM2835_CLOCK_VPU>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 }; 203 204 spi6: spi@7e204c00 { 205 compatible = "brcm,bcm2835-spi"; 206 reg = <0x7e204c00 0x0200>; 207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clocks BCM2835_CLOCK_VPU>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 i2c3: i2c@7e205600 { 215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 216 reg = <0x7e205600 0x200>; 217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clocks BCM2835_CLOCK_VPU>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 status = "disabled"; 222 }; 223 224 i2c4: i2c@7e205800 { 225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 226 reg = <0x7e205800 0x200>; 227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clocks BCM2835_CLOCK_VPU>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 i2c5: i2c@7e205a00 { 235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 236 reg = <0x7e205a00 0x200>; 237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clocks BCM2835_CLOCK_VPU>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 i2c6: i2c@7e205c00 { 245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 246 reg = <0x7e205c00 0x200>; 247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clocks BCM2835_CLOCK_VPU>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 pixelvalve0: pixelvalve@7e206000 { 255 compatible = "brcm,bcm2711-pixelvalve0"; 256 reg = <0x7e206000 0x100>; 257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 258 status = "disabled"; 259 }; 260 261 pixelvalve1: pixelvalve@7e207000 { 262 compatible = "brcm,bcm2711-pixelvalve1"; 263 reg = <0x7e207000 0x100>; 264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 }; 267 268 pixelvalve2: pixelvalve@7e20a000 { 269 compatible = "brcm,bcm2711-pixelvalve2"; 270 reg = <0x7e20a000 0x100>; 271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 272 status = "disabled"; 273 }; 274 275 pwm1: pwm@7e20c800 { 276 compatible = "brcm,bcm2835-pwm"; 277 reg = <0x7e20c800 0x28>; 278 clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 280 assigned-clock-rates = <10000000>; 281 #pwm-cells = <3>; 282 status = "disabled"; 283 }; 284 285 pixelvalve4: pixelvalve@7e216000 { 286 compatible = "brcm,bcm2711-pixelvalve4"; 287 reg = <0x7e216000 0x100>; 288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 289 status = "disabled"; 290 }; 291 292 hvs: hvs@7e400000 { 293 compatible = "brcm,bcm2711-hvs"; 294 reg = <0x7e400000 0x8000>; 295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 296 }; 297 298 pixelvalve3: pixelvalve@7ec12000 { 299 compatible = "brcm,bcm2711-pixelvalve3"; 300 reg = <0x7ec12000 0x100>; 301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 302 status = "disabled"; 303 }; 304 305 vec: vec@7ec13000 { 306 compatible = "brcm,bcm2711-vec"; 307 reg = <0x7ec13000 0x1000>; 308 clocks = <&clocks BCM2835_CLOCK_VEC>; 309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 dvp: clock@7ef00000 { 314 compatible = "brcm,brcm2711-dvp"; 315 reg = <0x7ef00000 0x10>; 316 clocks = <&clk_108MHz>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 }; 320 321 aon_intr: interrupt-controller@7ef00100 { 322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 323 reg = <0x7ef00100 0x30>; 324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-controller; 326 #interrupt-cells = <1>; 327 }; 328 329 hdmi0: hdmi@7ef00700 { 330 compatible = "brcm,bcm2711-hdmi0"; 331 reg = <0x7ef00700 0x300>, 332 <0x7ef00300 0x200>, 333 <0x7ef00f00 0x80>, 334 <0x7ef00f80 0x80>, 335 <0x7ef01b00 0x200>, 336 <0x7ef01f00 0x400>, 337 <0x7ef00200 0x80>, 338 <0x7ef04300 0x100>, 339 <0x7ef20000 0x100>; 340 reg-names = "hdmi", 341 "dvp", 342 "phy", 343 "rm", 344 "packet", 345 "metadata", 346 "csc", 347 "cec", 348 "hd"; 349 clock-names = "hdmi", "bvb", "audio", "cec"; 350 resets = <&dvp 0>; 351 interrupt-parent = <&aon_intr>; 352 interrupts = <0>, <1>, <2>, 353 <3>, <4>, <5>; 354 interrupt-names = "cec-tx", "cec-rx", "cec-low", 355 "wakeup", "hpd-connected", "hpd-removed"; 356 ddc = <&ddc0>; 357 dmas = <&dma 10>; 358 dma-names = "audio-rx"; 359 status = "disabled"; 360 }; 361 362 ddc0: i2c@7ef04500 { 363 compatible = "brcm,bcm2711-hdmi-i2c"; 364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 365 reg-names = "bsc", "auto-i2c"; 366 clock-frequency = <97500>; 367 status = "disabled"; 368 }; 369 370 hdmi1: hdmi@7ef05700 { 371 compatible = "brcm,bcm2711-hdmi1"; 372 reg = <0x7ef05700 0x300>, 373 <0x7ef05300 0x200>, 374 <0x7ef05f00 0x80>, 375 <0x7ef05f80 0x80>, 376 <0x7ef06b00 0x200>, 377 <0x7ef06f00 0x400>, 378 <0x7ef00280 0x80>, 379 <0x7ef09300 0x100>, 380 <0x7ef20000 0x100>; 381 reg-names = "hdmi", 382 "dvp", 383 "phy", 384 "rm", 385 "packet", 386 "metadata", 387 "csc", 388 "cec", 389 "hd"; 390 ddc = <&ddc1>; 391 clock-names = "hdmi", "bvb", "audio", "cec"; 392 resets = <&dvp 1>; 393 interrupt-parent = <&aon_intr>; 394 interrupts = <8>, <7>, <6>, 395 <9>, <10>, <11>; 396 interrupt-names = "cec-tx", "cec-rx", "cec-low", 397 "wakeup", "hpd-connected", "hpd-removed"; 398 dmas = <&dma 17>; 399 dma-names = "audio-rx"; 400 status = "disabled"; 401 }; 402 403 ddc1: i2c@7ef09500 { 404 compatible = "brcm,bcm2711-hdmi-i2c"; 405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 406 reg-names = "bsc", "auto-i2c"; 407 clock-frequency = <97500>; 408 status = "disabled"; 409 }; 410 }; 411 412 /* 413 * emmc2 has different DMA constraints based on SoC revisions. It was 414 * moved into its own bus, so as for RPi4's firmware to update them. 415 * The firmware will find whether the emmc2bus alias is defined, and if 416 * so, it'll edit the dma-ranges property below accordingly. 417 */ 418 emmc2bus: emmc2bus { 419 compatible = "simple-bus"; 420 #address-cells = <2>; 421 #size-cells = <1>; 422 423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 425 426 emmc2: mmc@7e340000 { 427 compatible = "brcm,bcm2711-emmc2"; 428 reg = <0x0 0x7e340000 0x100>; 429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 431 status = "disabled"; 432 }; 433 }; 434 435 arm-pmu { 436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 442 }; 443 444 timer { 445 compatible = "arm,armv8-timer"; 446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 447 IRQ_TYPE_LEVEL_LOW)>, 448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 449 IRQ_TYPE_LEVEL_LOW)>, 450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 451 IRQ_TYPE_LEVEL_LOW)>, 452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 453 IRQ_TYPE_LEVEL_LOW)>; 454 }; 455 456 cpus: cpus { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 460 461 /* Source for d/i-cache-line-size and d/i-cache-sets 462 * https://developer.arm.com/documentation/100095/0003 463 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 464 * Source for d/i-cache-size 465 * https://www.raspberrypi.com/documentation/computers 466 * /processors.html#bcm2711 467 */ 468 cpu0: cpu@0 { 469 device_type = "cpu"; 470 compatible = "arm,cortex-a72"; 471 reg = <0>; 472 enable-method = "spin-table"; 473 cpu-release-addr = <0x0 0x000000d8>; 474 d-cache-size = <0x8000>; 475 d-cache-line-size = <64>; 476 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 477 i-cache-size = <0xc000>; 478 i-cache-line-size = <64>; 479 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 480 next-level-cache = <&l2>; 481 }; 482 483 cpu1: cpu@1 { 484 device_type = "cpu"; 485 compatible = "arm,cortex-a72"; 486 reg = <1>; 487 enable-method = "spin-table"; 488 cpu-release-addr = <0x0 0x000000e0>; 489 d-cache-size = <0x8000>; 490 d-cache-line-size = <64>; 491 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 492 i-cache-size = <0xc000>; 493 i-cache-line-size = <64>; 494 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 495 next-level-cache = <&l2>; 496 }; 497 498 cpu2: cpu@2 { 499 device_type = "cpu"; 500 compatible = "arm,cortex-a72"; 501 reg = <2>; 502 enable-method = "spin-table"; 503 cpu-release-addr = <0x0 0x000000e8>; 504 d-cache-size = <0x8000>; 505 d-cache-line-size = <64>; 506 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 507 i-cache-size = <0xc000>; 508 i-cache-line-size = <64>; 509 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 510 next-level-cache = <&l2>; 511 }; 512 513 cpu3: cpu@3 { 514 device_type = "cpu"; 515 compatible = "arm,cortex-a72"; 516 reg = <3>; 517 enable-method = "spin-table"; 518 cpu-release-addr = <0x0 0x000000f0>; 519 d-cache-size = <0x8000>; 520 d-cache-line-size = <64>; 521 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 522 i-cache-size = <0xc000>; 523 i-cache-line-size = <64>; 524 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 525 next-level-cache = <&l2>; 526 }; 527 528 /* Source for d/i-cache-line-size and d/i-cache-sets 529 * https://developer.arm.com/documentation/100095/0003 530 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 531 * Source for d/i-cache-size 532 * https://www.raspberrypi.com/documentation/computers 533 * /processors.html#bcm2711 534 */ 535 l2: l2-cache0 { 536 compatible = "cache"; 537 cache-unified; 538 cache-size = <0x100000>; 539 cache-line-size = <64>; 540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 541 cache-level = <2>; 542 }; 543 }; 544 545 scb { 546 compatible = "simple-bus"; 547 #address-cells = <2>; 548 #size-cells = <1>; 549 550 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 551 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 552 553 pcie0: pcie@7d500000 { 554 compatible = "brcm,bcm2711-pcie"; 555 reg = <0x0 0x7d500000 0x9310>; 556 device_type = "pci"; 557 #address-cells = <3>; 558 #interrupt-cells = <1>; 559 #size-cells = <2>; 560 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "pcie", "msi"; 563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 565 IRQ_TYPE_LEVEL_HIGH>, 566 <0 0 0 2 &gicv2 GIC_SPI 144 567 IRQ_TYPE_LEVEL_HIGH>, 568 <0 0 0 3 &gicv2 GIC_SPI 145 569 IRQ_TYPE_LEVEL_HIGH>, 570 <0 0 0 4 &gicv2 GIC_SPI 146 571 IRQ_TYPE_LEVEL_HIGH>; 572 msi-controller; 573 msi-parent = <&pcie0>; 574 575 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 576 0x0 0x04000000>; 577 /* 578 * The wrapper around the PCIe block has a bug 579 * preventing it from accessing beyond the first 3GB of 580 * memory. 581 */ 582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 583 0x0 0xc0000000>; 584 brcm,enable-ssc; 585 }; 586 587 genet: ethernet@7d580000 { 588 compatible = "brcm,bcm2711-genet-v5"; 589 reg = <0x0 0x7d580000 0x10000>; 590 #address-cells = <0x1>; 591 #size-cells = <0x1>; 592 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 594 status = "disabled"; 595 596 genet_mdio: mdio@e14 { 597 compatible = "brcm,genet-mdio-v5"; 598 reg = <0xe14 0x8>; 599 reg-names = "mdio"; 600 #address-cells = <0x1>; 601 #size-cells = <0x0>; 602 }; 603 }; 604 605 v3d: gpu@7ec00000 { 606 compatible = "brcm,2711-v3d"; 607 reg = <0x0 0x7ec00000 0x4000>, 608 <0x0 0x7ec04000 0x4000>; 609 reg-names = "hub", "core0"; 610 611 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 612 resets = <&pm BCM2835_RESET_V3D>; 613 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 614 }; 615 }; 616}; 617 618&clk_osc { 619 clock-frequency = <54000000>; 620}; 621 622&clocks { 623 compatible = "brcm,bcm2711-cprman"; 624}; 625 626&cpu_thermal { 627 coefficients = <(-487) 410040>; 628 thermal-sensors = <&thermal>; 629}; 630 631&dsi0 { 632 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 633}; 634 635&dsi1 { 636 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 637 compatible = "brcm,bcm2711-dsi1"; 638}; 639 640&gpio { 641 compatible = "brcm,bcm2711-gpio"; 642 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 647 gpio-ranges = <&gpio 0 0 58>; 648 649 gpclk0_gpio49: gpclk0-gpio49 { 650 pin-gpclk { 651 pins = "gpio49"; 652 function = "alt1"; 653 bias-disable; 654 }; 655 }; 656 gpclk1_gpio50: gpclk1-gpio50 { 657 pin-gpclk { 658 pins = "gpio50"; 659 function = "alt1"; 660 bias-disable; 661 }; 662 }; 663 gpclk2_gpio51: gpclk2-gpio51 { 664 pin-gpclk { 665 pins = "gpio51"; 666 function = "alt1"; 667 bias-disable; 668 }; 669 }; 670 671 i2c0_gpio46: i2c0-gpio46 { 672 pin-sda { 673 function = "alt0"; 674 pins = "gpio46"; 675 bias-pull-up; 676 }; 677 pin-scl { 678 function = "alt0"; 679 pins = "gpio47"; 680 bias-disable; 681 }; 682 }; 683 i2c1_gpio46: i2c1-gpio46 { 684 pin-sda { 685 function = "alt1"; 686 pins = "gpio46"; 687 bias-pull-up; 688 }; 689 pin-scl { 690 function = "alt1"; 691 pins = "gpio47"; 692 bias-disable; 693 }; 694 }; 695 i2c3_gpio2: i2c3-gpio2 { 696 pin-sda { 697 function = "alt5"; 698 pins = "gpio2"; 699 bias-pull-up; 700 }; 701 pin-scl { 702 function = "alt5"; 703 pins = "gpio3"; 704 bias-disable; 705 }; 706 }; 707 i2c3_gpio4: i2c3-gpio4 { 708 pin-sda { 709 function = "alt5"; 710 pins = "gpio4"; 711 bias-pull-up; 712 }; 713 pin-scl { 714 function = "alt5"; 715 pins = "gpio5"; 716 bias-disable; 717 }; 718 }; 719 i2c4_gpio6: i2c4-gpio6 { 720 pin-sda { 721 function = "alt5"; 722 pins = "gpio6"; 723 bias-pull-up; 724 }; 725 pin-scl { 726 function = "alt5"; 727 pins = "gpio7"; 728 bias-disable; 729 }; 730 }; 731 i2c4_gpio8: i2c4-gpio8 { 732 pin-sda { 733 function = "alt5"; 734 pins = "gpio8"; 735 bias-pull-up; 736 }; 737 pin-scl { 738 function = "alt5"; 739 pins = "gpio9"; 740 bias-disable; 741 }; 742 }; 743 i2c5_gpio10: i2c5-gpio10 { 744 pin-sda { 745 function = "alt5"; 746 pins = "gpio10"; 747 bias-pull-up; 748 }; 749 pin-scl { 750 function = "alt5"; 751 pins = "gpio11"; 752 bias-disable; 753 }; 754 }; 755 i2c5_gpio12: i2c5-gpio12 { 756 pin-sda { 757 function = "alt5"; 758 pins = "gpio12"; 759 bias-pull-up; 760 }; 761 pin-scl { 762 function = "alt5"; 763 pins = "gpio13"; 764 bias-disable; 765 }; 766 }; 767 i2c6_gpio0: i2c6-gpio0 { 768 pin-sda { 769 function = "alt5"; 770 pins = "gpio0"; 771 bias-pull-up; 772 }; 773 pin-scl { 774 function = "alt5"; 775 pins = "gpio1"; 776 bias-disable; 777 }; 778 }; 779 i2c6_gpio22: i2c6-gpio22 { 780 pin-sda { 781 function = "alt5"; 782 pins = "gpio22"; 783 bias-pull-up; 784 }; 785 pin-scl { 786 function = "alt5"; 787 pins = "gpio23"; 788 bias-disable; 789 }; 790 }; 791 i2c_slave_gpio8: i2c-slave-gpio8 { 792 pins-i2c-slave { 793 pins = "gpio8", 794 "gpio9", 795 "gpio10", 796 "gpio11"; 797 function = "alt3"; 798 }; 799 }; 800 801 jtag_gpio48: jtag-gpio48 { 802 pins-jtag { 803 pins = "gpio48", 804 "gpio49", 805 "gpio50", 806 "gpio51", 807 "gpio52", 808 "gpio53"; 809 function = "alt4"; 810 }; 811 }; 812 813 mii_gpio28: mii-gpio28 { 814 pins-mii { 815 pins = "gpio28", 816 "gpio29", 817 "gpio30", 818 "gpio31"; 819 function = "alt4"; 820 }; 821 }; 822 mii_gpio36: mii-gpio36 { 823 pins-mii { 824 pins = "gpio36", 825 "gpio37", 826 "gpio38", 827 "gpio39"; 828 function = "alt5"; 829 }; 830 }; 831 832 pcm_gpio50: pcm-gpio50 { 833 pins-pcm { 834 pins = "gpio50", 835 "gpio51", 836 "gpio52", 837 "gpio53"; 838 function = "alt2"; 839 }; 840 }; 841 842 pwm0_0_gpio12: pwm0-0-gpio12 { 843 pin-pwm { 844 pins = "gpio12"; 845 function = "alt0"; 846 bias-disable; 847 }; 848 }; 849 pwm0_0_gpio18: pwm0-0-gpio18 { 850 pin-pwm { 851 pins = "gpio18"; 852 function = "alt5"; 853 bias-disable; 854 }; 855 }; 856 pwm1_0_gpio40: pwm1-0-gpio40 { 857 pin-pwm { 858 pins = "gpio40"; 859 function = "alt0"; 860 bias-disable; 861 }; 862 }; 863 pwm0_1_gpio13: pwm0-1-gpio13 { 864 pin-pwm { 865 pins = "gpio13"; 866 function = "alt0"; 867 bias-disable; 868 }; 869 }; 870 pwm0_1_gpio19: pwm0-1-gpio19 { 871 pin-pwm { 872 pins = "gpio19"; 873 function = "alt5"; 874 bias-disable; 875 }; 876 }; 877 pwm1_1_gpio41: pwm1-1-gpio41 { 878 pin-pwm { 879 pins = "gpio41"; 880 function = "alt0"; 881 bias-disable; 882 }; 883 }; 884 pwm0_1_gpio45: pwm0-1-gpio45 { 885 pin-pwm { 886 pins = "gpio45"; 887 function = "alt0"; 888 bias-disable; 889 }; 890 }; 891 pwm0_0_gpio52: pwm0-0-gpio52 { 892 pin-pwm { 893 pins = "gpio52"; 894 function = "alt1"; 895 bias-disable; 896 }; 897 }; 898 pwm0_1_gpio53: pwm0-1-gpio53 { 899 pin-pwm { 900 pins = "gpio53"; 901 function = "alt1"; 902 bias-disable; 903 }; 904 }; 905 906 rgmii_gpio35: rgmii-gpio35 { 907 pin-start-stop { 908 pins = "gpio35"; 909 function = "alt4"; 910 }; 911 pin-rx-ok { 912 pins = "gpio36"; 913 function = "alt4"; 914 }; 915 }; 916 rgmii_irq_gpio34: rgmii-irq-gpio34 { 917 pin-irq { 918 pins = "gpio34"; 919 function = "alt5"; 920 }; 921 }; 922 rgmii_irq_gpio39: rgmii-irq-gpio39 { 923 pin-irq { 924 pins = "gpio39"; 925 function = "alt4"; 926 }; 927 }; 928 rgmii_mdio_gpio28: rgmii-mdio-gpio28 { 929 pins-mdio { 930 pins = "gpio28", 931 "gpio29"; 932 function = "alt5"; 933 }; 934 }; 935 rgmii_mdio_gpio37: rgmii-mdio-gpio37 { 936 pins-mdio { 937 pins = "gpio37", 938 "gpio38"; 939 function = "alt4"; 940 }; 941 }; 942 943 spi0_gpio46: spi0-gpio46 { 944 pins-spi { 945 pins = "gpio46", 946 "gpio47", 947 "gpio48", 948 "gpio49"; 949 function = "alt2"; 950 }; 951 }; 952 spi2_gpio46: spi2-gpio46 { 953 pins-spi { 954 pins = "gpio46", 955 "gpio47", 956 "gpio48", 957 "gpio49", 958 "gpio50"; 959 function = "alt5"; 960 }; 961 }; 962 spi3_gpio0: spi3-gpio0 { 963 pins-spi { 964 pins = "gpio0", 965 "gpio1", 966 "gpio2", 967 "gpio3"; 968 function = "alt3"; 969 }; 970 }; 971 spi4_gpio4: spi4-gpio4 { 972 pins-spi { 973 pins = "gpio4", 974 "gpio5", 975 "gpio6", 976 "gpio7"; 977 function = "alt3"; 978 }; 979 }; 980 spi5_gpio12: spi5-gpio12 { 981 pins-spi { 982 pins = "gpio12", 983 "gpio13", 984 "gpio14", 985 "gpio15"; 986 function = "alt3"; 987 }; 988 }; 989 spi6_gpio18: spi6-gpio18 { 990 pins-spi { 991 pins = "gpio18", 992 "gpio19", 993 "gpio20", 994 "gpio21"; 995 function = "alt3"; 996 }; 997 }; 998 999 uart2_gpio0: uart2-gpio0 { 1000 pin-tx { 1001 pins = "gpio0"; 1002 function = "alt4"; 1003 bias-disable; 1004 }; 1005 pin-rx { 1006 pins = "gpio1"; 1007 function = "alt4"; 1008 bias-pull-up; 1009 }; 1010 }; 1011 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { 1012 pin-cts { 1013 pins = "gpio2"; 1014 function = "alt4"; 1015 bias-pull-up; 1016 }; 1017 pin-rts { 1018 pins = "gpio3"; 1019 function = "alt4"; 1020 bias-disable; 1021 }; 1022 }; 1023 uart3_gpio4: uart3-gpio4 { 1024 pin-tx { 1025 pins = "gpio4"; 1026 function = "alt4"; 1027 bias-disable; 1028 }; 1029 pin-rx { 1030 pins = "gpio5"; 1031 function = "alt4"; 1032 bias-pull-up; 1033 }; 1034 }; 1035 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { 1036 pin-cts { 1037 pins = "gpio6"; 1038 function = "alt4"; 1039 bias-pull-up; 1040 }; 1041 pin-rts { 1042 pins = "gpio7"; 1043 function = "alt4"; 1044 bias-disable; 1045 }; 1046 }; 1047 uart4_gpio8: uart4-gpio8 { 1048 pin-tx { 1049 pins = "gpio8"; 1050 function = "alt4"; 1051 bias-disable; 1052 }; 1053 pin-rx { 1054 pins = "gpio9"; 1055 function = "alt4"; 1056 bias-pull-up; 1057 }; 1058 }; 1059 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { 1060 pin-cts { 1061 pins = "gpio10"; 1062 function = "alt4"; 1063 bias-pull-up; 1064 }; 1065 pin-rts { 1066 pins = "gpio11"; 1067 function = "alt4"; 1068 bias-disable; 1069 }; 1070 }; 1071 uart5_gpio12: uart5-gpio12 { 1072 pin-tx { 1073 pins = "gpio12"; 1074 function = "alt4"; 1075 bias-disable; 1076 }; 1077 pin-rx { 1078 pins = "gpio13"; 1079 function = "alt4"; 1080 bias-pull-up; 1081 }; 1082 }; 1083 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { 1084 pin-cts { 1085 pins = "gpio14"; 1086 function = "alt4"; 1087 bias-pull-up; 1088 }; 1089 pin-rts { 1090 pins = "gpio15"; 1091 function = "alt4"; 1092 bias-disable; 1093 }; 1094 }; 1095}; 1096 1097&rmem { 1098 #address-cells = <2>; 1099}; 1100 1101&cma { 1102 /* 1103 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1104 * that's not good enough for the BCM2711 as some devices can 1105 * only address the lower 1G of memory (ZONE_DMA). 1106 */ 1107 alloc-ranges = <0x0 0x00000000 0x40000000>; 1108}; 1109 1110&i2c0 { 1111 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1112 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1113}; 1114 1115&i2c1 { 1116 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1117 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1118}; 1119 1120&mailbox { 1121 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1122}; 1123 1124&sdhci { 1125 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1126}; 1127 1128&sdhost { 1129 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1130}; 1131 1132&spi { 1133 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1134}; 1135 1136&spi1 { 1137 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1138}; 1139 1140&spi2 { 1141 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1142}; 1143 1144&system_timer { 1145 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1149}; 1150 1151&txp { 1152 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1153}; 1154 1155&uart0 { 1156 arm,primecell-periphid = <0x00341011>; 1157 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1158}; 1159 1160&uart1 { 1161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1162}; 1163 1164&usb { 1165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1166}; 1167 1168&vec { 1169 compatible = "brcm,bcm2711-vec"; 1170 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1171}; 1172