xref: /openbmc/u-boot/include/linux/usb/dwc3.h (revision e8f80a5a) 
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* include/linux/usb/dwc3.h
3  *
4  * Copyright (c) 2012 Samsung Electronics Co. Ltd
5  *
6  * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
7  */
8 
9 #ifndef __DWC3_H_
10 #define __DWC3_H_
11 
12 /* Global constants */
13 #define DWC3_ENDPOINTS_NUM			32
14 
15 #define DWC3_EVENT_BUFFERS_SIZE			PAGE_SIZE
16 #define DWC3_EVENT_TYPE_MASK			0xfe
17 
18 #define DWC3_EVENT_TYPE_DEV			0
19 #define DWC3_EVENT_TYPE_CARKIT			3
20 #define DWC3_EVENT_TYPE_I2C			4
21 
22 #define DWC3_DEVICE_EVENT_DISCONNECT		0
23 #define DWC3_DEVICE_EVENT_RESET			1
24 #define DWC3_DEVICE_EVENT_CONNECT_DONE		2
25 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
26 #define DWC3_DEVICE_EVENT_WAKEUP		4
27 #define DWC3_DEVICE_EVENT_EOPF			6
28 #define DWC3_DEVICE_EVENT_SOF			7
29 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
30 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
31 #define DWC3_DEVICE_EVENT_OVERFLOW		11
32 
33 #define DWC3_GEVNTCOUNT_MASK			0xfffc
34 #define DWC3_GSNPSID_MASK			0xffff0000
35 #define DWC3_GSNPSID_SHIFT			16
36 #define DWC3_GSNPSREV_MASK			0xffff
37 
38 #define DWC3_REVISION_MASK			0xffff
39 
40 #define DWC3_REG_OFFSET				0xC100
41 
42 struct g_event_buffer {
43 	u32 g_evntadrlo;
44 	u32 g_evntadrhi;
45 	u32 g_evntsiz;
46 	u32 g_evntcount;
47 };
48 
49 struct d_physical_endpoint {
50 	u32 d_depcmdpar2;
51 	u32 d_depcmdpar1;
52 	u32 d_depcmdpar0;
53 	u32 d_depcmd;
54 };
55 
56 struct dwc3 {					/* offset: 0xC100 */
57 	u32 g_sbuscfg0;
58 	u32 g_sbuscfg1;
59 	u32 g_txthrcfg;
60 	u32 g_rxthrcfg;
61 	u32 g_ctl;
62 
63 	u32 reserved1;
64 
65 	u32 g_sts;
66 
67 	u32 reserved2;
68 
69 	u32 g_snpsid;
70 	u32 g_gpio;
71 	u32 g_uid;
72 	u32 g_uctl;
73 	u64 g_buserraddr;
74 	u64 g_prtbimap;
75 
76 	u32 g_hwparams0;
77 	u32 g_hwparams1;
78 	u32 g_hwparams2;
79 	u32 g_hwparams3;
80 	u32 g_hwparams4;
81 	u32 g_hwparams5;
82 	u32 g_hwparams6;
83 	u32 g_hwparams7;
84 
85 	u32 g_dbgfifospace;
86 	u32 g_dbgltssm;
87 	u32 g_dbglnmcc;
88 	u32 g_dbgbmu;
89 	u32 g_dbglspmux;
90 	u32 g_dbglsp;
91 	u32 g_dbgepinfo0;
92 	u32 g_dbgepinfo1;
93 
94 	u64 g_prtbimap_hs;
95 	u64 g_prtbimap_fs;
96 
97 	u32 reserved3[28];
98 
99 	u32 g_usb2phycfg[16];
100 	u32 g_usb2i2cctl[16];
101 	u32 g_usb2phyacc[16];
102 	u32 g_usb3pipectl[16];
103 
104 	u32 g_txfifosiz[32];
105 	u32 g_rxfifosiz[32];
106 
107 	struct g_event_buffer g_evnt_buf[32];
108 
109 	u32 g_hwparams8;
110 
111 	u32 reserved4[11];
112 
113 	u32 g_fladj;
114 
115 	u32 reserved5[51];
116 
117 	u32 d_cfg;
118 	u32 d_ctl;
119 	u32 d_evten;
120 	u32 d_sts;
121 	u32 d_gcmdpar;
122 	u32 d_gcmd;
123 
124 	u32 reserved6[2];
125 
126 	u32 d_alepena;
127 
128 	u32 reserved7[55];
129 
130 	struct d_physical_endpoint d_phy_ep_cmd[32];
131 
132 	u32 reserved8[128];
133 
134 	u32 o_cfg;
135 	u32 o_ctl;
136 	u32 o_evt;
137 	u32 o_evten;
138 	u32 o_sts;
139 
140 	u32 reserved9[3];
141 
142 	u32 adp_cfg;
143 	u32 adp_ctl;
144 	u32 adp_evt;
145 	u32 adp_evten;
146 
147 	u32 bc_cfg;
148 
149 	u32 reserved10;
150 
151 	u32 bc_evt;
152 	u32 bc_evten;
153 };
154 
155 /* Global Configuration Register */
156 #define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
157 #define DWC3_GCTL_U2RSTECN			(1 << 16)
158 #define DWC3_GCTL_RAMCLKSEL(x)			\
159 		(((x) & DWC3_GCTL_CLK_MASK) << 6)
160 #define DWC3_GCTL_CLK_BUS			(0)
161 #define DWC3_GCTL_CLK_PIPE			(1)
162 #define DWC3_GCTL_CLK_PIPEHALF			(2)
163 #define DWC3_GCTL_CLK_MASK			(3)
164 #define DWC3_GCTL_PRTCAP(n)			(((n) & (3 << 12)) >> 12)
165 #define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
166 #define DWC3_GCTL_PRTCAP_HOST			1
167 #define DWC3_GCTL_PRTCAP_DEVICE			2
168 #define DWC3_GCTL_PRTCAP_OTG			3
169 #define DWC3_GCTL_CORESOFTRESET			(1 << 11)
170 #define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
171 #define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
172 #define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
173 #define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
174 
175 /* Global HWPARAMS1 Register */
176 #define DWC3_GHWPARAMS1_EN_PWROPT(n)		(((n) & (3 << 24)) >> 24)
177 #define DWC3_GHWPARAMS1_EN_PWROPT_NO		0
178 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK		1
179 
180 /* Global USB2 PHY Configuration Register */
181 #define DWC3_GUSB2PHYCFG_PHYSOFTRST		(1 << 31)
182 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
183 #define DWC3_GUSB2PHYCFG_ENBLSLPM		(1 << 8)
184 #define DWC3_GUSB2PHYCFG_SUSPHY			(1 << 6)
185 #define DWC3_GUSB2PHYCFG_PHYIF			(1 << 3)
186 
187 /* Global USB2 PHY Configuration Mask */
188 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK		(0xf << 10)
189 
190 /* Global USB2 PHY Configuration Offset */
191 #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET	10
192 
193 #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
194 		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
195 #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
196 		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
197 
198 /* Global USB3 PIPE Control Register */
199 #define DWC3_GUSB3PIPECTL_PHYSOFTRST		(1 << 31)
200 #define DWC3_GUSB3PIPECTL_DISRXDETP3		(1 << 28)
201 #define DWC3_GUSB3PIPECTL_SUSPHY		(1 << 17)
202 
203 /* Global TX Fifo Size Register */
204 #define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
205 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)
206 
207 /* Device Control Register */
208 #define DWC3_DCTL_RUN_STOP			(1 << 31)
209 #define DWC3_DCTL_CSFTRST			(1 << 30)
210 #define DWC3_DCTL_LSFTRST			(1 << 29)
211 
212 /* Global Frame Length Adjustment Register */
213 #define GFLADJ_30MHZ_REG_SEL			(1 << 7)
214 #define GFLADJ_30MHZ(n)				((n) & 0x3f)
215 #define GFLADJ_30MHZ_DEFAULT			0x20
216 
217 #ifdef CONFIG_USB_XHCI_DWC3
218 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
219 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
220 int dwc3_core_init(struct dwc3 *dwc3_reg);
221 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
222 #endif
223 #endif /* __DWC3_H_ */
224