1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <net/addrconf.h>
40 #include <rdma/ib_addr.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/uverbs_ioctl.h>
44
45 #include "hnae3.h"
46 #include "hns_roce_common.h"
47 #include "hns_roce_device.h"
48 #include "hns_roce_cmd.h"
49 #include "hns_roce_hem.h"
50 #include "hns_roce_hw_v2.h"
51
52 enum {
53 CMD_RST_PRC_OTHERS,
54 CMD_RST_PRC_SUCCESS,
55 CMD_RST_PRC_EBUSY,
56 };
57
58 enum ecc_resource_type {
59 ECC_RESOURCE_QPC,
60 ECC_RESOURCE_CQC,
61 ECC_RESOURCE_MPT,
62 ECC_RESOURCE_SRQC,
63 ECC_RESOURCE_GMV,
64 ECC_RESOURCE_QPC_TIMER,
65 ECC_RESOURCE_CQC_TIMER,
66 ECC_RESOURCE_SCCC,
67 ECC_RESOURCE_COUNT,
68 };
69
70 static const struct {
71 const char *name;
72 u8 read_bt0_op;
73 u8 write_bt0_op;
74 } fmea_ram_res[] = {
75 { "ECC_RESOURCE_QPC",
76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
77 { "ECC_RESOURCE_CQC",
78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
79 { "ECC_RESOURCE_MPT",
80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
81 { "ECC_RESOURCE_SRQC",
82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
84 { "ECC_RESOURCE_GMV",
85 0, 0 },
86 { "ECC_RESOURCE_QPC_TIMER",
87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
88 { "ECC_RESOURCE_CQC_TIMER",
89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
90 { "ECC_RESOURCE_SCCC",
91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
92 };
93
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
95 struct ib_sge *sg)
96 {
97 dseg->lkey = cpu_to_le32(sg->lkey);
98 dseg->addr = cpu_to_le64(sg->addr);
99 dseg->len = cpu_to_le32(sg->length);
100 }
101
102 /*
103 * mapped-value = 1 + real-value
104 * The hns wr opcode real value is start from 0, In order to distinguish between
105 * initialized and uninitialized map values, we plus 1 to the actual value when
106 * defining the mapping, so that the validity can be identified by checking the
107 * mapped value is greater than 0.
108 */
109 #define HR_OPC_MAP(ib_key, hr_key) \
110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
111
112 static const u32 hns_roce_op_code[] = {
113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
115 HR_OPC_MAP(SEND, SEND),
116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
117 HR_OPC_MAP(RDMA_READ, RDMA_READ),
118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
123 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
124 };
125
to_hr_opcode(u32 ib_opcode)126 static u32 to_hr_opcode(u32 ib_opcode)
127 {
128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
129 return HNS_ROCE_V2_WQE_OP_MASK;
130
131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
132 HNS_ROCE_V2_WQE_OP_MASK;
133 }
134
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
136 const struct ib_reg_wr *wr)
137 {
138 struct hns_roce_wqe_frmr_seg *fseg =
139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
140 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
141 u64 pbl_ba;
142
143 /* use ib_access_flags */
144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
145 hr_reg_write_bool(fseg, FRMR_ATOMIC,
146 wr->access & IB_ACCESS_REMOTE_ATOMIC);
147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
150
151 /* Data structure reuse may lead to confusion */
152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
155
156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
158 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
160
161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
164 hr_reg_clear(fseg, FRMR_BLK_MODE);
165 }
166
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)167 static void set_atomic_seg(const struct ib_send_wr *wr,
168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
169 unsigned int valid_num_sge)
170 {
171 struct hns_roce_v2_wqe_data_seg *dseg =
172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
173 struct hns_roce_wqe_atomic_seg *aseg =
174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
175
176 set_data_seg_v2(dseg, wr->sg_list);
177
178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
181 } else {
182 aseg->fetchadd_swap_data =
183 cpu_to_le64(atomic_wr(wr)->compare_add);
184 aseg->cmp_data = 0;
185 }
186
187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
188 }
189
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
191 const struct ib_send_wr *wr,
192 unsigned int *sge_idx, u32 msg_len)
193 {
194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
195 unsigned int left_len_in_pg;
196 unsigned int idx = *sge_idx;
197 unsigned int i = 0;
198 unsigned int len;
199 void *addr;
200 void *dseg;
201
202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
203 ibdev_err(ibdev,
204 "no enough extended sge space for inline data.\n");
205 return -EINVAL;
206 }
207
208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
210 len = wr->sg_list[0].length;
211 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
212
213 /* When copying data to extended sge space, the left length in page may
214 * not long enough for current user's sge. So the data should be
215 * splited into several parts, one in the first page, and the others in
216 * the subsequent pages.
217 */
218 while (1) {
219 if (len <= left_len_in_pg) {
220 memcpy(dseg, addr, len);
221
222 idx += len / HNS_ROCE_SGE_SIZE;
223
224 i++;
225 if (i >= wr->num_sge)
226 break;
227
228 left_len_in_pg -= len;
229 len = wr->sg_list[i].length;
230 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
231 dseg += len;
232 } else {
233 memcpy(dseg, addr, left_len_in_pg);
234
235 len -= left_len_in_pg;
236 addr += left_len_in_pg;
237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
238 dseg = hns_roce_get_extend_sge(qp,
239 idx & (qp->sge.sge_cnt - 1));
240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
241 }
242 }
243
244 *sge_idx = idx;
245
246 return 0;
247 }
248
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
250 unsigned int *sge_ind, unsigned int cnt)
251 {
252 struct hns_roce_v2_wqe_data_seg *dseg;
253 unsigned int idx = *sge_ind;
254
255 while (cnt > 0) {
256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
257 if (likely(sge->length)) {
258 set_data_seg_v2(dseg, sge);
259 idx++;
260 cnt--;
261 }
262 sge++;
263 }
264
265 *sge_ind = idx;
266 }
267
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
269 {
270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
271 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
272
273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
274 ibdev_err(&hr_dev->ib_dev,
275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
276 len, qp->max_inline_data, mtu);
277 return false;
278 }
279
280 return true;
281 }
282
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
285 unsigned int *sge_idx)
286 {
287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
289 struct ib_device *ibdev = &hr_dev->ib_dev;
290 unsigned int curr_idx = *sge_idx;
291 void *dseg = rc_sq_wqe;
292 unsigned int i;
293 int ret;
294
295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
296 ibdev_err(ibdev, "invalid inline parameters!\n");
297 return -EINVAL;
298 }
299
300 if (!check_inl_data_len(qp, msg_len))
301 return -EINVAL;
302
303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
304
305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
307
308 for (i = 0; i < wr->num_sge; i++) {
309 memcpy(dseg, ((void *)wr->sg_list[i].addr),
310 wr->sg_list[i].length);
311 dseg += wr->sg_list[i].length;
312 }
313 } else {
314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
315
316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
317 if (ret)
318 return ret;
319
320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
321 }
322
323 *sge_idx = curr_idx;
324
325 return 0;
326 }
327
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
330 unsigned int *sge_ind,
331 unsigned int valid_num_sge)
332 {
333 struct hns_roce_v2_wqe_data_seg *dseg =
334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
335 struct hns_roce_qp *qp = to_hr_qp(ibqp);
336 int j = 0;
337 int i;
338
339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
340 (*sge_ind) & (qp->sge.sge_cnt - 1));
341
342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
343 !!(wr->send_flags & IB_SEND_INLINE));
344 if (wr->send_flags & IB_SEND_INLINE)
345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
346
347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
348 for (i = 0; i < wr->num_sge; i++) {
349 if (likely(wr->sg_list[i].length)) {
350 set_data_seg_v2(dseg, wr->sg_list + i);
351 dseg++;
352 }
353 }
354 } else {
355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
356 if (likely(wr->sg_list[i].length)) {
357 set_data_seg_v2(dseg, wr->sg_list + i);
358 dseg++;
359 j++;
360 }
361 }
362
363 set_extend_sge(qp, wr->sg_list + i, sge_ind,
364 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
365 }
366
367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
368
369 return 0;
370 }
371
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)372 static int check_send_valid(struct hns_roce_dev *hr_dev,
373 struct hns_roce_qp *hr_qp)
374 {
375 struct ib_device *ibdev = &hr_dev->ib_dev;
376
377 if (unlikely(hr_qp->state == IB_QPS_RESET ||
378 hr_qp->state == IB_QPS_INIT ||
379 hr_qp->state == IB_QPS_RTR)) {
380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
381 hr_qp->state);
382 return -EINVAL;
383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
385 hr_dev->state);
386 return -EIO;
387 }
388
389 return 0;
390 }
391
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)392 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
393 unsigned int *sge_len)
394 {
395 unsigned int valid_num = 0;
396 unsigned int len = 0;
397 int i;
398
399 for (i = 0; i < wr->num_sge; i++) {
400 if (likely(wr->sg_list[i].length)) {
401 len += wr->sg_list[i].length;
402 valid_num++;
403 }
404 }
405
406 *sge_len = len;
407 return valid_num;
408 }
409
get_immtdata(const struct ib_send_wr * wr)410 static __le32 get_immtdata(const struct ib_send_wr *wr)
411 {
412 switch (wr->opcode) {
413 case IB_WR_SEND_WITH_IMM:
414 case IB_WR_RDMA_WRITE_WITH_IMM:
415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
416 default:
417 return 0;
418 }
419 }
420
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)421 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
422 const struct ib_send_wr *wr)
423 {
424 u32 ib_op = wr->opcode;
425
426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
427 return -EINVAL;
428
429 ud_sq_wqe->immtdata = get_immtdata(wr);
430
431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
432
433 return 0;
434 }
435
fill_ud_av(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,struct hns_roce_ah * ah)436 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
437 struct hns_roce_ah *ah)
438 {
439 struct ib_device *ib_dev = ah->ibah.device;
440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
441
442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
446
447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
448 return -EINVAL;
449
450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
451
452 ud_sq_wqe->sgid_index = ah->av.gid_index;
453
454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
456
457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
458 return 0;
459
460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
462
463 return 0;
464 }
465
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)466 static inline int set_ud_wqe(struct hns_roce_qp *qp,
467 const struct ib_send_wr *wr,
468 void *wqe, unsigned int *sge_idx,
469 unsigned int owner_bit)
470 {
471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
473 unsigned int curr_idx = *sge_idx;
474 unsigned int valid_num_sge;
475 u32 msg_len = 0;
476 int ret;
477
478 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
479
480 ret = set_ud_opcode(ud_sq_wqe, wr);
481 if (WARN_ON(ret))
482 return ret;
483
484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
485
486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
487 !!(wr->send_flags & IB_SEND_SIGNALED));
488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
489 !!(wr->send_flags & IB_SEND_SOLICITED));
490
491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
494 curr_idx & (qp->sge.sge_cnt - 1));
495
496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
497 qp->qkey : ud_wr(wr)->remote_qkey);
498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
499
500 ret = fill_ud_av(ud_sq_wqe, ah);
501 if (ret)
502 return ret;
503
504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
505
506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
507
508 /*
509 * The pipeline can sequentially post all valid WQEs into WQ buffer,
510 * including new WQEs waiting for the doorbell to update the PI again.
511 * Therefore, the owner bit of WQE MUST be updated after all fields
512 * and extSGEs have been written into DDR instead of cache.
513 */
514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
515 dma_wmb();
516
517 *sge_idx = curr_idx;
518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
519
520 return 0;
521 }
522
set_rc_opcode(struct hns_roce_dev * hr_dev,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)523 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
525 const struct ib_send_wr *wr)
526 {
527 u32 ib_op = wr->opcode;
528 int ret = 0;
529
530 rc_sq_wqe->immtdata = get_immtdata(wr);
531
532 switch (ib_op) {
533 case IB_WR_RDMA_READ:
534 case IB_WR_RDMA_WRITE:
535 case IB_WR_RDMA_WRITE_WITH_IMM:
536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
538 break;
539 case IB_WR_SEND:
540 case IB_WR_SEND_WITH_IMM:
541 break;
542 case IB_WR_ATOMIC_CMP_AND_SWP:
543 case IB_WR_ATOMIC_FETCH_AND_ADD:
544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
546 break;
547 case IB_WR_REG_MR:
548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
549 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
550 else
551 ret = -EOPNOTSUPP;
552 break;
553 case IB_WR_SEND_WITH_INV:
554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
555 break;
556 default:
557 ret = -EINVAL;
558 }
559
560 if (unlikely(ret))
561 return ret;
562
563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
564
565 return ret;
566 }
567
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)568 static inline int set_rc_wqe(struct hns_roce_qp *qp,
569 const struct ib_send_wr *wr,
570 void *wqe, unsigned int *sge_idx,
571 unsigned int owner_bit)
572 {
573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
575 unsigned int curr_idx = *sge_idx;
576 unsigned int valid_num_sge;
577 u32 msg_len = 0;
578 int ret;
579
580 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
581
582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
583
584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
585 if (WARN_ON(ret))
586 return ret;
587
588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE,
589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
590
591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
593
594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
596
597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
599 if (msg_len != ATOMIC_WR_LEN)
600 return -EINVAL;
601 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
602 } else if (wr->opcode != IB_WR_REG_MR) {
603 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
604 &curr_idx, valid_num_sge);
605 if (ret)
606 return ret;
607 }
608
609 /*
610 * The pipeline can sequentially post all valid WQEs into WQ buffer,
611 * including new WQEs waiting for the doorbell to update the PI again.
612 * Therefore, the owner bit of WQE MUST be updated after all fields
613 * and extSGEs have been written into DDR instead of cache.
614 */
615 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
616 dma_wmb();
617
618 *sge_idx = curr_idx;
619 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
620
621 return ret;
622 }
623
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)624 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
625 struct hns_roce_qp *qp)
626 {
627 if (unlikely(qp->state == IB_QPS_ERR)) {
628 flush_cqe(hr_dev, qp);
629 } else {
630 struct hns_roce_v2_db sq_db = {};
631
632 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
633 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
634 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
635 hr_reg_write(&sq_db, DB_SL, qp->sl);
636
637 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
638 }
639 }
640
update_rq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)641 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
642 struct hns_roce_qp *qp)
643 {
644 if (unlikely(qp->state == IB_QPS_ERR)) {
645 flush_cqe(hr_dev, qp);
646 } else {
647 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
648 *qp->rdb.db_record =
649 qp->rq.head & V2_DB_PRODUCER_IDX_M;
650 } else {
651 struct hns_roce_v2_db rq_db = {};
652
653 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
654 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
655 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
656
657 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
658 qp->rq.db_reg);
659 }
660 }
661 }
662
hns_roce_write512(struct hns_roce_dev * hr_dev,u64 * val,u64 __iomem * dest)663 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
664 u64 __iomem *dest)
665 {
666 #define HNS_ROCE_WRITE_TIMES 8
667 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
668 struct hnae3_handle *handle = priv->handle;
669 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
670 int i;
671
672 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
673 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
674 writeq_relaxed(*(val + i), dest + i);
675 }
676
write_dwqe(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,void * wqe)677 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
678 void *wqe)
679 {
680 #define HNS_ROCE_SL_SHIFT 2
681 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
682
683 /* All kinds of DirectWQE have the same header field layout */
684 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
685 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
686 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
687 qp->sl >> HNS_ROCE_SL_SHIFT);
688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
689
690 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
691 }
692
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)693 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
694 const struct ib_send_wr *wr,
695 const struct ib_send_wr **bad_wr)
696 {
697 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
698 struct ib_device *ibdev = &hr_dev->ib_dev;
699 struct hns_roce_qp *qp = to_hr_qp(ibqp);
700 unsigned long flags = 0;
701 unsigned int owner_bit;
702 unsigned int sge_idx;
703 unsigned int wqe_idx;
704 void *wqe = NULL;
705 u32 nreq;
706 int ret;
707
708 spin_lock_irqsave(&qp->sq.lock, flags);
709
710 ret = check_send_valid(hr_dev, qp);
711 if (unlikely(ret)) {
712 *bad_wr = wr;
713 nreq = 0;
714 goto out;
715 }
716
717 sge_idx = qp->next_sge;
718
719 for (nreq = 0; wr; ++nreq, wr = wr->next) {
720 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
721 ret = -ENOMEM;
722 *bad_wr = wr;
723 goto out;
724 }
725
726 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
727
728 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
729 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
730 wr->num_sge, qp->sq.max_gs);
731 ret = -EINVAL;
732 *bad_wr = wr;
733 goto out;
734 }
735
736 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
737 qp->sq.wrid[wqe_idx] = wr->wr_id;
738 owner_bit =
739 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
740
741 /* Corresponding to the QP type, wqe process separately */
742 if (ibqp->qp_type == IB_QPT_RC)
743 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
744 else
745 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
746
747 if (unlikely(ret)) {
748 *bad_wr = wr;
749 goto out;
750 }
751 }
752
753 out:
754 if (likely(nreq)) {
755 qp->sq.head += nreq;
756 qp->next_sge = sge_idx;
757
758 if (nreq == 1 && !ret &&
759 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
760 write_dwqe(hr_dev, qp, wqe);
761 else
762 update_sq_db(hr_dev, qp);
763 }
764
765 spin_unlock_irqrestore(&qp->sq.lock, flags);
766
767 return ret;
768 }
769
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)770 static int check_recv_valid(struct hns_roce_dev *hr_dev,
771 struct hns_roce_qp *hr_qp)
772 {
773 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
774 return -EIO;
775
776 if (hr_qp->state == IB_QPS_RESET)
777 return -EINVAL;
778
779 return 0;
780 }
781
fill_recv_sge_to_wqe(const struct ib_recv_wr * wr,void * wqe,u32 max_sge,bool rsv)782 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
783 u32 max_sge, bool rsv)
784 {
785 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
786 u32 i, cnt;
787
788 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
789 /* Skip zero-length sge */
790 if (!wr->sg_list[i].length)
791 continue;
792 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
793 cnt++;
794 }
795
796 /* Fill a reserved sge to make hw stop reading remaining segments */
797 if (rsv) {
798 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
799 dseg[cnt].addr = 0;
800 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
801 } else {
802 /* Clear remaining segments to make ROCEE ignore sges */
803 if (cnt < max_sge)
804 memset(dseg + cnt, 0,
805 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
806 }
807 }
808
fill_rq_wqe(struct hns_roce_qp * hr_qp,const struct ib_recv_wr * wr,u32 wqe_idx,u32 max_sge)809 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
810 u32 wqe_idx, u32 max_sge)
811 {
812 void *wqe = NULL;
813
814 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
815 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
816 }
817
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)818 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
819 const struct ib_recv_wr *wr,
820 const struct ib_recv_wr **bad_wr)
821 {
822 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
823 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
824 struct ib_device *ibdev = &hr_dev->ib_dev;
825 u32 wqe_idx, nreq, max_sge;
826 unsigned long flags;
827 int ret;
828
829 spin_lock_irqsave(&hr_qp->rq.lock, flags);
830
831 ret = check_recv_valid(hr_dev, hr_qp);
832 if (unlikely(ret)) {
833 *bad_wr = wr;
834 nreq = 0;
835 goto out;
836 }
837
838 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
839 for (nreq = 0; wr; ++nreq, wr = wr->next) {
840 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
841 hr_qp->ibqp.recv_cq))) {
842 ret = -ENOMEM;
843 *bad_wr = wr;
844 goto out;
845 }
846
847 if (unlikely(wr->num_sge > max_sge)) {
848 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
849 wr->num_sge, max_sge);
850 ret = -EINVAL;
851 *bad_wr = wr;
852 goto out;
853 }
854
855 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
856 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
857 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
858 }
859
860 out:
861 if (likely(nreq)) {
862 hr_qp->rq.head += nreq;
863
864 update_rq_db(hr_dev, hr_qp);
865 }
866 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
867
868 return ret;
869 }
870
get_srq_wqe_buf(struct hns_roce_srq * srq,u32 n)871 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
872 {
873 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
874 }
875
get_idx_buf(struct hns_roce_idx_que * idx_que,u32 n)876 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
877 {
878 return hns_roce_buf_offset(idx_que->mtr.kmem,
879 n << idx_que->entry_shift);
880 }
881
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,u32 wqe_index)882 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
883 {
884 /* always called with interrupts disabled. */
885 spin_lock(&srq->lock);
886
887 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
888 srq->idx_que.tail++;
889
890 spin_unlock(&srq->lock);
891 }
892
hns_roce_srqwq_overflow(struct hns_roce_srq * srq)893 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
894 {
895 struct hns_roce_idx_que *idx_que = &srq->idx_que;
896
897 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
898 }
899
check_post_srq_valid(struct hns_roce_srq * srq,u32 max_sge,const struct ib_recv_wr * wr)900 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
901 const struct ib_recv_wr *wr)
902 {
903 struct ib_device *ib_dev = srq->ibsrq.device;
904
905 if (unlikely(wr->num_sge > max_sge)) {
906 ibdev_err(ib_dev,
907 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
908 wr->num_sge, max_sge);
909 return -EINVAL;
910 }
911
912 if (unlikely(hns_roce_srqwq_overflow(srq))) {
913 ibdev_err(ib_dev,
914 "failed to check srqwq status, srqwq is full.\n");
915 return -ENOMEM;
916 }
917
918 return 0;
919 }
920
get_srq_wqe_idx(struct hns_roce_srq * srq,u32 * wqe_idx)921 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
922 {
923 struct hns_roce_idx_que *idx_que = &srq->idx_que;
924 u32 pos;
925
926 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
927 if (unlikely(pos == srq->wqe_cnt))
928 return -ENOSPC;
929
930 bitmap_set(idx_que->bitmap, pos, 1);
931 *wqe_idx = pos;
932 return 0;
933 }
934
fill_wqe_idx(struct hns_roce_srq * srq,unsigned int wqe_idx)935 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
936 {
937 struct hns_roce_idx_que *idx_que = &srq->idx_que;
938 unsigned int head;
939 __le32 *buf;
940
941 head = idx_que->head & (srq->wqe_cnt - 1);
942
943 buf = get_idx_buf(idx_que, head);
944 *buf = cpu_to_le32(wqe_idx);
945
946 idx_que->head++;
947 }
948
update_srq_db(struct hns_roce_v2_db * db,struct hns_roce_srq * srq)949 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
950 {
951 hr_reg_write(db, DB_TAG, srq->srqn);
952 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
953 hr_reg_write(db, DB_PI, srq->idx_que.head);
954 }
955
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)956 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
957 const struct ib_recv_wr *wr,
958 const struct ib_recv_wr **bad_wr)
959 {
960 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
961 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
962 struct hns_roce_v2_db srq_db;
963 unsigned long flags;
964 int ret = 0;
965 u32 max_sge;
966 u32 wqe_idx;
967 void *wqe;
968 u32 nreq;
969
970 spin_lock_irqsave(&srq->lock, flags);
971
972 max_sge = srq->max_gs - srq->rsv_sge;
973 for (nreq = 0; wr; ++nreq, wr = wr->next) {
974 ret = check_post_srq_valid(srq, max_sge, wr);
975 if (ret) {
976 *bad_wr = wr;
977 break;
978 }
979
980 ret = get_srq_wqe_idx(srq, &wqe_idx);
981 if (unlikely(ret)) {
982 *bad_wr = wr;
983 break;
984 }
985
986 wqe = get_srq_wqe_buf(srq, wqe_idx);
987 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
988 fill_wqe_idx(srq, wqe_idx);
989 srq->wrid[wqe_idx] = wr->wr_id;
990 }
991
992 if (likely(nreq)) {
993 update_srq_db(&srq_db, srq);
994
995 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
996 }
997
998 spin_unlock_irqrestore(&srq->lock, flags);
999
1000 return ret;
1001 }
1002
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1003 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1004 unsigned long instance_stage,
1005 unsigned long reset_stage)
1006 {
1007 /* When hardware reset has been completed once or more, we should stop
1008 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1009 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1010 * stage of soft reset process, we should exit with error, and then
1011 * HNAE3_INIT_CLIENT related process can rollback the operation like
1012 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1013 * process will exit with error to notify NIC driver to reschedule soft
1014 * reset process once again.
1015 */
1016 hr_dev->is_reset = true;
1017 hr_dev->dis_db = true;
1018
1019 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1020 instance_stage == HNS_ROCE_STATE_INIT)
1021 return CMD_RST_PRC_EBUSY;
1022
1023 return CMD_RST_PRC_SUCCESS;
1024 }
1025
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1026 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1027 unsigned long instance_stage,
1028 unsigned long reset_stage)
1029 {
1030 #define HW_RESET_TIMEOUT_US 1000000
1031 #define HW_RESET_SLEEP_US 1000
1032
1033 struct hns_roce_v2_priv *priv = hr_dev->priv;
1034 struct hnae3_handle *handle = priv->handle;
1035 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1036 unsigned long val;
1037 int ret;
1038
1039 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1040 * doorbell to hardware. If now in .init_instance() function, we should
1041 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1042 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1043 * related process can rollback the operation like notifing hardware to
1044 * free resources, HNAE3_INIT_CLIENT related process will exit with
1045 * error to notify NIC driver to reschedule soft reset process once
1046 * again.
1047 */
1048 hr_dev->dis_db = true;
1049
1050 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1051 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1052 HW_RESET_TIMEOUT_US, false, handle);
1053 if (!ret)
1054 hr_dev->is_reset = true;
1055
1056 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1057 instance_stage == HNS_ROCE_STATE_INIT)
1058 return CMD_RST_PRC_EBUSY;
1059
1060 return CMD_RST_PRC_SUCCESS;
1061 }
1062
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1063 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1064 {
1065 struct hns_roce_v2_priv *priv = hr_dev->priv;
1066 struct hnae3_handle *handle = priv->handle;
1067 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1068
1069 /* When software reset is detected at .init_instance() function, we
1070 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1071 * with error.
1072 */
1073 hr_dev->dis_db = true;
1074 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1075 hr_dev->is_reset = true;
1076
1077 return CMD_RST_PRC_EBUSY;
1078 }
1079
check_aedev_reset_status(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1080 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1081 struct hnae3_handle *handle)
1082 {
1083 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1084 unsigned long instance_stage; /* the current instance stage */
1085 unsigned long reset_stage; /* the current reset stage */
1086 unsigned long reset_cnt;
1087 bool sw_resetting;
1088 bool hw_resetting;
1089
1090 /* Get information about reset from NIC driver or RoCE driver itself,
1091 * the meaning of the following variables from NIC driver are described
1092 * as below:
1093 * reset_cnt -- The count value of completed hardware reset.
1094 * hw_resetting -- Whether hardware device is resetting now.
1095 * sw_resetting -- Whether NIC's software reset process is running now.
1096 */
1097 instance_stage = handle->rinfo.instance_state;
1098 reset_stage = handle->rinfo.reset_state;
1099 reset_cnt = ops->ae_dev_reset_cnt(handle);
1100 if (reset_cnt != hr_dev->reset_cnt)
1101 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1102 reset_stage);
1103
1104 hw_resetting = ops->get_cmdq_stat(handle);
1105 if (hw_resetting)
1106 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1107 reset_stage);
1108
1109 sw_resetting = ops->ae_dev_resetting(handle);
1110 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1111 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1112
1113 return CMD_RST_PRC_OTHERS;
1114 }
1115
check_device_is_in_reset(struct hns_roce_dev * hr_dev)1116 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1117 {
1118 struct hns_roce_v2_priv *priv = hr_dev->priv;
1119 struct hnae3_handle *handle = priv->handle;
1120 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1121
1122 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1123 return true;
1124
1125 if (ops->get_hw_reset_stat(handle))
1126 return true;
1127
1128 if (ops->ae_dev_resetting(handle))
1129 return true;
1130
1131 return false;
1132 }
1133
v2_chk_mbox_is_avail(struct hns_roce_dev * hr_dev,bool * busy)1134 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1135 {
1136 struct hns_roce_v2_priv *priv = hr_dev->priv;
1137 u32 status;
1138
1139 if (hr_dev->is_reset)
1140 status = CMD_RST_PRC_SUCCESS;
1141 else
1142 status = check_aedev_reset_status(hr_dev, priv->handle);
1143
1144 *busy = (status == CMD_RST_PRC_EBUSY);
1145
1146 return status == CMD_RST_PRC_OTHERS;
1147 }
1148
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1149 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1150 struct hns_roce_v2_cmq_ring *ring)
1151 {
1152 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1153
1154 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1155 &ring->desc_dma_addr, GFP_KERNEL);
1156 if (!ring->desc)
1157 return -ENOMEM;
1158
1159 return 0;
1160 }
1161
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1162 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1163 struct hns_roce_v2_cmq_ring *ring)
1164 {
1165 dma_free_coherent(hr_dev->dev,
1166 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1167 ring->desc, ring->desc_dma_addr);
1168
1169 ring->desc_dma_addr = 0;
1170 }
1171
init_csq(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * csq)1172 static int init_csq(struct hns_roce_dev *hr_dev,
1173 struct hns_roce_v2_cmq_ring *csq)
1174 {
1175 dma_addr_t dma;
1176 int ret;
1177
1178 csq->desc_num = CMD_CSQ_DESC_NUM;
1179 spin_lock_init(&csq->lock);
1180 csq->flag = TYPE_CSQ;
1181 csq->head = 0;
1182
1183 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1184 if (ret)
1185 return ret;
1186
1187 dma = csq->desc_dma_addr;
1188 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1189 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1190 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1191 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1192
1193 /* Make sure to write CI first and then PI */
1194 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1195 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1196
1197 return 0;
1198 }
1199
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1200 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1201 {
1202 struct hns_roce_v2_priv *priv = hr_dev->priv;
1203 int ret;
1204
1205 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1206
1207 ret = init_csq(hr_dev, &priv->cmq.csq);
1208 if (ret)
1209 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1210
1211 return ret;
1212 }
1213
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1214 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1215 {
1216 struct hns_roce_v2_priv *priv = hr_dev->priv;
1217
1218 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1219 }
1220
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1221 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1222 enum hns_roce_opcode_type opcode,
1223 bool is_read)
1224 {
1225 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1226 desc->opcode = cpu_to_le16(opcode);
1227 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1228 if (is_read)
1229 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1230 else
1231 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1232 }
1233
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1234 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1235 {
1236 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1237 struct hns_roce_v2_priv *priv = hr_dev->priv;
1238
1239 return tail == priv->cmq.csq.head;
1240 }
1241
update_cmdq_status(struct hns_roce_dev * hr_dev)1242 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1243 {
1244 struct hns_roce_v2_priv *priv = hr_dev->priv;
1245 struct hnae3_handle *handle = priv->handle;
1246
1247 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1248 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1249 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1250 }
1251
hns_roce_cmd_err_convert_errno(u16 desc_ret)1252 static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1253 {
1254 struct hns_roce_cmd_errcode errcode_table[] = {
1255 {CMD_EXEC_SUCCESS, 0},
1256 {CMD_NO_AUTH, -EPERM},
1257 {CMD_NOT_EXIST, -EOPNOTSUPP},
1258 {CMD_CRQ_FULL, -EXFULL},
1259 {CMD_NEXT_ERR, -ENOSR},
1260 {CMD_NOT_EXEC, -ENOTBLK},
1261 {CMD_PARA_ERR, -EINVAL},
1262 {CMD_RESULT_ERR, -ERANGE},
1263 {CMD_TIMEOUT, -ETIME},
1264 {CMD_HILINK_ERR, -ENOLINK},
1265 {CMD_INFO_ILLEGAL, -ENXIO},
1266 {CMD_INVALID, -EBADR},
1267 };
1268 u16 i;
1269
1270 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1271 if (desc_ret == errcode_table[i].return_status)
1272 return errcode_table[i].errno;
1273 return -EIO;
1274 }
1275
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1276 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1277 struct hns_roce_cmq_desc *desc, int num)
1278 {
1279 struct hns_roce_v2_priv *priv = hr_dev->priv;
1280 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1281 u32 timeout = 0;
1282 u16 desc_ret;
1283 u32 tail;
1284 int ret;
1285 int i;
1286
1287 spin_lock_bh(&csq->lock);
1288
1289 tail = csq->head;
1290
1291 for (i = 0; i < num; i++) {
1292 csq->desc[csq->head++] = desc[i];
1293 if (csq->head == csq->desc_num)
1294 csq->head = 0;
1295 }
1296
1297 /* Write to hardware */
1298 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1299
1300 do {
1301 if (hns_roce_cmq_csq_done(hr_dev))
1302 break;
1303 udelay(1);
1304 } while (++timeout < priv->cmq.tx_timeout);
1305
1306 if (hns_roce_cmq_csq_done(hr_dev)) {
1307 ret = 0;
1308 for (i = 0; i < num; i++) {
1309 /* check the result of hardware write back */
1310 desc[i] = csq->desc[tail++];
1311 if (tail == csq->desc_num)
1312 tail = 0;
1313
1314 desc_ret = le16_to_cpu(desc[i].retval);
1315 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1316 continue;
1317
1318 dev_err_ratelimited(hr_dev->dev,
1319 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1320 desc->opcode, desc_ret);
1321 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1322 }
1323 } else {
1324 /* FW/HW reset or incorrect number of desc */
1325 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1326 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1327 csq->head, tail);
1328 csq->head = tail;
1329
1330 update_cmdq_status(hr_dev);
1331
1332 ret = -EAGAIN;
1333 }
1334
1335 spin_unlock_bh(&csq->lock);
1336
1337 return ret;
1338 }
1339
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1340 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1341 struct hns_roce_cmq_desc *desc, int num)
1342 {
1343 bool busy;
1344 int ret;
1345
1346 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1347 return -EIO;
1348
1349 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1350 return busy ? -EBUSY : 0;
1351
1352 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1353 if (ret) {
1354 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1355 return busy ? -EBUSY : 0;
1356 }
1357
1358 return ret;
1359 }
1360
config_hem_ba_to_hw(struct hns_roce_dev * hr_dev,dma_addr_t base_addr,u8 cmd,unsigned long tag)1361 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1362 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1363 {
1364 struct hns_roce_cmd_mailbox *mbox;
1365 int ret;
1366
1367 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1368 if (IS_ERR(mbox))
1369 return PTR_ERR(mbox);
1370
1371 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1372 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1373 return ret;
1374 }
1375
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1376 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1377 {
1378 struct hns_roce_query_version *resp;
1379 struct hns_roce_cmq_desc desc;
1380 int ret;
1381
1382 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1383 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1384 if (ret)
1385 return ret;
1386
1387 resp = (struct hns_roce_query_version *)desc.data;
1388 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1389 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1390
1391 return 0;
1392 }
1393
func_clr_hw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1394 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1395 struct hnae3_handle *handle)
1396 {
1397 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1398 unsigned long end;
1399
1400 hr_dev->dis_db = true;
1401
1402 dev_warn(hr_dev->dev,
1403 "func clear is pending, device in resetting state.\n");
1404 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1405 while (end) {
1406 if (!ops->get_hw_reset_stat(handle)) {
1407 hr_dev->is_reset = true;
1408 dev_info(hr_dev->dev,
1409 "func clear success after reset.\n");
1410 return;
1411 }
1412 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1413 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1414 }
1415
1416 dev_warn(hr_dev->dev, "func clear failed.\n");
1417 }
1418
func_clr_sw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1419 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1420 struct hnae3_handle *handle)
1421 {
1422 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1423 unsigned long end;
1424
1425 hr_dev->dis_db = true;
1426
1427 dev_warn(hr_dev->dev,
1428 "func clear is pending, device in resetting state.\n");
1429 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1430 while (end) {
1431 if (ops->ae_dev_reset_cnt(handle) !=
1432 hr_dev->reset_cnt) {
1433 hr_dev->is_reset = true;
1434 dev_info(hr_dev->dev,
1435 "func clear success after sw reset\n");
1436 return;
1437 }
1438 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1439 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1440 }
1441
1442 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1443 }
1444
hns_roce_func_clr_rst_proc(struct hns_roce_dev * hr_dev,int retval,int flag)1445 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1446 int flag)
1447 {
1448 struct hns_roce_v2_priv *priv = hr_dev->priv;
1449 struct hnae3_handle *handle = priv->handle;
1450 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1451
1452 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1453 hr_dev->dis_db = true;
1454 hr_dev->is_reset = true;
1455 dev_info(hr_dev->dev, "func clear success after reset.\n");
1456 return;
1457 }
1458
1459 if (ops->get_hw_reset_stat(handle)) {
1460 func_clr_hw_resetting_state(hr_dev, handle);
1461 return;
1462 }
1463
1464 if (ops->ae_dev_resetting(handle) &&
1465 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1466 func_clr_sw_resetting_state(hr_dev, handle);
1467 return;
1468 }
1469
1470 if (retval && !flag)
1471 dev_warn(hr_dev->dev,
1472 "func clear read failed, ret = %d.\n", retval);
1473
1474 dev_warn(hr_dev->dev, "func clear failed.\n");
1475 }
1476
__hns_roce_function_clear(struct hns_roce_dev * hr_dev,int vf_id)1477 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1478 {
1479 bool fclr_write_fail_flag = false;
1480 struct hns_roce_func_clear *resp;
1481 struct hns_roce_cmq_desc desc;
1482 unsigned long end;
1483 int ret = 0;
1484
1485 if (check_device_is_in_reset(hr_dev))
1486 goto out;
1487
1488 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1489 resp = (struct hns_roce_func_clear *)desc.data;
1490 resp->rst_funcid_en = cpu_to_le32(vf_id);
1491
1492 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1493 if (ret) {
1494 fclr_write_fail_flag = true;
1495 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1496 ret);
1497 goto out;
1498 }
1499
1500 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1501 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1502 while (end) {
1503 if (check_device_is_in_reset(hr_dev))
1504 goto out;
1505 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1506 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1507
1508 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1509 true);
1510
1511 resp->rst_funcid_en = cpu_to_le32(vf_id);
1512 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1513 if (ret)
1514 continue;
1515
1516 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1517 if (vf_id == 0)
1518 hr_dev->is_reset = true;
1519 return;
1520 }
1521 }
1522
1523 out:
1524 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1525 }
1526
hns_roce_free_vf_resource(struct hns_roce_dev * hr_dev,int vf_id)1527 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1528 {
1529 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1530 struct hns_roce_cmq_desc desc[2];
1531 struct hns_roce_cmq_req *req_a;
1532
1533 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1534 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1535 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1536 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1537 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1538
1539 return hns_roce_cmq_send(hr_dev, desc, 2);
1540 }
1541
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1542 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1543 {
1544 int ret;
1545 int i;
1546
1547 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1548 return;
1549
1550 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1551 __hns_roce_function_clear(hr_dev, i);
1552
1553 if (i == 0)
1554 continue;
1555
1556 ret = hns_roce_free_vf_resource(hr_dev, i);
1557 if (ret)
1558 ibdev_err(&hr_dev->ib_dev,
1559 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1560 i, ret);
1561 }
1562 }
1563
hns_roce_clear_extdb_list_info(struct hns_roce_dev * hr_dev)1564 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1565 {
1566 struct hns_roce_cmq_desc desc;
1567 int ret;
1568
1569 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1570 false);
1571 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1572 if (ret)
1573 ibdev_err(&hr_dev->ib_dev,
1574 "failed to clear extended doorbell info, ret = %d.\n",
1575 ret);
1576
1577 return ret;
1578 }
1579
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1580 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1581 {
1582 struct hns_roce_query_fw_info *resp;
1583 struct hns_roce_cmq_desc desc;
1584 int ret;
1585
1586 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1587 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1588 if (ret)
1589 return ret;
1590
1591 resp = (struct hns_roce_query_fw_info *)desc.data;
1592 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1593
1594 return 0;
1595 }
1596
hns_roce_query_func_info(struct hns_roce_dev * hr_dev)1597 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1598 {
1599 struct hns_roce_cmq_desc desc;
1600 int ret;
1601
1602 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1603 hr_dev->func_num = 1;
1604 return 0;
1605 }
1606
1607 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1608 true);
1609 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1610 if (ret) {
1611 hr_dev->func_num = 1;
1612 return ret;
1613 }
1614
1615 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1616 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1617
1618 return 0;
1619 }
1620
hns_roce_hw_v2_query_counter(struct hns_roce_dev * hr_dev,u64 * stats,u32 port,int * num_counters)1621 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1622 u64 *stats, u32 port, int *num_counters)
1623 {
1624 #define CNT_PER_DESC 3
1625 struct hns_roce_cmq_desc *desc;
1626 int bd_idx, cnt_idx;
1627 __le64 *cnt_data;
1628 int desc_num;
1629 int ret;
1630 int i;
1631
1632 if (port > hr_dev->caps.num_ports)
1633 return -EINVAL;
1634
1635 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1636 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1637 if (!desc)
1638 return -ENOMEM;
1639
1640 for (i = 0; i < desc_num; i++) {
1641 hns_roce_cmq_setup_basic_desc(&desc[i],
1642 HNS_ROCE_OPC_QUERY_COUNTER, true);
1643 if (i != desc_num - 1)
1644 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1645 }
1646
1647 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1648 if (ret) {
1649 ibdev_err(&hr_dev->ib_dev,
1650 "failed to get counter, ret = %d.\n", ret);
1651 goto err_out;
1652 }
1653
1654 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1655 bd_idx = i / CNT_PER_DESC;
1656 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC &&
1657 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT)))
1658 break;
1659
1660 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1661 cnt_idx = i % CNT_PER_DESC;
1662 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1663 }
1664 *num_counters = i;
1665
1666 err_out:
1667 kfree(desc);
1668 return ret;
1669 }
1670
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1671 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1672 {
1673 struct hns_roce_cmq_desc desc;
1674 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1675 u32 clock_cycles_of_1us;
1676
1677 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1678 false);
1679
1680 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1681 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1682 else
1683 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1684
1685 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1686 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1687
1688 return hns_roce_cmq_send(hr_dev, &desc, 1);
1689 }
1690
load_func_res_caps(struct hns_roce_dev * hr_dev,bool is_vf)1691 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1692 {
1693 struct hns_roce_cmq_desc desc[2];
1694 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1695 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1696 struct hns_roce_caps *caps = &hr_dev->caps;
1697 enum hns_roce_opcode_type opcode;
1698 u32 func_num;
1699 int ret;
1700
1701 if (is_vf) {
1702 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1703 func_num = 1;
1704 } else {
1705 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1706 func_num = hr_dev->func_num;
1707 }
1708
1709 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1710 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1711 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1712
1713 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1714 if (ret)
1715 return ret;
1716
1717 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1718 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1719 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1720 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1721 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1722 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1723 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1724 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1725
1726 if (is_vf) {
1727 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1728 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1729 func_num;
1730 } else {
1731 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1732 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1733 func_num;
1734 }
1735
1736 return 0;
1737 }
1738
load_pf_timer_res_caps(struct hns_roce_dev * hr_dev)1739 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1740 {
1741 struct hns_roce_cmq_desc desc;
1742 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1743 struct hns_roce_caps *caps = &hr_dev->caps;
1744 int ret;
1745
1746 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1747 true);
1748
1749 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1750 if (ret)
1751 return ret;
1752
1753 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1754 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1755
1756 return 0;
1757 }
1758
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1759 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1760 {
1761 struct device *dev = hr_dev->dev;
1762 int ret;
1763
1764 ret = load_func_res_caps(hr_dev, false);
1765 if (ret) {
1766 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1767 return ret;
1768 }
1769
1770 ret = load_pf_timer_res_caps(hr_dev);
1771 if (ret)
1772 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1773 ret);
1774
1775 return ret;
1776 }
1777
hns_roce_query_vf_resource(struct hns_roce_dev * hr_dev)1778 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1779 {
1780 struct device *dev = hr_dev->dev;
1781 int ret;
1782
1783 ret = load_func_res_caps(hr_dev, true);
1784 if (ret)
1785 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1786
1787 return ret;
1788 }
1789
__hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,u32 vf_id)1790 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1791 u32 vf_id)
1792 {
1793 struct hns_roce_vf_switch *swt;
1794 struct hns_roce_cmq_desc desc;
1795 int ret;
1796
1797 swt = (struct hns_roce_vf_switch *)desc.data;
1798 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1799 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1800 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1801 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1802 if (ret)
1803 return ret;
1804
1805 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1806 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1807 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1808 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1809 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1810
1811 return hns_roce_cmq_send(hr_dev, &desc, 1);
1812 }
1813
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev)1814 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1815 {
1816 u32 vf_id;
1817 int ret;
1818
1819 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1820 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1821 if (ret)
1822 return ret;
1823 }
1824 return 0;
1825 }
1826
config_vf_hem_resource(struct hns_roce_dev * hr_dev,int vf_id)1827 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1828 {
1829 struct hns_roce_cmq_desc desc[2];
1830 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1831 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1832 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1833 struct hns_roce_caps *caps = &hr_dev->caps;
1834
1835 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1836 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1837 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1838
1839 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1840
1841 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1842 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1843 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1844 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1845 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1846 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1847 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1848 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1849 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1850 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1851 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1852 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1853 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1854 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1855
1856 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1857 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1858 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1859 vf_id * caps->gmv_bt_num);
1860 } else {
1861 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1862 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1863 vf_id * caps->sgid_bt_num);
1864 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1865 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1866 vf_id * caps->smac_bt_num);
1867 }
1868
1869 return hns_roce_cmq_send(hr_dev, desc, 2);
1870 }
1871
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)1872 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1873 {
1874 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1875 u32 vf_id;
1876 int ret;
1877
1878 for (vf_id = 0; vf_id < func_num; vf_id++) {
1879 ret = config_vf_hem_resource(hr_dev, vf_id);
1880 if (ret) {
1881 dev_err(hr_dev->dev,
1882 "failed to config vf-%u hem res, ret = %d.\n",
1883 vf_id, ret);
1884 return ret;
1885 }
1886 }
1887
1888 return 0;
1889 }
1890
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)1891 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1892 {
1893 struct hns_roce_cmq_desc desc;
1894 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1895 struct hns_roce_caps *caps = &hr_dev->caps;
1896
1897 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1898
1899 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1900 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1901 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1902 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1903 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1904 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1905
1906 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1907 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1908 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1909 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1910 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1911 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1912
1913 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1914 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1915 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1916 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1917 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1918 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1919
1920 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1921 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1922 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1923 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1924 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1925 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1926
1927 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1928 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1929 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1930 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1931 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1932 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1933
1934 return hns_roce_cmq_send(hr_dev, &desc, 1);
1935 }
1936
calc_pg_sz(u32 obj_num,u32 obj_size,u32 hop_num,u32 ctx_bt_num,u32 * buf_page_size,u32 * bt_page_size,u32 hem_type)1937 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
1938 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
1939 {
1940 u64 obj_per_chunk;
1941 u64 bt_chunk_size = PAGE_SIZE;
1942 u64 buf_chunk_size = PAGE_SIZE;
1943 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
1944
1945 *buf_page_size = 0;
1946 *bt_page_size = 0;
1947
1948 switch (hop_num) {
1949 case 3:
1950 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1951 (bt_chunk_size / BA_BYTE_LEN) *
1952 (bt_chunk_size / BA_BYTE_LEN) *
1953 obj_per_chunk_default;
1954 break;
1955 case 2:
1956 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1957 (bt_chunk_size / BA_BYTE_LEN) *
1958 obj_per_chunk_default;
1959 break;
1960 case 1:
1961 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1962 obj_per_chunk_default;
1963 break;
1964 case HNS_ROCE_HOP_NUM_0:
1965 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1966 break;
1967 default:
1968 pr_err("table %u not support hop_num = %u!\n", hem_type,
1969 hop_num);
1970 return;
1971 }
1972
1973 if (hem_type >= HEM_TYPE_MTT)
1974 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1975 else
1976 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1977 }
1978
set_hem_page_size(struct hns_roce_dev * hr_dev)1979 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
1980 {
1981 struct hns_roce_caps *caps = &hr_dev->caps;
1982
1983 /* EQ */
1984 caps->eqe_ba_pg_sz = 0;
1985 caps->eqe_buf_pg_sz = 0;
1986
1987 /* Link Table */
1988 caps->llm_buf_pg_sz = 0;
1989
1990 /* MR */
1991 caps->mpt_ba_pg_sz = 0;
1992 caps->mpt_buf_pg_sz = 0;
1993 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
1994 caps->pbl_buf_pg_sz = 0;
1995 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1996 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1997 HEM_TYPE_MTPT);
1998
1999 /* QP */
2000 caps->qpc_ba_pg_sz = 0;
2001 caps->qpc_buf_pg_sz = 0;
2002 caps->qpc_timer_ba_pg_sz = 0;
2003 caps->qpc_timer_buf_pg_sz = 0;
2004 caps->sccc_ba_pg_sz = 0;
2005 caps->sccc_buf_pg_sz = 0;
2006 caps->mtt_ba_pg_sz = 0;
2007 caps->mtt_buf_pg_sz = 0;
2008 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2009 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2010 HEM_TYPE_QPC);
2011
2012 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2013 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2014 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2015 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2016
2017 /* CQ */
2018 caps->cqc_ba_pg_sz = 0;
2019 caps->cqc_buf_pg_sz = 0;
2020 caps->cqc_timer_ba_pg_sz = 0;
2021 caps->cqc_timer_buf_pg_sz = 0;
2022 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2023 caps->cqe_buf_pg_sz = 0;
2024 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2025 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2026 HEM_TYPE_CQC);
2027 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2028 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2029
2030 /* SRQ */
2031 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2032 caps->srqc_ba_pg_sz = 0;
2033 caps->srqc_buf_pg_sz = 0;
2034 caps->srqwqe_ba_pg_sz = 0;
2035 caps->srqwqe_buf_pg_sz = 0;
2036 caps->idx_ba_pg_sz = 0;
2037 caps->idx_buf_pg_sz = 0;
2038 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2039 caps->srqc_hop_num, caps->srqc_bt_num,
2040 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2041 HEM_TYPE_SRQC);
2042 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2043 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2044 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2045 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2046 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2047 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2048 }
2049
2050 /* GMV */
2051 caps->gmv_ba_pg_sz = 0;
2052 caps->gmv_buf_pg_sz = 0;
2053 }
2054
2055 /* Apply all loaded caps before setting to hardware */
apply_func_caps(struct hns_roce_dev * hr_dev)2056 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2057 {
2058 struct hns_roce_caps *caps = &hr_dev->caps;
2059 struct hns_roce_v2_priv *priv = hr_dev->priv;
2060
2061 /* The following configurations don't need to be got from firmware. */
2062 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2063 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2064 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2065
2066 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2067 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2068 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2069
2070 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2071 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2072
2073 if (!caps->num_comp_vectors)
2074 caps->num_comp_vectors =
2075 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2076 (u32)priv->handle->rinfo.num_vectors -
2077 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2078
2079 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2080 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2081 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2082 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2083
2084 /* The following configurations will be overwritten */
2085 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2086 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2087 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2088
2089 /* The following configurations are not got from firmware */
2090 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2091
2092 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2093 caps->gid_table_len[0] = caps->gmv_bt_num *
2094 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2095
2096 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE /
2097 caps->gmv_entry_sz);
2098 } else {
2099 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2100
2101 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2102 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2103 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2104 caps->gid_table_len[0] /= func_num;
2105 }
2106
2107 if (hr_dev->is_vf) {
2108 caps->default_aeq_arm_st = 0x3;
2109 caps->default_ceq_arm_st = 0x3;
2110 caps->default_ceq_max_cnt = 0x1;
2111 caps->default_ceq_period = 0x10;
2112 caps->default_aeq_max_cnt = 0x1;
2113 caps->default_aeq_period = 0x10;
2114 }
2115
2116 set_hem_page_size(hr_dev);
2117 }
2118
hns_roce_query_caps(struct hns_roce_dev * hr_dev)2119 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2120 {
2121 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2122 struct hns_roce_caps *caps = &hr_dev->caps;
2123 struct hns_roce_query_pf_caps_a *resp_a;
2124 struct hns_roce_query_pf_caps_b *resp_b;
2125 struct hns_roce_query_pf_caps_c *resp_c;
2126 struct hns_roce_query_pf_caps_d *resp_d;
2127 struct hns_roce_query_pf_caps_e *resp_e;
2128 enum hns_roce_opcode_type cmd;
2129 int ctx_hop_num;
2130 int pbl_hop_num;
2131 int ret;
2132 int i;
2133
2134 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2135 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2136
2137 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2138 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2139 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2140 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2141 else
2142 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2143 }
2144
2145 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2146 if (ret)
2147 return ret;
2148
2149 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2150 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2151 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2152 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2153 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2154
2155 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2156 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2157 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2158 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2159 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2160 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2161 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2162 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2163 caps->num_other_vectors = resp_a->num_other_vectors;
2164 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2165 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2166
2167 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2168 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2169 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2170 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2171 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2172 caps->idx_entry_sz = resp_b->idx_entry_sz;
2173 caps->sccc_sz = resp_b->sccc_sz;
2174 caps->max_mtu = resp_b->max_mtu;
2175 caps->min_cqes = resp_b->min_cqes;
2176 caps->min_wqes = resp_b->min_wqes;
2177 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2178 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2179 caps->phy_num_uars = resp_b->phy_num_uars;
2180 ctx_hop_num = resp_b->ctx_hop_num;
2181 pbl_hop_num = resp_b->pbl_hop_num;
2182
2183 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2184
2185 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2186 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2187 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2188
2189 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2190 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2191 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2192 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2193 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2194 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2195 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2196 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2197 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2198
2199 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2200 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2201 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2202 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2203 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2204 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2205 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2206 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2207 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2208 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2209
2210 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2211 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2212 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2213 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2214 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2215 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2216
2217 caps->qpc_hop_num = ctx_hop_num;
2218 caps->sccc_hop_num = ctx_hop_num;
2219 caps->srqc_hop_num = ctx_hop_num;
2220 caps->cqc_hop_num = ctx_hop_num;
2221 caps->mpt_hop_num = ctx_hop_num;
2222 caps->mtt_hop_num = pbl_hop_num;
2223 caps->cqe_hop_num = pbl_hop_num;
2224 caps->srqwqe_hop_num = pbl_hop_num;
2225 caps->idx_hop_num = pbl_hop_num;
2226 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2227 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2228 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2229
2230 if (!(caps->page_size_cap & PAGE_SIZE))
2231 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2232
2233 if (!hr_dev->is_vf) {
2234 caps->cqe_sz = resp_a->cqe_sz;
2235 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2236 caps->default_aeq_arm_st =
2237 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2238 caps->default_ceq_arm_st =
2239 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2240 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2241 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2242 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2243 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2244 }
2245
2246 return 0;
2247 }
2248
config_hem_entry_size(struct hns_roce_dev * hr_dev,u32 type,u32 val)2249 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2250 {
2251 struct hns_roce_cmq_desc desc;
2252 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2253
2254 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2255 false);
2256
2257 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2258 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2259
2260 return hns_roce_cmq_send(hr_dev, &desc, 1);
2261 }
2262
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2263 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2264 {
2265 struct hns_roce_caps *caps = &hr_dev->caps;
2266 int ret;
2267
2268 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2269 return 0;
2270
2271 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2272 caps->qpc_sz);
2273 if (ret) {
2274 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2275 return ret;
2276 }
2277
2278 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2279 caps->sccc_sz);
2280 if (ret)
2281 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2282
2283 return ret;
2284 }
2285
hns_roce_v2_vf_profile(struct hns_roce_dev * hr_dev)2286 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2287 {
2288 struct device *dev = hr_dev->dev;
2289 int ret;
2290
2291 hr_dev->func_num = 1;
2292
2293 ret = hns_roce_query_caps(hr_dev);
2294 if (ret) {
2295 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2296 return ret;
2297 }
2298
2299 ret = hns_roce_query_vf_resource(hr_dev);
2300 if (ret) {
2301 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2302 return ret;
2303 }
2304
2305 apply_func_caps(hr_dev);
2306
2307 ret = hns_roce_v2_set_bt(hr_dev);
2308 if (ret)
2309 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2310
2311 return ret;
2312 }
2313
hns_roce_v2_pf_profile(struct hns_roce_dev * hr_dev)2314 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2315 {
2316 struct device *dev = hr_dev->dev;
2317 int ret;
2318
2319 ret = hns_roce_query_func_info(hr_dev);
2320 if (ret) {
2321 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2322 return ret;
2323 }
2324
2325 ret = hns_roce_config_global_param(hr_dev);
2326 if (ret) {
2327 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2328 return ret;
2329 }
2330
2331 ret = hns_roce_set_vf_switch_param(hr_dev);
2332 if (ret) {
2333 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2334 return ret;
2335 }
2336
2337 ret = hns_roce_query_caps(hr_dev);
2338 if (ret) {
2339 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2340 return ret;
2341 }
2342
2343 ret = hns_roce_query_pf_resource(hr_dev);
2344 if (ret) {
2345 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2346 return ret;
2347 }
2348
2349 apply_func_caps(hr_dev);
2350
2351 ret = hns_roce_alloc_vf_resource(hr_dev);
2352 if (ret) {
2353 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2354 return ret;
2355 }
2356
2357 ret = hns_roce_v2_set_bt(hr_dev);
2358 if (ret) {
2359 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2360 return ret;
2361 }
2362
2363 /* Configure the size of QPC, SCCC, etc. */
2364 return hns_roce_config_entry_size(hr_dev);
2365 }
2366
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2367 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2368 {
2369 struct device *dev = hr_dev->dev;
2370 int ret;
2371
2372 ret = hns_roce_cmq_query_hw_info(hr_dev);
2373 if (ret) {
2374 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2375 return ret;
2376 }
2377
2378 ret = hns_roce_query_fw_ver(hr_dev);
2379 if (ret) {
2380 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2381 return ret;
2382 }
2383
2384 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2385 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2386
2387 if (hr_dev->is_vf)
2388 return hns_roce_v2_vf_profile(hr_dev);
2389 else
2390 return hns_roce_v2_pf_profile(hr_dev);
2391 }
2392
config_llm_table(struct hns_roce_buf * data_buf,void * cfg_buf)2393 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2394 {
2395 u32 i, next_ptr, page_num;
2396 __le64 *entry = cfg_buf;
2397 dma_addr_t addr;
2398 u64 val;
2399
2400 page_num = data_buf->npages;
2401 for (i = 0; i < page_num; i++) {
2402 addr = hns_roce_buf_page(data_buf, i);
2403 if (i == (page_num - 1))
2404 next_ptr = 0;
2405 else
2406 next_ptr = i + 1;
2407
2408 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2409 entry[i] = cpu_to_le64(val);
2410 }
2411 }
2412
set_llm_cfg_to_hw(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * table)2413 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2414 struct hns_roce_link_table *table)
2415 {
2416 struct hns_roce_cmq_desc desc[2];
2417 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2418 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2419 struct hns_roce_buf *buf = table->buf;
2420 enum hns_roce_opcode_type opcode;
2421 dma_addr_t addr;
2422
2423 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2424 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2425 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2426 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2427
2428 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2429 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2430 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2431 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2432 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2433
2434 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2435 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2436 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2437 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2438 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2439
2440 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2441 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2442 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2443 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2444
2445 return hns_roce_cmq_send(hr_dev, desc, 2);
2446 }
2447
2448 static struct hns_roce_link_table *
alloc_link_table_buf(struct hns_roce_dev * hr_dev)2449 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2450 {
2451 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2452 struct hns_roce_v2_priv *priv = hr_dev->priv;
2453 struct hns_roce_link_table *link_tbl;
2454 u32 pg_shift, size, min_size;
2455
2456 link_tbl = &priv->ext_llm;
2457 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2458 size = hr_dev->caps.num_qps * hr_dev->func_num *
2459 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2460 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2461
2462 /* Alloc data table */
2463 size = max(size, min_size);
2464 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2465 if (IS_ERR(link_tbl->buf))
2466 return ERR_PTR(-ENOMEM);
2467
2468 /* Alloc config table */
2469 size = link_tbl->buf->npages * sizeof(u64);
2470 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2471 &link_tbl->table.map,
2472 GFP_KERNEL);
2473 if (!link_tbl->table.buf) {
2474 hns_roce_buf_free(hr_dev, link_tbl->buf);
2475 return ERR_PTR(-ENOMEM);
2476 }
2477
2478 return link_tbl;
2479 }
2480
free_link_table_buf(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * tbl)2481 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2482 struct hns_roce_link_table *tbl)
2483 {
2484 if (tbl->buf) {
2485 u32 size = tbl->buf->npages * sizeof(u64);
2486
2487 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2488 tbl->table.map);
2489 }
2490
2491 hns_roce_buf_free(hr_dev, tbl->buf);
2492 }
2493
hns_roce_init_link_table(struct hns_roce_dev * hr_dev)2494 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2495 {
2496 struct hns_roce_link_table *link_tbl;
2497 int ret;
2498
2499 link_tbl = alloc_link_table_buf(hr_dev);
2500 if (IS_ERR(link_tbl))
2501 return -ENOMEM;
2502
2503 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2504 ret = -EINVAL;
2505 goto err_alloc;
2506 }
2507
2508 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2509 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2510 if (ret)
2511 goto err_alloc;
2512
2513 return 0;
2514
2515 err_alloc:
2516 free_link_table_buf(hr_dev, link_tbl);
2517 return ret;
2518 }
2519
hns_roce_free_link_table(struct hns_roce_dev * hr_dev)2520 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2521 {
2522 struct hns_roce_v2_priv *priv = hr_dev->priv;
2523
2524 free_link_table_buf(hr_dev, &priv->ext_llm);
2525 }
2526
free_dip_list(struct hns_roce_dev * hr_dev)2527 static void free_dip_list(struct hns_roce_dev *hr_dev)
2528 {
2529 struct hns_roce_dip *hr_dip;
2530 struct hns_roce_dip *tmp;
2531 unsigned long flags;
2532
2533 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2534
2535 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2536 list_del(&hr_dip->node);
2537 kfree(hr_dip);
2538 }
2539
2540 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2541 }
2542
free_mr_init_pd(struct hns_roce_dev * hr_dev)2543 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2544 {
2545 struct hns_roce_v2_priv *priv = hr_dev->priv;
2546 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2547 struct ib_device *ibdev = &hr_dev->ib_dev;
2548 struct hns_roce_pd *hr_pd;
2549 struct ib_pd *pd;
2550
2551 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2552 if (ZERO_OR_NULL_PTR(hr_pd))
2553 return NULL;
2554 pd = &hr_pd->ibpd;
2555 pd->device = ibdev;
2556
2557 if (hns_roce_alloc_pd(pd, NULL)) {
2558 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2559 kfree(hr_pd);
2560 return NULL;
2561 }
2562 free_mr->rsv_pd = to_hr_pd(pd);
2563 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2564 free_mr->rsv_pd->ibpd.uobject = NULL;
2565 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2566 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2567
2568 return pd;
2569 }
2570
free_mr_init_cq(struct hns_roce_dev * hr_dev)2571 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2572 {
2573 struct hns_roce_v2_priv *priv = hr_dev->priv;
2574 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2575 struct ib_device *ibdev = &hr_dev->ib_dev;
2576 struct ib_cq_init_attr cq_init_attr = {};
2577 struct hns_roce_cq *hr_cq;
2578 struct ib_cq *cq;
2579
2580 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2581
2582 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2583 if (ZERO_OR_NULL_PTR(hr_cq))
2584 return NULL;
2585
2586 cq = &hr_cq->ib_cq;
2587 cq->device = ibdev;
2588
2589 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2590 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2591 kfree(hr_cq);
2592 return NULL;
2593 }
2594 free_mr->rsv_cq = to_hr_cq(cq);
2595 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2596 free_mr->rsv_cq->ib_cq.uobject = NULL;
2597 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2598 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2599 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2600 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2601
2602 return cq;
2603 }
2604
free_mr_init_qp(struct hns_roce_dev * hr_dev,struct ib_cq * cq,struct ib_qp_init_attr * init_attr,int i)2605 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2606 struct ib_qp_init_attr *init_attr, int i)
2607 {
2608 struct hns_roce_v2_priv *priv = hr_dev->priv;
2609 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2610 struct ib_device *ibdev = &hr_dev->ib_dev;
2611 struct hns_roce_qp *hr_qp;
2612 struct ib_qp *qp;
2613 int ret;
2614
2615 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2616 if (ZERO_OR_NULL_PTR(hr_qp))
2617 return -ENOMEM;
2618
2619 qp = &hr_qp->ibqp;
2620 qp->device = ibdev;
2621
2622 ret = hns_roce_create_qp(qp, init_attr, NULL);
2623 if (ret) {
2624 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2625 kfree(hr_qp);
2626 return ret;
2627 }
2628
2629 free_mr->rsv_qp[i] = hr_qp;
2630 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2631 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2632
2633 return 0;
2634 }
2635
free_mr_exit(struct hns_roce_dev * hr_dev)2636 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2637 {
2638 struct hns_roce_v2_priv *priv = hr_dev->priv;
2639 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2640 struct ib_qp *qp;
2641 int i;
2642
2643 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2644 if (free_mr->rsv_qp[i]) {
2645 qp = &free_mr->rsv_qp[i]->ibqp;
2646 hns_roce_v2_destroy_qp(qp, NULL);
2647 kfree(free_mr->rsv_qp[i]);
2648 free_mr->rsv_qp[i] = NULL;
2649 }
2650 }
2651
2652 if (free_mr->rsv_cq) {
2653 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2654 kfree(free_mr->rsv_cq);
2655 free_mr->rsv_cq = NULL;
2656 }
2657
2658 if (free_mr->rsv_pd) {
2659 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2660 kfree(free_mr->rsv_pd);
2661 free_mr->rsv_pd = NULL;
2662 }
2663 }
2664
free_mr_alloc_res(struct hns_roce_dev * hr_dev)2665 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2666 {
2667 struct hns_roce_v2_priv *priv = hr_dev->priv;
2668 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2669 struct ib_qp_init_attr qp_init_attr = {};
2670 struct ib_pd *pd;
2671 struct ib_cq *cq;
2672 int ret;
2673 int i;
2674
2675 pd = free_mr_init_pd(hr_dev);
2676 if (!pd)
2677 return -ENOMEM;
2678
2679 cq = free_mr_init_cq(hr_dev);
2680 if (!cq) {
2681 ret = -ENOMEM;
2682 goto create_failed_cq;
2683 }
2684
2685 qp_init_attr.qp_type = IB_QPT_RC;
2686 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2687 qp_init_attr.send_cq = cq;
2688 qp_init_attr.recv_cq = cq;
2689 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2690 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2691 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2692 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2693 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2694
2695 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2696 if (ret)
2697 goto create_failed_qp;
2698 }
2699
2700 return 0;
2701
2702 create_failed_qp:
2703 for (i--; i >= 0; i--) {
2704 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2705 kfree(free_mr->rsv_qp[i]);
2706 }
2707 hns_roce_destroy_cq(cq, NULL);
2708 kfree(cq);
2709
2710 create_failed_cq:
2711 hns_roce_dealloc_pd(pd, NULL);
2712 kfree(pd);
2713
2714 return ret;
2715 }
2716
free_mr_modify_rsv_qp(struct hns_roce_dev * hr_dev,struct ib_qp_attr * attr,int sl_num)2717 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2718 struct ib_qp_attr *attr, int sl_num)
2719 {
2720 struct hns_roce_v2_priv *priv = hr_dev->priv;
2721 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2722 struct ib_device *ibdev = &hr_dev->ib_dev;
2723 struct hns_roce_qp *hr_qp;
2724 int loopback;
2725 int mask;
2726 int ret;
2727
2728 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2729 hr_qp->free_mr_en = 1;
2730 hr_qp->ibqp.device = ibdev;
2731 hr_qp->ibqp.qp_type = IB_QPT_RC;
2732
2733 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2734 attr->qp_state = IB_QPS_INIT;
2735 attr->port_num = 1;
2736 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2737 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2738 IB_QPS_INIT, NULL);
2739 if (ret) {
2740 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
2741 ret);
2742 return ret;
2743 }
2744
2745 loopback = hr_dev->loop_idc;
2746 /* Set qpc lbi = 1 incidate loopback IO */
2747 hr_dev->loop_idc = 1;
2748
2749 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2750 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2751 attr->qp_state = IB_QPS_RTR;
2752 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2753 attr->path_mtu = IB_MTU_256;
2754 attr->dest_qp_num = hr_qp->qpn;
2755 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2756
2757 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2758
2759 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2760 IB_QPS_RTR, NULL);
2761 hr_dev->loop_idc = loopback;
2762 if (ret) {
2763 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2764 ret);
2765 return ret;
2766 }
2767
2768 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2769 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2770 attr->qp_state = IB_QPS_RTS;
2771 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2772 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2773 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2774 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2775 IB_QPS_RTS, NULL);
2776 if (ret)
2777 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2778 ret);
2779
2780 return ret;
2781 }
2782
free_mr_modify_qp(struct hns_roce_dev * hr_dev)2783 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2784 {
2785 struct hns_roce_v2_priv *priv = hr_dev->priv;
2786 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2787 struct ib_qp_attr attr = {};
2788 int ret;
2789 int i;
2790
2791 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2792 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2793 rdma_ah_set_port_num(&attr.ah_attr, 1);
2794
2795 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2796 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2797 if (ret)
2798 return ret;
2799 }
2800
2801 return 0;
2802 }
2803
free_mr_init(struct hns_roce_dev * hr_dev)2804 static int free_mr_init(struct hns_roce_dev *hr_dev)
2805 {
2806 struct hns_roce_v2_priv *priv = hr_dev->priv;
2807 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2808 int ret;
2809
2810 mutex_init(&free_mr->mutex);
2811
2812 ret = free_mr_alloc_res(hr_dev);
2813 if (ret)
2814 return ret;
2815
2816 ret = free_mr_modify_qp(hr_dev);
2817 if (ret)
2818 goto err_modify_qp;
2819
2820 return 0;
2821
2822 err_modify_qp:
2823 free_mr_exit(hr_dev);
2824
2825 return ret;
2826 }
2827
get_hem_table(struct hns_roce_dev * hr_dev)2828 static int get_hem_table(struct hns_roce_dev *hr_dev)
2829 {
2830 unsigned int qpc_count;
2831 unsigned int cqc_count;
2832 unsigned int gmv_count;
2833 int ret;
2834 int i;
2835
2836 /* Alloc memory for source address table buffer space chunk */
2837 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2838 gmv_count++) {
2839 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2840 if (ret)
2841 goto err_gmv_failed;
2842 }
2843
2844 if (hr_dev->is_vf)
2845 return 0;
2846
2847 /* Alloc memory for QPC Timer buffer space chunk */
2848 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2849 qpc_count++) {
2850 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2851 qpc_count);
2852 if (ret) {
2853 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2854 goto err_qpc_timer_failed;
2855 }
2856 }
2857
2858 /* Alloc memory for CQC Timer buffer space chunk */
2859 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2860 cqc_count++) {
2861 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2862 cqc_count);
2863 if (ret) {
2864 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2865 goto err_cqc_timer_failed;
2866 }
2867 }
2868
2869 return 0;
2870
2871 err_cqc_timer_failed:
2872 for (i = 0; i < cqc_count; i++)
2873 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2874
2875 err_qpc_timer_failed:
2876 for (i = 0; i < qpc_count; i++)
2877 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2878
2879 err_gmv_failed:
2880 for (i = 0; i < gmv_count; i++)
2881 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2882
2883 return ret;
2884 }
2885
put_hem_table(struct hns_roce_dev * hr_dev)2886 static void put_hem_table(struct hns_roce_dev *hr_dev)
2887 {
2888 int i;
2889
2890 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2891 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2892
2893 if (hr_dev->is_vf)
2894 return;
2895
2896 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2897 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2898
2899 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2900 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2901 }
2902
hns_roce_v2_init(struct hns_roce_dev * hr_dev)2903 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2904 {
2905 int ret;
2906
2907 /* The hns ROCEE requires the extdb info to be cleared before using */
2908 ret = hns_roce_clear_extdb_list_info(hr_dev);
2909 if (ret)
2910 return ret;
2911
2912 ret = get_hem_table(hr_dev);
2913 if (ret)
2914 return ret;
2915
2916 if (hr_dev->is_vf)
2917 return 0;
2918
2919 ret = hns_roce_init_link_table(hr_dev);
2920 if (ret) {
2921 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2922 goto err_llm_init_failed;
2923 }
2924
2925 return 0;
2926
2927 err_llm_init_failed:
2928 put_hem_table(hr_dev);
2929
2930 return ret;
2931 }
2932
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)2933 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2934 {
2935 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2936 free_mr_exit(hr_dev);
2937
2938 hns_roce_function_clear(hr_dev);
2939
2940 if (!hr_dev->is_vf)
2941 hns_roce_free_link_table(hr_dev);
2942
2943 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2944 free_dip_list(hr_dev);
2945 }
2946
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)2947 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2948 struct hns_roce_mbox_msg *mbox_msg)
2949 {
2950 struct hns_roce_cmq_desc desc;
2951 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2952
2953 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2954
2955 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2956 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2957 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2958 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2959 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2960 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2961 mbox_msg->token);
2962
2963 return hns_roce_cmq_send(hr_dev, &desc, 1);
2964 }
2965
v2_wait_mbox_complete(struct hns_roce_dev * hr_dev,u32 timeout,u8 * complete_status)2966 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2967 u8 *complete_status)
2968 {
2969 struct hns_roce_mbox_status *mb_st;
2970 struct hns_roce_cmq_desc desc;
2971 unsigned long end;
2972 int ret = -EBUSY;
2973 u32 status;
2974 bool busy;
2975
2976 mb_st = (struct hns_roce_mbox_status *)desc.data;
2977 end = msecs_to_jiffies(timeout) + jiffies;
2978 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2979 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2980 return -EIO;
2981
2982 status = 0;
2983 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2984 true);
2985 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2986 if (!ret) {
2987 status = le32_to_cpu(mb_st->mb_status_hw_run);
2988 /* No pending message exists in ROCEE mbox. */
2989 if (!(status & MB_ST_HW_RUN_M))
2990 break;
2991 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2992 break;
2993 }
2994
2995 if (time_after(jiffies, end)) {
2996 dev_err_ratelimited(hr_dev->dev,
2997 "failed to wait mbox status 0x%x\n",
2998 status);
2999 return -ETIMEDOUT;
3000 }
3001
3002 cond_resched();
3003 ret = -EBUSY;
3004 }
3005
3006 if (!ret) {
3007 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3008 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3009 /* Ignore all errors if the mbox is unavailable. */
3010 ret = 0;
3011 *complete_status = MB_ST_COMPLETE_M;
3012 }
3013
3014 return ret;
3015 }
3016
v2_post_mbox(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3017 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3018 struct hns_roce_mbox_msg *mbox_msg)
3019 {
3020 u8 status = 0;
3021 int ret;
3022
3023 /* Waiting for the mbox to be idle */
3024 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3025 &status);
3026 if (unlikely(ret)) {
3027 dev_err_ratelimited(hr_dev->dev,
3028 "failed to check post mbox status = 0x%x, ret = %d.\n",
3029 status, ret);
3030 return ret;
3031 }
3032
3033 /* Post new message to mbox */
3034 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3035 if (ret)
3036 dev_err_ratelimited(hr_dev->dev,
3037 "failed to post mailbox, ret = %d.\n", ret);
3038
3039 return ret;
3040 }
3041
v2_poll_mbox_done(struct hns_roce_dev * hr_dev)3042 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3043 {
3044 u8 status = 0;
3045 int ret;
3046
3047 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3048 &status);
3049 if (!ret) {
3050 if (status != MB_ST_COMPLETE_SUCC)
3051 return -EBUSY;
3052 } else {
3053 dev_err_ratelimited(hr_dev->dev,
3054 "failed to check mbox status = 0x%x, ret = %d.\n",
3055 status, ret);
3056 }
3057
3058 return ret;
3059 }
3060
copy_gid(void * dest,const union ib_gid * gid)3061 static void copy_gid(void *dest, const union ib_gid *gid)
3062 {
3063 #define GID_SIZE 4
3064 const union ib_gid *src = gid;
3065 __le32 (*p)[GID_SIZE] = dest;
3066 int i;
3067
3068 if (!gid)
3069 src = &zgid;
3070
3071 for (i = 0; i < GID_SIZE; i++)
3072 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3073 }
3074
config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)3075 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3076 int gid_index, const union ib_gid *gid,
3077 enum hns_roce_sgid_type sgid_type)
3078 {
3079 struct hns_roce_cmq_desc desc;
3080 struct hns_roce_cfg_sgid_tb *sgid_tb =
3081 (struct hns_roce_cfg_sgid_tb *)desc.data;
3082
3083 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3084
3085 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3086 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3087
3088 copy_gid(&sgid_tb->vf_sgid_l, gid);
3089
3090 return hns_roce_cmq_send(hr_dev, &desc, 1);
3091 }
3092
config_gmv_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type,const struct ib_gid_attr * attr)3093 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3094 int gid_index, const union ib_gid *gid,
3095 enum hns_roce_sgid_type sgid_type,
3096 const struct ib_gid_attr *attr)
3097 {
3098 struct hns_roce_cmq_desc desc[2];
3099 struct hns_roce_cfg_gmv_tb_a *tb_a =
3100 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3101 struct hns_roce_cfg_gmv_tb_b *tb_b =
3102 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3103
3104 u16 vlan_id = VLAN_CFI_MASK;
3105 u8 mac[ETH_ALEN] = {};
3106 int ret;
3107
3108 if (gid) {
3109 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3110 if (ret)
3111 return ret;
3112 }
3113
3114 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3115 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3116
3117 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3118
3119 copy_gid(&tb_a->vf_sgid_l, gid);
3120
3121 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3122 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3123 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3124
3125 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3126
3127 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3128 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3129
3130 return hns_roce_cmq_send(hr_dev, desc, 2);
3131 }
3132
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)3133 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3134 const union ib_gid *gid,
3135 const struct ib_gid_attr *attr)
3136 {
3137 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3138 int ret;
3139
3140 if (gid) {
3141 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3142 if (ipv6_addr_v4mapped((void *)gid))
3143 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3144 else
3145 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3146 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3147 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3148 }
3149 }
3150
3151 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3152 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3153 else
3154 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3155
3156 if (ret)
3157 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3158 ret);
3159
3160 return ret;
3161 }
3162
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,const u8 * addr)3163 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3164 const u8 *addr)
3165 {
3166 struct hns_roce_cmq_desc desc;
3167 struct hns_roce_cfg_smac_tb *smac_tb =
3168 (struct hns_roce_cfg_smac_tb *)desc.data;
3169 u16 reg_smac_h;
3170 u32 reg_smac_l;
3171
3172 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3173
3174 reg_smac_l = *(u32 *)(&addr[0]);
3175 reg_smac_h = *(u16 *)(&addr[4]);
3176
3177 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3178 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3179 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3180
3181 return hns_roce_cmq_send(hr_dev, &desc, 1);
3182 }
3183
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)3184 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3185 struct hns_roce_v2_mpt_entry *mpt_entry,
3186 struct hns_roce_mr *mr)
3187 {
3188 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3189 struct ib_device *ibdev = &hr_dev->ib_dev;
3190 dma_addr_t pbl_ba;
3191 int i, count;
3192
3193 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3194 min_t(int, ARRAY_SIZE(pages), mr->npages),
3195 &pbl_ba);
3196 if (count < 1) {
3197 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3198 count);
3199 return -ENOBUFS;
3200 }
3201
3202 /* Aligned to the hardware address access unit */
3203 for (i = 0; i < count; i++)
3204 pages[i] >>= 6;
3205
3206 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3207 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3208 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3209
3210 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3211 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3212
3213 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3214 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3215 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3216 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3217
3218 return 0;
3219 }
3220
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3221 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3222 void *mb_buf, struct hns_roce_mr *mr)
3223 {
3224 struct hns_roce_v2_mpt_entry *mpt_entry;
3225
3226 mpt_entry = mb_buf;
3227 memset(mpt_entry, 0, sizeof(*mpt_entry));
3228
3229 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3230 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3231
3232 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3233 mr->access & IB_ACCESS_MW_BIND);
3234 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3235 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3236 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3237 mr->access & IB_ACCESS_REMOTE_READ);
3238 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3239 mr->access & IB_ACCESS_REMOTE_WRITE);
3240 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3241 mr->access & IB_ACCESS_LOCAL_WRITE);
3242
3243 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3244 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3245 mpt_entry->lkey = cpu_to_le32(mr->key);
3246 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3247 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3248
3249 if (mr->type != MR_TYPE_MR)
3250 hr_reg_enable(mpt_entry, MPT_PA);
3251
3252 if (mr->type == MR_TYPE_DMA)
3253 return 0;
3254
3255 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3256 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3257
3258 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3259 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3260 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3261
3262 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3263 }
3264
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,void * mb_buf)3265 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3266 struct hns_roce_mr *mr, int flags,
3267 void *mb_buf)
3268 {
3269 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3270 u32 mr_access_flags = mr->access;
3271 int ret = 0;
3272
3273 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3274 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3275
3276 if (flags & IB_MR_REREG_ACCESS) {
3277 hr_reg_write(mpt_entry, MPT_BIND_EN,
3278 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3279 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3280 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3281 hr_reg_write(mpt_entry, MPT_RR_EN,
3282 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3283 hr_reg_write(mpt_entry, MPT_RW_EN,
3284 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3285 hr_reg_write(mpt_entry, MPT_LW_EN,
3286 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3287 }
3288
3289 if (flags & IB_MR_REREG_TRANS) {
3290 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3291 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3292 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3293 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3294
3295 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3296 }
3297
3298 return ret;
3299 }
3300
hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3301 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3302 void *mb_buf, struct hns_roce_mr *mr)
3303 {
3304 struct ib_device *ibdev = &hr_dev->ib_dev;
3305 struct hns_roce_v2_mpt_entry *mpt_entry;
3306 dma_addr_t pbl_ba = 0;
3307
3308 mpt_entry = mb_buf;
3309 memset(mpt_entry, 0, sizeof(*mpt_entry));
3310
3311 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3312 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3313 return -ENOBUFS;
3314 }
3315
3316 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3317 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3318
3319 hr_reg_enable(mpt_entry, MPT_RA_EN);
3320 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3321
3322 hr_reg_enable(mpt_entry, MPT_FRE);
3323 hr_reg_clear(mpt_entry, MPT_MR_MW);
3324 hr_reg_enable(mpt_entry, MPT_BPD);
3325 hr_reg_clear(mpt_entry, MPT_PA);
3326
3327 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3328 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3329 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3330 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3331 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3332
3333 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3334
3335 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3336 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3337
3338 return 0;
3339 }
3340
hns_roce_v2_mw_write_mtpt(void * mb_buf,struct hns_roce_mw * mw)3341 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3342 {
3343 struct hns_roce_v2_mpt_entry *mpt_entry;
3344
3345 mpt_entry = mb_buf;
3346 memset(mpt_entry, 0, sizeof(*mpt_entry));
3347
3348 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3349 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3350
3351 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3352 hr_reg_enable(mpt_entry, MPT_LW_EN);
3353
3354 hr_reg_enable(mpt_entry, MPT_MR_MW);
3355 hr_reg_enable(mpt_entry, MPT_BPD);
3356 hr_reg_clear(mpt_entry, MPT_PA);
3357 hr_reg_write(mpt_entry, MPT_BQP,
3358 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3359
3360 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3361
3362 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3363 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3364 mw->pbl_hop_num);
3365 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3366 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3367 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3368 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3369
3370 return 0;
3371 }
3372
free_mr_post_send_lp_wqe(struct hns_roce_qp * hr_qp)3373 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3374 {
3375 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3376 struct ib_device *ibdev = &hr_dev->ib_dev;
3377 const struct ib_send_wr *bad_wr;
3378 struct ib_rdma_wr rdma_wr = {};
3379 struct ib_send_wr *send_wr;
3380 int ret;
3381
3382 send_wr = &rdma_wr.wr;
3383 send_wr->opcode = IB_WR_RDMA_WRITE;
3384
3385 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3386 if (ret) {
3387 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3388 ret);
3389 return ret;
3390 }
3391
3392 return 0;
3393 }
3394
3395 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3396 struct ib_wc *wc);
3397
free_mr_send_cmd_to_hw(struct hns_roce_dev * hr_dev)3398 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3399 {
3400 struct hns_roce_v2_priv *priv = hr_dev->priv;
3401 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3402 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3403 struct ib_device *ibdev = &hr_dev->ib_dev;
3404 struct hns_roce_qp *hr_qp;
3405 unsigned long end;
3406 int cqe_cnt = 0;
3407 int npolled;
3408 int ret;
3409 int i;
3410
3411 /*
3412 * If the device initialization is not complete or in the uninstall
3413 * process, then there is no need to execute free mr.
3414 */
3415 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3416 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3417 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3418 return;
3419
3420 mutex_lock(&free_mr->mutex);
3421
3422 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3423 hr_qp = free_mr->rsv_qp[i];
3424
3425 ret = free_mr_post_send_lp_wqe(hr_qp);
3426 if (ret) {
3427 ibdev_err(ibdev,
3428 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3429 hr_qp->qpn, ret);
3430 break;
3431 }
3432
3433 cqe_cnt++;
3434 }
3435
3436 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3437 while (cqe_cnt) {
3438 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3439 if (npolled < 0) {
3440 ibdev_err(ibdev,
3441 "failed to poll cqe for free mr, remain %d cqe.\n",
3442 cqe_cnt);
3443 goto out;
3444 }
3445
3446 if (time_after(jiffies, end)) {
3447 ibdev_err(ibdev,
3448 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3449 cqe_cnt);
3450 goto out;
3451 }
3452 cqe_cnt -= npolled;
3453 }
3454
3455 out:
3456 mutex_unlock(&free_mr->mutex);
3457 }
3458
hns_roce_v2_dereg_mr(struct hns_roce_dev * hr_dev)3459 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3460 {
3461 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3462 free_mr_send_cmd_to_hw(hr_dev);
3463 }
3464
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)3465 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3466 {
3467 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3468 }
3469
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,unsigned int n)3470 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3471 {
3472 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3473
3474 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3475 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3476 NULL;
3477 }
3478
update_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)3479 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3480 struct hns_roce_cq *hr_cq)
3481 {
3482 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3483 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3484 } else {
3485 struct hns_roce_v2_db cq_db = {};
3486
3487 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3488 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3489 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3490 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3491
3492 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3493 }
3494 }
3495
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3496 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3497 struct hns_roce_srq *srq)
3498 {
3499 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3500 struct hns_roce_v2_cqe *cqe, *dest;
3501 u32 prod_index;
3502 int nfreed = 0;
3503 int wqe_index;
3504 u8 owner_bit;
3505
3506 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3507 ++prod_index) {
3508 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3509 break;
3510 }
3511
3512 /*
3513 * Now backwards through the CQ, removing CQ entries
3514 * that match our QP by overwriting them with next entries.
3515 */
3516 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3517 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3518 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3519 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3520 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3521 hns_roce_free_srq_wqe(srq, wqe_index);
3522 }
3523 ++nfreed;
3524 } else if (nfreed) {
3525 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3526 hr_cq->ib_cq.cqe);
3527 owner_bit = hr_reg_read(dest, CQE_OWNER);
3528 memcpy(dest, cqe, hr_cq->cqe_size);
3529 hr_reg_write(dest, CQE_OWNER, owner_bit);
3530 }
3531 }
3532
3533 if (nfreed) {
3534 hr_cq->cons_index += nfreed;
3535 update_cq_db(hr_dev, hr_cq);
3536 }
3537 }
3538
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3539 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3540 struct hns_roce_srq *srq)
3541 {
3542 spin_lock_irq(&hr_cq->lock);
3543 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3544 spin_unlock_irq(&hr_cq->lock);
3545 }
3546
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3547 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3548 struct hns_roce_cq *hr_cq, void *mb_buf,
3549 u64 *mtts, dma_addr_t dma_handle)
3550 {
3551 struct hns_roce_v2_cq_context *cq_context;
3552
3553 cq_context = mb_buf;
3554 memset(cq_context, 0, sizeof(*cq_context));
3555
3556 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3557 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3558 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3559 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3560 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3561
3562 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3563 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3564
3565 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3566 hr_reg_enable(cq_context, CQC_STASH);
3567
3568 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3569 to_hr_hw_page_addr(mtts[0]));
3570 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3571 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3572 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3573 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3574 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3575 to_hr_hw_page_addr(mtts[1]));
3576 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3577 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3578 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3579 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3580 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3581 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3582 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3583 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3584 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3585 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3586 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3587 ((u32)hr_cq->db.dma) >> 1);
3588 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3589 hr_cq->db.dma >> 32);
3590 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3591 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3592 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3593 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3594 }
3595
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3596 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3597 enum ib_cq_notify_flags flags)
3598 {
3599 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3600 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3601 struct hns_roce_v2_db cq_db = {};
3602 u32 notify_flag;
3603
3604 /*
3605 * flags = 0, then notify_flag : next
3606 * flags = 1, then notify flag : solocited
3607 */
3608 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3609 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3610
3611 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3612 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3613 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3614 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3615 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3616
3617 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3618
3619 return 0;
3620 }
3621
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3622 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3623 int num_entries, struct ib_wc *wc)
3624 {
3625 unsigned int left;
3626 int npolled = 0;
3627
3628 left = wq->head - wq->tail;
3629 if (left == 0)
3630 return 0;
3631
3632 left = min_t(unsigned int, (unsigned int)num_entries, left);
3633 while (npolled < left) {
3634 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3635 wc->status = IB_WC_WR_FLUSH_ERR;
3636 wc->vendor_err = 0;
3637 wc->qp = &hr_qp->ibqp;
3638
3639 wq->tail++;
3640 wc++;
3641 npolled++;
3642 }
3643
3644 return npolled;
3645 }
3646
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3647 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3648 struct ib_wc *wc)
3649 {
3650 struct hns_roce_qp *hr_qp;
3651 int npolled = 0;
3652
3653 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3654 npolled += sw_comp(hr_qp, &hr_qp->sq,
3655 num_entries - npolled, wc + npolled);
3656 if (npolled >= num_entries)
3657 goto out;
3658 }
3659
3660 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3661 npolled += sw_comp(hr_qp, &hr_qp->rq,
3662 num_entries - npolled, wc + npolled);
3663 if (npolled >= num_entries)
3664 goto out;
3665 }
3666
3667 out:
3668 return npolled;
3669 }
3670
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3671 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3672 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3673 struct ib_wc *wc)
3674 {
3675 static const struct {
3676 u32 cqe_status;
3677 enum ib_wc_status wc_status;
3678 } map[] = {
3679 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3680 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3681 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3682 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3683 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3684 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3685 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3686 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3687 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3688 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3689 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3690 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3691 IB_WC_RETRY_EXC_ERR },
3692 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3693 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3694 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3695 };
3696
3697 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3698 int i;
3699
3700 wc->status = IB_WC_GENERAL_ERR;
3701 for (i = 0; i < ARRAY_SIZE(map); i++)
3702 if (cqe_status == map[i].cqe_status) {
3703 wc->status = map[i].wc_status;
3704 break;
3705 }
3706
3707 if (likely(wc->status == IB_WC_SUCCESS ||
3708 wc->status == IB_WC_WR_FLUSH_ERR))
3709 return;
3710
3711 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n",
3712 cqe_status);
3713 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3714 cq->cqe_size, false);
3715 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3716
3717 /*
3718 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3719 * the standard protocol, the driver must ignore it and needn't to set
3720 * the QP to an error state.
3721 */
3722 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3723 return;
3724
3725 flush_cqe(hr_dev, qp);
3726 }
3727
get_cur_qp(struct hns_roce_cq * hr_cq,struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp)3728 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3729 struct hns_roce_qp **cur_qp)
3730 {
3731 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3732 struct hns_roce_qp *hr_qp = *cur_qp;
3733 u32 qpn;
3734
3735 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3736
3737 if (!hr_qp || qpn != hr_qp->qpn) {
3738 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3739 if (unlikely(!hr_qp)) {
3740 ibdev_err(&hr_dev->ib_dev,
3741 "CQ %06lx with entry for unknown QPN %06x\n",
3742 hr_cq->cqn, qpn);
3743 return -EINVAL;
3744 }
3745 *cur_qp = hr_qp;
3746 }
3747
3748 return 0;
3749 }
3750
3751 /*
3752 * mapped-value = 1 + real-value
3753 * The ib wc opcode's real value is start from 0, In order to distinguish
3754 * between initialized and uninitialized map values, we plus 1 to the actual
3755 * value when defining the mapping, so that the validity can be identified by
3756 * checking whether the mapped value is greater than 0.
3757 */
3758 #define HR_WC_OP_MAP(hr_key, ib_key) \
3759 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3760
3761 static const u32 wc_send_op_map[] = {
3762 HR_WC_OP_MAP(SEND, SEND),
3763 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3764 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3765 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3766 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3767 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3768 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3769 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3770 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3771 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3772 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3773 HR_WC_OP_MAP(BIND_MW, REG_MR),
3774 };
3775
to_ib_wc_send_op(u32 hr_opcode)3776 static int to_ib_wc_send_op(u32 hr_opcode)
3777 {
3778 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3779 return -EINVAL;
3780
3781 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3782 -EINVAL;
3783 }
3784
3785 static const u32 wc_recv_op_map[] = {
3786 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3787 HR_WC_OP_MAP(SEND, RECV),
3788 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3789 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3790 };
3791
to_ib_wc_recv_op(u32 hr_opcode)3792 static int to_ib_wc_recv_op(u32 hr_opcode)
3793 {
3794 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3795 return -EINVAL;
3796
3797 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3798 -EINVAL;
3799 }
3800
fill_send_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3801 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3802 {
3803 u32 hr_opcode;
3804 int ib_opcode;
3805
3806 wc->wc_flags = 0;
3807
3808 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3809 switch (hr_opcode) {
3810 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3811 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3812 break;
3813 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3814 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3815 wc->wc_flags |= IB_WC_WITH_IMM;
3816 break;
3817 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3818 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3819 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3820 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3821 wc->byte_len = 8;
3822 break;
3823 default:
3824 break;
3825 }
3826
3827 ib_opcode = to_ib_wc_send_op(hr_opcode);
3828 if (ib_opcode < 0)
3829 wc->status = IB_WC_GENERAL_ERR;
3830 else
3831 wc->opcode = ib_opcode;
3832 }
3833
fill_recv_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3834 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3835 {
3836 u32 hr_opcode;
3837 int ib_opcode;
3838
3839 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3840
3841 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3842 switch (hr_opcode) {
3843 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3844 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3845 wc->wc_flags = IB_WC_WITH_IMM;
3846 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3847 break;
3848 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3849 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3850 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3851 break;
3852 default:
3853 wc->wc_flags = 0;
3854 }
3855
3856 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3857 if (ib_opcode < 0)
3858 wc->status = IB_WC_GENERAL_ERR;
3859 else
3860 wc->opcode = ib_opcode;
3861
3862 wc->sl = hr_reg_read(cqe, CQE_SL);
3863 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3864 wc->slid = 0;
3865 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3866 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3867 wc->pkey_index = 0;
3868
3869 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3870 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3871 wc->wc_flags |= IB_WC_WITH_VLAN;
3872 } else {
3873 wc->vlan_id = 0xffff;
3874 }
3875
3876 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3877
3878 return 0;
3879 }
3880
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3881 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3882 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3883 {
3884 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3885 struct hns_roce_qp *qp = *cur_qp;
3886 struct hns_roce_srq *srq = NULL;
3887 struct hns_roce_v2_cqe *cqe;
3888 struct hns_roce_wq *wq;
3889 int is_send;
3890 u16 wqe_idx;
3891 int ret;
3892
3893 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3894 if (!cqe)
3895 return -EAGAIN;
3896
3897 ++hr_cq->cons_index;
3898 /* Memory barrier */
3899 rmb();
3900
3901 ret = get_cur_qp(hr_cq, cqe, &qp);
3902 if (ret)
3903 return ret;
3904
3905 wc->qp = &qp->ibqp;
3906 wc->vendor_err = 0;
3907
3908 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3909
3910 is_send = !hr_reg_read(cqe, CQE_S_R);
3911 if (is_send) {
3912 wq = &qp->sq;
3913
3914 /* If sg_signal_bit is set, tail pointer will be updated to
3915 * the WQE corresponding to the current CQE.
3916 */
3917 if (qp->sq_signal_bits)
3918 wq->tail += (wqe_idx - (u16)wq->tail) &
3919 (wq->wqe_cnt - 1);
3920
3921 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3922 ++wq->tail;
3923
3924 fill_send_wc(wc, cqe);
3925 } else {
3926 if (qp->ibqp.srq) {
3927 srq = to_hr_srq(qp->ibqp.srq);
3928 wc->wr_id = srq->wrid[wqe_idx];
3929 hns_roce_free_srq_wqe(srq, wqe_idx);
3930 } else {
3931 wq = &qp->rq;
3932 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3933 ++wq->tail;
3934 }
3935
3936 ret = fill_recv_wc(wc, cqe);
3937 }
3938
3939 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3940 if (unlikely(wc->status != IB_WC_SUCCESS))
3941 return 0;
3942
3943 return ret;
3944 }
3945
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)3946 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3947 struct ib_wc *wc)
3948 {
3949 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3950 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3951 struct hns_roce_qp *cur_qp = NULL;
3952 unsigned long flags;
3953 int npolled;
3954
3955 spin_lock_irqsave(&hr_cq->lock, flags);
3956
3957 /*
3958 * When the device starts to reset, the state is RST_DOWN. At this time,
3959 * there may still be some valid CQEs in the hardware that are not
3960 * polled. Therefore, it is not allowed to switch to the software mode
3961 * immediately. When the state changes to UNINIT, CQE no longer exists
3962 * in the hardware, and then switch to software mode.
3963 */
3964 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3965 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3966 goto out;
3967 }
3968
3969 for (npolled = 0; npolled < num_entries; ++npolled) {
3970 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3971 break;
3972 }
3973
3974 if (npolled)
3975 update_cq_db(hr_dev, hr_cq);
3976
3977 out:
3978 spin_unlock_irqrestore(&hr_cq->lock, flags);
3979
3980 return npolled;
3981 }
3982
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,u32 step_idx,u8 * mbox_cmd)3983 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3984 u32 step_idx, u8 *mbox_cmd)
3985 {
3986 u8 cmd;
3987
3988 switch (type) {
3989 case HEM_TYPE_QPC:
3990 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
3991 break;
3992 case HEM_TYPE_MTPT:
3993 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
3994 break;
3995 case HEM_TYPE_CQC:
3996 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
3997 break;
3998 case HEM_TYPE_SRQC:
3999 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4000 break;
4001 case HEM_TYPE_SCCC:
4002 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4003 break;
4004 case HEM_TYPE_QPC_TIMER:
4005 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4006 break;
4007 case HEM_TYPE_CQC_TIMER:
4008 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4009 break;
4010 default:
4011 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4012 return -EINVAL;
4013 }
4014
4015 *mbox_cmd = cmd + step_idx;
4016
4017 return 0;
4018 }
4019
config_gmv_ba_to_hw(struct hns_roce_dev * hr_dev,unsigned long obj,dma_addr_t base_addr)4020 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4021 dma_addr_t base_addr)
4022 {
4023 struct hns_roce_cmq_desc desc;
4024 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4025 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4026 u64 addr = to_hr_hw_page_addr(base_addr);
4027
4028 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4029
4030 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4031 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4032 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4033
4034 return hns_roce_cmq_send(hr_dev, &desc, 1);
4035 }
4036
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,dma_addr_t base_addr,u32 hem_type,u32 step_idx)4037 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4038 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4039 {
4040 int ret;
4041 u8 cmd;
4042
4043 if (unlikely(hem_type == HEM_TYPE_GMV))
4044 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4045
4046 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4047 return 0;
4048
4049 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4050 if (ret < 0)
4051 return ret;
4052
4053 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4054 }
4055
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,u32 step_idx)4056 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4057 struct hns_roce_hem_table *table, int obj,
4058 u32 step_idx)
4059 {
4060 struct hns_roce_hem_iter iter;
4061 struct hns_roce_hem_mhop mhop;
4062 struct hns_roce_hem *hem;
4063 unsigned long mhop_obj = obj;
4064 int i, j, k;
4065 int ret = 0;
4066 u64 hem_idx = 0;
4067 u64 l1_idx = 0;
4068 u64 bt_ba = 0;
4069 u32 chunk_ba_num;
4070 u32 hop_num;
4071
4072 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4073 return 0;
4074
4075 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4076 i = mhop.l0_idx;
4077 j = mhop.l1_idx;
4078 k = mhop.l2_idx;
4079 hop_num = mhop.hop_num;
4080 chunk_ba_num = mhop.bt_chunk_size / 8;
4081
4082 if (hop_num == 2) {
4083 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4084 k;
4085 l1_idx = i * chunk_ba_num + j;
4086 } else if (hop_num == 1) {
4087 hem_idx = i * chunk_ba_num + j;
4088 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4089 hem_idx = i;
4090 }
4091
4092 if (table->type == HEM_TYPE_SCCC)
4093 obj = mhop.l0_idx;
4094
4095 if (check_whether_last_step(hop_num, step_idx)) {
4096 hem = table->hem[hem_idx];
4097 for (hns_roce_hem_first(hem, &iter);
4098 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4099 bt_ba = hns_roce_hem_addr(&iter);
4100 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4101 step_idx);
4102 }
4103 } else {
4104 if (step_idx == 0)
4105 bt_ba = table->bt_l0_dma_addr[i];
4106 else if (step_idx == 1 && hop_num == 2)
4107 bt_ba = table->bt_l1_dma_addr[l1_idx];
4108
4109 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4110 }
4111
4112 return ret;
4113 }
4114
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int tag,u32 step_idx)4115 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4116 struct hns_roce_hem_table *table,
4117 int tag, u32 step_idx)
4118 {
4119 struct hns_roce_cmd_mailbox *mailbox;
4120 struct device *dev = hr_dev->dev;
4121 u8 cmd = 0xff;
4122 int ret;
4123
4124 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4125 return 0;
4126
4127 switch (table->type) {
4128 case HEM_TYPE_QPC:
4129 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4130 break;
4131 case HEM_TYPE_MTPT:
4132 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4133 break;
4134 case HEM_TYPE_CQC:
4135 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4136 break;
4137 case HEM_TYPE_SRQC:
4138 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4139 break;
4140 case HEM_TYPE_SCCC:
4141 case HEM_TYPE_QPC_TIMER:
4142 case HEM_TYPE_CQC_TIMER:
4143 case HEM_TYPE_GMV:
4144 return 0;
4145 default:
4146 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4147 table->type);
4148 return 0;
4149 }
4150
4151 cmd += step_idx;
4152
4153 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4154 if (IS_ERR(mailbox))
4155 return PTR_ERR(mailbox);
4156
4157 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4158
4159 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4160 return ret;
4161 }
4162
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)4163 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4164 struct hns_roce_v2_qp_context *context,
4165 struct hns_roce_v2_qp_context *qpc_mask,
4166 struct hns_roce_qp *hr_qp)
4167 {
4168 struct hns_roce_cmd_mailbox *mailbox;
4169 int qpc_size;
4170 int ret;
4171
4172 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4173 if (IS_ERR(mailbox))
4174 return PTR_ERR(mailbox);
4175
4176 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4177 qpc_size = hr_dev->caps.qpc_sz;
4178 memcpy(mailbox->buf, context, qpc_size);
4179 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4180
4181 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4182 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4183
4184 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4185
4186 return ret;
4187 }
4188
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)4189 static void set_access_flags(struct hns_roce_qp *hr_qp,
4190 struct hns_roce_v2_qp_context *context,
4191 struct hns_roce_v2_qp_context *qpc_mask,
4192 const struct ib_qp_attr *attr, int attr_mask)
4193 {
4194 u8 dest_rd_atomic;
4195 u32 access_flags;
4196
4197 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4198 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4199
4200 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4201 attr->qp_access_flags : hr_qp->atomic_rd_en;
4202
4203 if (!dest_rd_atomic)
4204 access_flags &= IB_ACCESS_REMOTE_WRITE;
4205
4206 hr_reg_write_bool(context, QPC_RRE,
4207 access_flags & IB_ACCESS_REMOTE_READ);
4208 hr_reg_clear(qpc_mask, QPC_RRE);
4209
4210 hr_reg_write_bool(context, QPC_RWE,
4211 access_flags & IB_ACCESS_REMOTE_WRITE);
4212 hr_reg_clear(qpc_mask, QPC_RWE);
4213
4214 hr_reg_write_bool(context, QPC_ATE,
4215 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4216 hr_reg_clear(qpc_mask, QPC_ATE);
4217 hr_reg_write_bool(context, QPC_EXT_ATE,
4218 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4219 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4220 }
4221
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4222 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4223 struct hns_roce_v2_qp_context *context,
4224 struct hns_roce_v2_qp_context *qpc_mask)
4225 {
4226 hr_reg_write(context, QPC_SGE_SHIFT,
4227 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4228 hr_qp->sge.sge_shift));
4229
4230 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4231
4232 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4233 }
4234
get_cqn(struct ib_cq * ib_cq)4235 static inline int get_cqn(struct ib_cq *ib_cq)
4236 {
4237 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4238 }
4239
get_pdn(struct ib_pd * ib_pd)4240 static inline int get_pdn(struct ib_pd *ib_pd)
4241 {
4242 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4243 }
4244
modify_qp_reset_to_init(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4245 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4246 const struct ib_qp_attr *attr,
4247 struct hns_roce_v2_qp_context *context,
4248 struct hns_roce_v2_qp_context *qpc_mask)
4249 {
4250 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4251 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4252
4253 /*
4254 * In v2 engine, software pass context and context mask to hardware
4255 * when modifying qp. If software need modify some fields in context,
4256 * we should set all bits of the relevant fields in context mask to
4257 * 0 at the same time, else set them to 0x1.
4258 */
4259 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4260
4261 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4262
4263 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4264
4265 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4266
4267 /* No VLAN need to set 0xFFF */
4268 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4269
4270 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4271 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4272
4273 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4274 }
4275
4276 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4277 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4278
4279 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4280 hr_reg_enable(context, QPC_OWNER_MODE);
4281
4282 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4283 lower_32_bits(hr_qp->rdb.dma) >> 1);
4284 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4285 upper_32_bits(hr_qp->rdb.dma));
4286
4287 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4288
4289 if (ibqp->srq) {
4290 hr_reg_enable(context, QPC_SRQ_EN);
4291 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4292 }
4293
4294 hr_reg_enable(context, QPC_FRE);
4295
4296 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4297
4298 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4299 return;
4300
4301 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4302 hr_reg_enable(&context->ext, QPCEX_STASH);
4303 }
4304
modify_qp_init_to_init(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4305 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4306 const struct ib_qp_attr *attr,
4307 struct hns_roce_v2_qp_context *context,
4308 struct hns_roce_v2_qp_context *qpc_mask)
4309 {
4310 /*
4311 * In v2 engine, software pass context and context mask to hardware
4312 * when modifying qp. If software need modify some fields in context,
4313 * we should set all bits of the relevant fields in context mask to
4314 * 0 at the same time, else set them to 0x1.
4315 */
4316 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4317 hr_reg_clear(qpc_mask, QPC_TST);
4318
4319 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4320 hr_reg_clear(qpc_mask, QPC_PD);
4321
4322 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4323 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4324
4325 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4326 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4327
4328 if (ibqp->srq) {
4329 hr_reg_enable(context, QPC_SRQ_EN);
4330 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4331 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4332 hr_reg_clear(qpc_mask, QPC_SRQN);
4333 }
4334 }
4335
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4336 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4337 struct hns_roce_qp *hr_qp,
4338 struct hns_roce_v2_qp_context *context,
4339 struct hns_roce_v2_qp_context *qpc_mask)
4340 {
4341 u64 mtts[MTT_MIN_COUNT] = { 0 };
4342 u64 wqe_sge_ba;
4343 int count;
4344
4345 /* Search qp buf's mtts */
4346 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4347 MTT_MIN_COUNT, &wqe_sge_ba);
4348 if (hr_qp->rq.wqe_cnt && count < 1) {
4349 ibdev_err(&hr_dev->ib_dev,
4350 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4351 return -EINVAL;
4352 }
4353
4354 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4355 qpc_mask->wqe_sge_ba = 0;
4356
4357 /*
4358 * In v2 engine, software pass context and context mask to hardware
4359 * when modifying qp. If software need modify some fields in context,
4360 * we should set all bits of the relevant fields in context mask to
4361 * 0 at the same time, else set them to 0x1.
4362 */
4363 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4364 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4365
4366 hr_reg_write(context, QPC_SQ_HOP_NUM,
4367 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4368 hr_qp->sq.wqe_cnt));
4369 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4370
4371 hr_reg_write(context, QPC_SGE_HOP_NUM,
4372 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4373 hr_qp->sge.sge_cnt));
4374 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4375
4376 hr_reg_write(context, QPC_RQ_HOP_NUM,
4377 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4378 hr_qp->rq.wqe_cnt));
4379
4380 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4381
4382 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4383 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4384 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4385
4386 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4387 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4388 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4389
4390 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4391 qpc_mask->rq_cur_blk_addr = 0;
4392
4393 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4394 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4395 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4396
4397 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4398 context->rq_nxt_blk_addr =
4399 cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4400 qpc_mask->rq_nxt_blk_addr = 0;
4401 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4402 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4403 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4404 }
4405
4406 return 0;
4407 }
4408
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4409 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4410 struct hns_roce_qp *hr_qp,
4411 struct hns_roce_v2_qp_context *context,
4412 struct hns_roce_v2_qp_context *qpc_mask)
4413 {
4414 struct ib_device *ibdev = &hr_dev->ib_dev;
4415 u64 sge_cur_blk = 0;
4416 u64 sq_cur_blk = 0;
4417 int count;
4418
4419 /* search qp buf's mtts */
4420 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4421 if (count < 1) {
4422 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4423 hr_qp->qpn);
4424 return -EINVAL;
4425 }
4426 if (hr_qp->sge.sge_cnt > 0) {
4427 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4428 hr_qp->sge.offset,
4429 &sge_cur_blk, 1, NULL);
4430 if (count < 1) {
4431 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4432 hr_qp->qpn);
4433 return -EINVAL;
4434 }
4435 }
4436
4437 /*
4438 * In v2 engine, software pass context and context mask to hardware
4439 * when modifying qp. If software need modify some fields in context,
4440 * we should set all bits of the relevant fields in context mask to
4441 * 0 at the same time, else set them to 0x1.
4442 */
4443 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4444 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4445 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4446 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4447 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4448 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4449
4450 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4451 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4452 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4453 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4454 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4455 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4456
4457 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4458 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4459 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4460 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4461 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4462 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4463
4464 return 0;
4465 }
4466
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4467 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4468 const struct ib_qp_attr *attr)
4469 {
4470 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4471 return IB_MTU_4096;
4472
4473 return attr->path_mtu;
4474 }
4475
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4476 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4477 const struct ib_qp_attr *attr, int attr_mask,
4478 struct hns_roce_v2_qp_context *context,
4479 struct hns_roce_v2_qp_context *qpc_mask,
4480 struct ib_udata *udata)
4481 {
4482 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4483 struct hns_roce_ucontext, ibucontext);
4484 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4485 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4486 struct ib_device *ibdev = &hr_dev->ib_dev;
4487 dma_addr_t trrl_ba;
4488 dma_addr_t irrl_ba;
4489 enum ib_mtu ib_mtu;
4490 const u8 *smac;
4491 u8 lp_pktn_ini;
4492 u64 *mtts;
4493 u8 *dmac;
4494 u32 port;
4495 int mtu;
4496 int ret;
4497
4498 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4499 if (ret) {
4500 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4501 return ret;
4502 }
4503
4504 /* Search IRRL's mtts */
4505 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4506 hr_qp->qpn, &irrl_ba);
4507 if (!mtts) {
4508 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4509 return -EINVAL;
4510 }
4511
4512 /* Search TRRL's mtts */
4513 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4514 hr_qp->qpn, &trrl_ba);
4515 if (!mtts) {
4516 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4517 return -EINVAL;
4518 }
4519
4520 if (attr_mask & IB_QP_ALT_PATH) {
4521 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4522 attr_mask);
4523 return -EINVAL;
4524 }
4525
4526 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4527 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4528 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4529 qpc_mask->trrl_ba = 0;
4530 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4531 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4532
4533 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4534 qpc_mask->irrl_ba = 0;
4535 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4536 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4537
4538 hr_reg_enable(context, QPC_RMT_E2E);
4539 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4540
4541 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4542 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4543
4544 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4545
4546 smac = (const u8 *)hr_dev->dev_addr[port];
4547 dmac = (u8 *)attr->ah_attr.roce.dmac;
4548 /* when dmac equals smac or loop_idc is 1, it should loopback */
4549 if (ether_addr_equal_unaligned(dmac, smac) ||
4550 hr_dev->loop_idc == 0x1) {
4551 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4552 hr_reg_clear(qpc_mask, QPC_LBI);
4553 }
4554
4555 if (attr_mask & IB_QP_DEST_QPN) {
4556 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4557 hr_reg_clear(qpc_mask, QPC_DQPN);
4558 }
4559
4560 memcpy(&context->dmac, dmac, sizeof(u32));
4561 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4562 qpc_mask->dmac = 0;
4563 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4564
4565 ib_mtu = get_mtu(ibqp, attr);
4566 hr_qp->path_mtu = ib_mtu;
4567
4568 mtu = ib_mtu_enum_to_int(ib_mtu);
4569 if (WARN_ON(mtu <= 0))
4570 return -EINVAL;
4571 #define MIN_LP_MSG_LEN 1024
4572 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4573 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu);
4574
4575 if (attr_mask & IB_QP_PATH_MTU) {
4576 hr_reg_write(context, QPC_MTU, ib_mtu);
4577 hr_reg_clear(qpc_mask, QPC_MTU);
4578 }
4579
4580 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4581 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4582
4583 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4584 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4585 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4586
4587 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4588 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4589 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4590
4591 context->rq_rnr_timer = 0;
4592 qpc_mask->rq_rnr_timer = 0;
4593
4594 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4595 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4596
4597 /* rocee send 2^lp_sgen_ini segs every time */
4598 hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4599 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4600
4601 if (udata && ibqp->qp_type == IB_QPT_RC &&
4602 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4603 hr_reg_write_bool(context, QPC_RQIE,
4604 hr_dev->caps.flags &
4605 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4606 hr_reg_clear(qpc_mask, QPC_RQIE);
4607 }
4608
4609 if (udata &&
4610 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4611 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4612 hr_reg_write_bool(context, QPC_CQEIE,
4613 hr_dev->caps.flags &
4614 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4615 hr_reg_clear(qpc_mask, QPC_CQEIE);
4616
4617 hr_reg_write(context, QPC_CQEIS, 0);
4618 hr_reg_clear(qpc_mask, QPC_CQEIS);
4619 }
4620
4621 return 0;
4622 }
4623
modify_qp_rtr_to_rts(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4624 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4625 const struct ib_qp_attr *attr, int attr_mask,
4626 struct hns_roce_v2_qp_context *context,
4627 struct hns_roce_v2_qp_context *qpc_mask)
4628 {
4629 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4630 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4631 struct ib_device *ibdev = &hr_dev->ib_dev;
4632 int ret;
4633
4634 /* Not support alternate path and path migration */
4635 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4636 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4637 return -EINVAL;
4638 }
4639
4640 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4641 if (ret) {
4642 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4643 return ret;
4644 }
4645
4646 /*
4647 * Set some fields in context to zero, Because the default values
4648 * of all fields in context are zero, we need not set them to 0 again.
4649 * but we should set the relevant fields of context mask to 0.
4650 */
4651 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4652
4653 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4654
4655 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4656 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4657 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4658
4659 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4660
4661 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4662
4663 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4664
4665 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4666
4667 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4668
4669 return 0;
4670 }
4671
get_dip_ctx_idx(struct ib_qp * ibqp,const struct ib_qp_attr * attr,u32 * dip_idx)4672 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4673 u32 *dip_idx)
4674 {
4675 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4676 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4677 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4678 u32 *head = &hr_dev->qp_table.idx_table.head;
4679 u32 *tail = &hr_dev->qp_table.idx_table.tail;
4680 struct hns_roce_dip *hr_dip;
4681 unsigned long flags;
4682 int ret = 0;
4683
4684 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4685
4686 spare_idx[*tail] = ibqp->qp_num;
4687 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4688
4689 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4690 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4691 *dip_idx = hr_dip->dip_idx;
4692 goto out;
4693 }
4694 }
4695
4696 /* If no dgid is found, a new dip and a mapping between dgid and
4697 * dip_idx will be created.
4698 */
4699 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4700 if (!hr_dip) {
4701 ret = -ENOMEM;
4702 goto out;
4703 }
4704
4705 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4706 hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4707 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4708 list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4709
4710 out:
4711 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4712 return ret;
4713 }
4714
4715 enum {
4716 CONG_DCQCN,
4717 CONG_WINDOW,
4718 };
4719
4720 enum {
4721 UNSUPPORT_CONG_LEVEL,
4722 SUPPORT_CONG_LEVEL,
4723 };
4724
4725 enum {
4726 CONG_LDCP,
4727 CONG_HC3,
4728 };
4729
4730 enum {
4731 DIP_INVALID,
4732 DIP_VALID,
4733 };
4734
4735 enum {
4736 WND_LIMIT,
4737 WND_UNLIMIT,
4738 };
4739
check_cong_type(struct ib_qp * ibqp,struct hns_roce_congestion_algorithm * cong_alg)4740 static int check_cong_type(struct ib_qp *ibqp,
4741 struct hns_roce_congestion_algorithm *cong_alg)
4742 {
4743 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4744 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4745
4746 if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI)
4747 hr_qp->cong_type = CONG_TYPE_DCQCN;
4748 else
4749 hr_qp->cong_type = hr_dev->caps.cong_type;
4750
4751 /* different congestion types match different configurations */
4752 switch (hr_qp->cong_type) {
4753 case CONG_TYPE_DCQCN:
4754 cong_alg->alg_sel = CONG_DCQCN;
4755 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4756 cong_alg->dip_vld = DIP_INVALID;
4757 cong_alg->wnd_mode_sel = WND_LIMIT;
4758 break;
4759 case CONG_TYPE_LDCP:
4760 cong_alg->alg_sel = CONG_WINDOW;
4761 cong_alg->alg_sub_sel = CONG_LDCP;
4762 cong_alg->dip_vld = DIP_INVALID;
4763 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4764 break;
4765 case CONG_TYPE_HC3:
4766 cong_alg->alg_sel = CONG_WINDOW;
4767 cong_alg->alg_sub_sel = CONG_HC3;
4768 cong_alg->dip_vld = DIP_INVALID;
4769 cong_alg->wnd_mode_sel = WND_LIMIT;
4770 break;
4771 case CONG_TYPE_DIP:
4772 cong_alg->alg_sel = CONG_DCQCN;
4773 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4774 cong_alg->dip_vld = DIP_VALID;
4775 cong_alg->wnd_mode_sel = WND_LIMIT;
4776 break;
4777 default:
4778 ibdev_warn(&hr_dev->ib_dev,
4779 "invalid type(%u) for congestion selection.\n",
4780 hr_qp->cong_type);
4781 hr_qp->cong_type = CONG_TYPE_DCQCN;
4782 cong_alg->alg_sel = CONG_DCQCN;
4783 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4784 cong_alg->dip_vld = DIP_INVALID;
4785 cong_alg->wnd_mode_sel = WND_LIMIT;
4786 break;
4787 }
4788
4789 return 0;
4790 }
4791
fill_cong_field(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4792 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4793 struct hns_roce_v2_qp_context *context,
4794 struct hns_roce_v2_qp_context *qpc_mask)
4795 {
4796 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4797 struct hns_roce_congestion_algorithm cong_field;
4798 struct ib_device *ibdev = ibqp->device;
4799 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4800 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4801 u32 dip_idx = 0;
4802 int ret;
4803
4804 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4805 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4806 return 0;
4807
4808 ret = check_cong_type(ibqp, &cong_field);
4809 if (ret)
4810 return ret;
4811
4812 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4813 hr_qp->cong_type * HNS_ROCE_CONG_SIZE);
4814 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4815 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4816 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4817 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4818 cong_field.alg_sub_sel);
4819 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4820 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4821 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4822 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4823 cong_field.wnd_mode_sel);
4824 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4825
4826 /* if dip is disabled, there is no need to set dip idx */
4827 if (cong_field.dip_vld == 0)
4828 return 0;
4829
4830 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4831 if (ret) {
4832 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4833 return ret;
4834 }
4835
4836 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4837 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4838
4839 return 0;
4840 }
4841
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4842 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4843 const struct ib_qp_attr *attr,
4844 int attr_mask,
4845 struct hns_roce_v2_qp_context *context,
4846 struct hns_roce_v2_qp_context *qpc_mask)
4847 {
4848 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4849 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4850 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4851 struct ib_device *ibdev = &hr_dev->ib_dev;
4852 const struct ib_gid_attr *gid_attr = NULL;
4853 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
4854 int is_roce_protocol;
4855 u16 vlan_id = 0xffff;
4856 bool is_udp = false;
4857 u32 max_sl;
4858 u8 ib_port;
4859 u8 hr_port;
4860 int ret;
4861
4862 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
4863 if (unlikely(sl > max_sl)) {
4864 ibdev_err_ratelimited(ibdev,
4865 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n",
4866 sl, max_sl);
4867 return -EINVAL;
4868 }
4869
4870 /*
4871 * If free_mr_en of qp is set, it means that this qp comes from
4872 * free mr. This qp will perform the loopback operation.
4873 * In the loopback scenario, only sl needs to be set.
4874 */
4875 if (hr_qp->free_mr_en) {
4876 hr_reg_write(context, QPC_SL, sl);
4877 hr_reg_clear(qpc_mask, QPC_SL);
4878 hr_qp->sl = sl;
4879 return 0;
4880 }
4881
4882 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4883 hr_port = ib_port - 1;
4884 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4885 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4886
4887 if (is_roce_protocol) {
4888 gid_attr = attr->ah_attr.grh.sgid_attr;
4889 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4890 if (ret)
4891 return ret;
4892
4893 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4894 }
4895
4896 /* Only HIP08 needs to set the vlan_en bits in QPC */
4897 if (vlan_id < VLAN_N_VID &&
4898 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4899 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4900 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4901 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4902 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4903 }
4904
4905 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4906 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4907
4908 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4909 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4910 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4911 return -EINVAL;
4912 }
4913
4914 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4915 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4916 return -EINVAL;
4917 }
4918
4919 hr_reg_write(context, QPC_UDPSPN,
4920 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4921 attr->dest_qp_num) :
4922 0);
4923
4924 hr_reg_clear(qpc_mask, QPC_UDPSPN);
4925
4926 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4927
4928 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4929
4930 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4931 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4932
4933 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4934 if (ret)
4935 return ret;
4936
4937 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4938 hr_reg_clear(qpc_mask, QPC_TC);
4939
4940 hr_reg_write(context, QPC_FL, grh->flow_label);
4941 hr_reg_clear(qpc_mask, QPC_FL);
4942 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4943 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4944
4945 hr_qp->sl = sl;
4946 hr_reg_write(context, QPC_SL, hr_qp->sl);
4947 hr_reg_clear(qpc_mask, QPC_SL);
4948
4949 return 0;
4950 }
4951
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)4952 static bool check_qp_state(enum ib_qp_state cur_state,
4953 enum ib_qp_state new_state)
4954 {
4955 static const bool sm[][IB_QPS_ERR + 1] = {
4956 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4957 [IB_QPS_INIT] = true },
4958 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4959 [IB_QPS_INIT] = true,
4960 [IB_QPS_RTR] = true,
4961 [IB_QPS_ERR] = true },
4962 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4963 [IB_QPS_RTS] = true,
4964 [IB_QPS_ERR] = true },
4965 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4966 [IB_QPS_RTS] = true,
4967 [IB_QPS_ERR] = true },
4968 [IB_QPS_SQD] = {},
4969 [IB_QPS_SQE] = {},
4970 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4971 [IB_QPS_ERR] = true }
4972 };
4973
4974 return sm[cur_state][new_state];
4975 }
4976
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4977 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4978 const struct ib_qp_attr *attr,
4979 int attr_mask,
4980 enum ib_qp_state cur_state,
4981 enum ib_qp_state new_state,
4982 struct hns_roce_v2_qp_context *context,
4983 struct hns_roce_v2_qp_context *qpc_mask,
4984 struct ib_udata *udata)
4985 {
4986 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4987 int ret = 0;
4988
4989 if (!check_qp_state(cur_state, new_state)) {
4990 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4991 return -EINVAL;
4992 }
4993
4994 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4995 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4996 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
4997 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4998 modify_qp_init_to_init(ibqp, attr, context, qpc_mask);
4999 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5000 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5001 qpc_mask, udata);
5002 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5003 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
5004 qpc_mask);
5005 }
5006
5007 return ret;
5008 }
5009
check_qp_timeout_cfg_range(struct hns_roce_dev * hr_dev,u8 * timeout)5010 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5011 {
5012 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5013 #define QP_ACK_TIMEOUT_MAX 31
5014
5015 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5016 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5017 ibdev_warn(&hr_dev->ib_dev,
5018 "local ACK timeout shall be 0 to 20.\n");
5019 return false;
5020 }
5021 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5022 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5023 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5024 ibdev_warn(&hr_dev->ib_dev,
5025 "local ACK timeout shall be 0 to 31.\n");
5026 return false;
5027 }
5028 }
5029
5030 return true;
5031 }
5032
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5033 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5034 const struct ib_qp_attr *attr,
5035 int attr_mask,
5036 struct hns_roce_v2_qp_context *context,
5037 struct hns_roce_v2_qp_context *qpc_mask)
5038 {
5039 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5040 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5041 int ret = 0;
5042 u8 timeout;
5043
5044 if (attr_mask & IB_QP_AV) {
5045 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5046 qpc_mask);
5047 if (ret)
5048 return ret;
5049 }
5050
5051 if (attr_mask & IB_QP_TIMEOUT) {
5052 timeout = attr->timeout;
5053 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5054 hr_reg_write(context, QPC_AT, timeout);
5055 hr_reg_clear(qpc_mask, QPC_AT);
5056 }
5057 }
5058
5059 if (attr_mask & IB_QP_RETRY_CNT) {
5060 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5061 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5062
5063 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5064 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5065 }
5066
5067 if (attr_mask & IB_QP_RNR_RETRY) {
5068 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5069 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5070
5071 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5072 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5073 }
5074
5075 if (attr_mask & IB_QP_SQ_PSN) {
5076 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5077 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5078
5079 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5080 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5081
5082 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5083 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5084
5085 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5086 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5087 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5088
5089 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5090 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5091
5092 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5093 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5094 }
5095
5096 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5097 attr->max_dest_rd_atomic) {
5098 hr_reg_write(context, QPC_RR_MAX,
5099 fls(attr->max_dest_rd_atomic - 1));
5100 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5101 }
5102
5103 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5104 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5105 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5106 }
5107
5108 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5109 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5110
5111 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5112 hr_reg_write(context, QPC_MIN_RNR_TIME,
5113 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5114 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5115 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5116 }
5117
5118 if (attr_mask & IB_QP_RQ_PSN) {
5119 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5120 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5121
5122 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5123 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5124 }
5125
5126 if (attr_mask & IB_QP_QKEY) {
5127 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5128 qpc_mask->qkey_xrcd = 0;
5129 hr_qp->qkey = attr->qkey;
5130 }
5131
5132 return ret;
5133 }
5134
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)5135 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5136 const struct ib_qp_attr *attr,
5137 int attr_mask)
5138 {
5139 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5140 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5141
5142 if (attr_mask & IB_QP_ACCESS_FLAGS)
5143 hr_qp->atomic_rd_en = attr->qp_access_flags;
5144
5145 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5146 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5147 if (attr_mask & IB_QP_PORT) {
5148 hr_qp->port = attr->port_num - 1;
5149 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5150 }
5151 }
5152
clear_qp(struct hns_roce_qp * hr_qp)5153 static void clear_qp(struct hns_roce_qp *hr_qp)
5154 {
5155 struct ib_qp *ibqp = &hr_qp->ibqp;
5156
5157 if (ibqp->send_cq)
5158 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5159 hr_qp->qpn, NULL);
5160
5161 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5162 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5163 hr_qp->qpn, ibqp->srq ?
5164 to_hr_srq(ibqp->srq) : NULL);
5165
5166 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5167 *hr_qp->rdb.db_record = 0;
5168
5169 hr_qp->rq.head = 0;
5170 hr_qp->rq.tail = 0;
5171 hr_qp->sq.head = 0;
5172 hr_qp->sq.tail = 0;
5173 hr_qp->next_sge = 0;
5174 }
5175
v2_set_flushed_fields(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5176 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5177 struct hns_roce_v2_qp_context *context,
5178 struct hns_roce_v2_qp_context *qpc_mask)
5179 {
5180 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5181 unsigned long sq_flag = 0;
5182 unsigned long rq_flag = 0;
5183
5184 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5185 return;
5186
5187 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5188 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5189 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5190 hr_qp->state = IB_QPS_ERR;
5191 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5192
5193 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5194 return;
5195
5196 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5197 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5198 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5199 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5200 }
5201
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)5202 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5203 const struct ib_qp_attr *attr,
5204 int attr_mask, enum ib_qp_state cur_state,
5205 enum ib_qp_state new_state, struct ib_udata *udata)
5206 {
5207 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5208 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5209 struct hns_roce_v2_qp_context ctx[2];
5210 struct hns_roce_v2_qp_context *context = ctx;
5211 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5212 struct ib_device *ibdev = &hr_dev->ib_dev;
5213 int ret;
5214
5215 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5216 return -EOPNOTSUPP;
5217
5218 /*
5219 * In v2 engine, software pass context and context mask to hardware
5220 * when modifying qp. If software need modify some fields in context,
5221 * we should set all bits of the relevant fields in context mask to
5222 * 0 at the same time, else set them to 0x1.
5223 */
5224 memset(context, 0, hr_dev->caps.qpc_sz);
5225 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5226
5227 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5228 new_state, context, qpc_mask, udata);
5229 if (ret)
5230 goto out;
5231
5232 /* When QP state is err, SQ and RQ WQE should be flushed */
5233 if (new_state == IB_QPS_ERR)
5234 v2_set_flushed_fields(ibqp, context, qpc_mask);
5235
5236 /* Configure the optional fields */
5237 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5238 qpc_mask);
5239 if (ret)
5240 goto out;
5241
5242 hr_reg_write_bool(context, QPC_INV_CREDIT,
5243 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5244 ibqp->srq);
5245 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5246
5247 /* Every status migrate must change state */
5248 hr_reg_write(context, QPC_QP_ST, new_state);
5249 hr_reg_clear(qpc_mask, QPC_QP_ST);
5250
5251 /* SW pass context to HW */
5252 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5253 if (ret) {
5254 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5255 goto out;
5256 }
5257
5258 hr_qp->state = new_state;
5259
5260 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5261
5262 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5263 clear_qp(hr_qp);
5264
5265 out:
5266 return ret;
5267 }
5268
to_ib_qp_st(enum hns_roce_v2_qp_state state)5269 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5270 {
5271 static const enum ib_qp_state map[] = {
5272 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5273 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5274 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5275 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5276 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5277 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5278 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5279 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5280 };
5281
5282 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5283 }
5284
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,u32 qpn,void * buffer)5285 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5286 void *buffer)
5287 {
5288 struct hns_roce_cmd_mailbox *mailbox;
5289 int ret;
5290
5291 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5292 if (IS_ERR(mailbox))
5293 return PTR_ERR(mailbox);
5294
5295 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5296 qpn);
5297 if (ret)
5298 goto out;
5299
5300 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5301
5302 out:
5303 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5304 return ret;
5305 }
5306
get_qp_timeout_attr(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context)5307 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5308 struct hns_roce_v2_qp_context *context)
5309 {
5310 u8 timeout;
5311
5312 timeout = (u8)hr_reg_read(context, QPC_AT);
5313 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5314 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5315
5316 return timeout;
5317 }
5318
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)5319 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5320 int qp_attr_mask,
5321 struct ib_qp_init_attr *qp_init_attr)
5322 {
5323 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5324 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5325 struct hns_roce_v2_qp_context context = {};
5326 struct ib_device *ibdev = &hr_dev->ib_dev;
5327 int tmp_qp_state;
5328 int state;
5329 int ret;
5330
5331 memset(qp_attr, 0, sizeof(*qp_attr));
5332 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5333
5334 mutex_lock(&hr_qp->mutex);
5335
5336 if (hr_qp->state == IB_QPS_RESET) {
5337 qp_attr->qp_state = IB_QPS_RESET;
5338 ret = 0;
5339 goto done;
5340 }
5341
5342 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5343 if (ret) {
5344 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5345 ret = -EINVAL;
5346 goto out;
5347 }
5348
5349 state = hr_reg_read(&context, QPC_QP_ST);
5350 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5351 if (tmp_qp_state == -1) {
5352 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5353 ret = -EINVAL;
5354 goto out;
5355 }
5356 hr_qp->state = (u8)tmp_qp_state;
5357 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5358 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5359 qp_attr->path_mig_state = IB_MIG_ARMED;
5360 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5361 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5362 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5363
5364 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5365 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5366 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5367 qp_attr->qp_access_flags =
5368 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5369 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5370 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5371
5372 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5373 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5374 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5375 struct ib_global_route *grh =
5376 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5377
5378 rdma_ah_set_sl(&qp_attr->ah_attr,
5379 hr_reg_read(&context, QPC_SL));
5380 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5381 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5382 grh->flow_label = hr_reg_read(&context, QPC_FL);
5383 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5384 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5385 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5386
5387 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5388 }
5389
5390 qp_attr->port_num = hr_qp->port + 1;
5391 qp_attr->sq_draining = 0;
5392 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5393 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5394
5395 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5396 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5397 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5398 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5399
5400 done:
5401 qp_attr->cur_qp_state = qp_attr->qp_state;
5402 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5403 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5404 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5405
5406 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5407 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5408
5409 qp_init_attr->qp_context = ibqp->qp_context;
5410 qp_init_attr->qp_type = ibqp->qp_type;
5411 qp_init_attr->recv_cq = ibqp->recv_cq;
5412 qp_init_attr->send_cq = ibqp->send_cq;
5413 qp_init_attr->srq = ibqp->srq;
5414 qp_init_attr->cap = qp_attr->cap;
5415 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5416
5417 out:
5418 mutex_unlock(&hr_qp->mutex);
5419 return ret;
5420 }
5421
modify_qp_is_ok(struct hns_roce_qp * hr_qp)5422 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5423 {
5424 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5425 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5426 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5427 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5428 hr_qp->state != IB_QPS_RESET);
5429 }
5430
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5431 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5432 struct hns_roce_qp *hr_qp,
5433 struct ib_udata *udata)
5434 {
5435 struct ib_device *ibdev = &hr_dev->ib_dev;
5436 struct hns_roce_cq *send_cq, *recv_cq;
5437 unsigned long flags;
5438 int ret = 0;
5439
5440 if (modify_qp_is_ok(hr_qp)) {
5441 /* Modify qp to reset before destroying qp */
5442 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5443 hr_qp->state, IB_QPS_RESET, udata);
5444 if (ret)
5445 ibdev_err(ibdev,
5446 "failed to modify QP to RST, ret = %d.\n",
5447 ret);
5448 }
5449
5450 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5451 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5452
5453 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5454 hns_roce_lock_cqs(send_cq, recv_cq);
5455
5456 if (!udata) {
5457 if (recv_cq)
5458 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5459 (hr_qp->ibqp.srq ?
5460 to_hr_srq(hr_qp->ibqp.srq) :
5461 NULL));
5462
5463 if (send_cq && send_cq != recv_cq)
5464 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5465 }
5466
5467 hns_roce_qp_remove(hr_dev, hr_qp);
5468
5469 hns_roce_unlock_cqs(send_cq, recv_cq);
5470 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5471
5472 return ret;
5473 }
5474
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5475 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5476 {
5477 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5478 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5479 int ret;
5480
5481 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5482 if (ret)
5483 ibdev_err(&hr_dev->ib_dev,
5484 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5485 hr_qp->qpn, ret);
5486
5487 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5488
5489 return 0;
5490 }
5491
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5492 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5493 struct hns_roce_qp *hr_qp)
5494 {
5495 struct ib_device *ibdev = &hr_dev->ib_dev;
5496 struct hns_roce_sccc_clr_done *resp;
5497 struct hns_roce_sccc_clr *clr;
5498 struct hns_roce_cmq_desc desc;
5499 int ret, i;
5500
5501 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5502 return 0;
5503
5504 mutex_lock(&hr_dev->qp_table.scc_mutex);
5505
5506 /* set scc ctx clear done flag */
5507 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5508 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5509 if (ret) {
5510 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5511 goto out;
5512 }
5513
5514 /* clear scc context */
5515 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5516 clr = (struct hns_roce_sccc_clr *)desc.data;
5517 clr->qpn = cpu_to_le32(hr_qp->qpn);
5518 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5519 if (ret) {
5520 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5521 goto out;
5522 }
5523
5524 /* query scc context clear is done or not */
5525 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5526 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5527 hns_roce_cmq_setup_basic_desc(&desc,
5528 HNS_ROCE_OPC_QUERY_SCCC, true);
5529 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5530 if (ret) {
5531 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5532 ret);
5533 goto out;
5534 }
5535
5536 if (resp->clr_done)
5537 goto out;
5538
5539 msleep(20);
5540 }
5541
5542 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5543 ret = -ETIMEDOUT;
5544
5545 out:
5546 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5547 return ret;
5548 }
5549
5550 #define DMA_IDX_SHIFT 3
5551 #define DMA_WQE_SHIFT 3
5552
hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq * srq,struct hns_roce_srq_context * ctx)5553 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5554 struct hns_roce_srq_context *ctx)
5555 {
5556 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5557 struct ib_device *ibdev = srq->ibsrq.device;
5558 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5559 u64 mtts_idx[MTT_MIN_COUNT] = {};
5560 dma_addr_t dma_handle_idx = 0;
5561 int ret;
5562
5563 /* Get physical address of idx que buf */
5564 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5565 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5566 if (ret < 1) {
5567 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5568 ret);
5569 return -ENOBUFS;
5570 }
5571
5572 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5573 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5574
5575 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5576 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5577 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5578
5579 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5580 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5581 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5582 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5583
5584 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5585 to_hr_hw_page_addr(mtts_idx[0]));
5586 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5587 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5588
5589 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5590 to_hr_hw_page_addr(mtts_idx[1]));
5591 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5592 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5593
5594 return 0;
5595 }
5596
hns_roce_v2_write_srqc(struct hns_roce_srq * srq,void * mb_buf)5597 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5598 {
5599 struct ib_device *ibdev = srq->ibsrq.device;
5600 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5601 struct hns_roce_srq_context *ctx = mb_buf;
5602 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5603 dma_addr_t dma_handle_wqe = 0;
5604 int ret;
5605
5606 memset(ctx, 0, sizeof(*ctx));
5607
5608 /* Get the physical address of srq buf */
5609 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5610 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5611 if (ret < 1) {
5612 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5613 ret);
5614 return -ENOBUFS;
5615 }
5616
5617 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5618 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5619 srq->ibsrq.srq_type == IB_SRQT_XRC);
5620 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5621 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5622 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5623 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5624 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5625 hr_reg_write(ctx, SRQC_RQWS,
5626 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5627
5628 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5629 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5630 srq->wqe_cnt));
5631
5632 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5633 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5634 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5635
5636 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5637 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5638 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5639 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5640
5641 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5642 }
5643
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5644 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5645 struct ib_srq_attr *srq_attr,
5646 enum ib_srq_attr_mask srq_attr_mask,
5647 struct ib_udata *udata)
5648 {
5649 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5650 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5651 struct hns_roce_srq_context *srq_context;
5652 struct hns_roce_srq_context *srqc_mask;
5653 struct hns_roce_cmd_mailbox *mailbox;
5654 int ret;
5655
5656 /* Resizing SRQs is not supported yet */
5657 if (srq_attr_mask & IB_SRQ_MAX_WR)
5658 return -EOPNOTSUPP;
5659
5660 if (srq_attr_mask & IB_SRQ_LIMIT) {
5661 if (srq_attr->srq_limit > srq->wqe_cnt)
5662 return -EINVAL;
5663
5664 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5665 if (IS_ERR(mailbox))
5666 return PTR_ERR(mailbox);
5667
5668 srq_context = mailbox->buf;
5669 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5670
5671 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5672
5673 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5674 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5675
5676 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5677 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5678 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5679 if (ret) {
5680 ibdev_err(&hr_dev->ib_dev,
5681 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5682 ret);
5683 return ret;
5684 }
5685 }
5686
5687 return 0;
5688 }
5689
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)5690 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5691 {
5692 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5693 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5694 struct hns_roce_srq_context *srq_context;
5695 struct hns_roce_cmd_mailbox *mailbox;
5696 int ret;
5697
5698 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5699 if (IS_ERR(mailbox))
5700 return PTR_ERR(mailbox);
5701
5702 srq_context = mailbox->buf;
5703 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5704 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5705 if (ret) {
5706 ibdev_err(&hr_dev->ib_dev,
5707 "failed to process cmd of querying SRQ, ret = %d.\n",
5708 ret);
5709 goto out;
5710 }
5711
5712 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5713 attr->max_wr = srq->wqe_cnt;
5714 attr->max_sge = srq->max_gs - srq->rsv_sge;
5715
5716 out:
5717 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5718 return ret;
5719 }
5720
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)5721 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5722 {
5723 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5724 struct hns_roce_v2_cq_context *cq_context;
5725 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5726 struct hns_roce_v2_cq_context *cqc_mask;
5727 struct hns_roce_cmd_mailbox *mailbox;
5728 int ret;
5729
5730 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5731 if (IS_ERR(mailbox))
5732 return PTR_ERR(mailbox);
5733
5734 cq_context = mailbox->buf;
5735 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5736
5737 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5738
5739 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5740 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5741
5742 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5743 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5744 dev_info(hr_dev->dev,
5745 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5746 cq_period);
5747 cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5748 }
5749 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5750 }
5751 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5752 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5753
5754 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5755 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5756 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5757 if (ret)
5758 ibdev_err(&hr_dev->ib_dev,
5759 "failed to process cmd when modifying CQ, ret = %d.\n",
5760 ret);
5761
5762 return ret;
5763 }
5764
hns_roce_v2_query_cqc(struct hns_roce_dev * hr_dev,u32 cqn,void * buffer)5765 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5766 void *buffer)
5767 {
5768 struct hns_roce_v2_cq_context *context;
5769 struct hns_roce_cmd_mailbox *mailbox;
5770 int ret;
5771
5772 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5773 if (IS_ERR(mailbox))
5774 return PTR_ERR(mailbox);
5775
5776 context = mailbox->buf;
5777 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5778 HNS_ROCE_CMD_QUERY_CQC, cqn);
5779 if (ret) {
5780 ibdev_err(&hr_dev->ib_dev,
5781 "failed to process cmd when querying CQ, ret = %d.\n",
5782 ret);
5783 goto err_mailbox;
5784 }
5785
5786 memcpy(buffer, context, sizeof(*context));
5787
5788 err_mailbox:
5789 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5790
5791 return ret;
5792 }
5793
hns_roce_v2_query_mpt(struct hns_roce_dev * hr_dev,u32 key,void * buffer)5794 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5795 void *buffer)
5796 {
5797 struct hns_roce_v2_mpt_entry *context;
5798 struct hns_roce_cmd_mailbox *mailbox;
5799 int ret;
5800
5801 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5802 if (IS_ERR(mailbox))
5803 return PTR_ERR(mailbox);
5804
5805 context = mailbox->buf;
5806 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5807 key_to_hw_index(key));
5808 if (ret) {
5809 ibdev_err(&hr_dev->ib_dev,
5810 "failed to process cmd when querying MPT, ret = %d.\n",
5811 ret);
5812 goto err_mailbox;
5813 }
5814
5815 memcpy(buffer, context, sizeof(*context));
5816
5817 err_mailbox:
5818 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5819
5820 return ret;
5821 }
5822
hns_roce_irq_work_handle(struct work_struct * work)5823 static void hns_roce_irq_work_handle(struct work_struct *work)
5824 {
5825 struct hns_roce_work *irq_work =
5826 container_of(work, struct hns_roce_work, work);
5827 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5828
5829 switch (irq_work->event_type) {
5830 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5831 ibdev_info(ibdev, "path migrated succeeded.\n");
5832 break;
5833 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5834 ibdev_warn(ibdev, "path migration failed.\n");
5835 break;
5836 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5837 break;
5838 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5839 ibdev_dbg(ibdev, "send queue drained.\n");
5840 break;
5841 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5842 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5843 irq_work->queue_num, irq_work->sub_type);
5844 break;
5845 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5846 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5847 irq_work->queue_num);
5848 break;
5849 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5850 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5851 irq_work->queue_num, irq_work->sub_type);
5852 break;
5853 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5854 ibdev_dbg(ibdev, "SRQ limit reach.\n");
5855 break;
5856 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5857 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
5858 break;
5859 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5860 ibdev_err(ibdev, "SRQ catas error.\n");
5861 break;
5862 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5863 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5864 break;
5865 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5866 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5867 break;
5868 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5869 ibdev_warn(ibdev, "DB overflow.\n");
5870 break;
5871 case HNS_ROCE_EVENT_TYPE_FLR:
5872 ibdev_warn(ibdev, "function level reset.\n");
5873 break;
5874 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5875 ibdev_err(ibdev, "xrc domain violation error.\n");
5876 break;
5877 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5878 ibdev_err(ibdev, "invalid xrceth error.\n");
5879 break;
5880 default:
5881 break;
5882 }
5883
5884 kfree(irq_work);
5885 }
5886
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 queue_num)5887 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5888 struct hns_roce_eq *eq, u32 queue_num)
5889 {
5890 struct hns_roce_work *irq_work;
5891
5892 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5893 if (!irq_work)
5894 return;
5895
5896 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5897 irq_work->hr_dev = hr_dev;
5898 irq_work->event_type = eq->event_type;
5899 irq_work->sub_type = eq->sub_type;
5900 irq_work->queue_num = queue_num;
5901 queue_work(hr_dev->irq_workq, &irq_work->work);
5902 }
5903
update_eq_db(struct hns_roce_eq * eq)5904 static void update_eq_db(struct hns_roce_eq *eq)
5905 {
5906 struct hns_roce_dev *hr_dev = eq->hr_dev;
5907 struct hns_roce_v2_db eq_db = {};
5908
5909 if (eq->type_flag == HNS_ROCE_AEQ) {
5910 hr_reg_write(&eq_db, EQ_DB_CMD,
5911 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5912 HNS_ROCE_EQ_DB_CMD_AEQ :
5913 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5914 } else {
5915 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5916
5917 hr_reg_write(&eq_db, EQ_DB_CMD,
5918 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5919 HNS_ROCE_EQ_DB_CMD_CEQ :
5920 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5921 }
5922
5923 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5924
5925 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5926 }
5927
next_aeqe_sw_v2(struct hns_roce_eq * eq)5928 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5929 {
5930 struct hns_roce_aeqe *aeqe;
5931
5932 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5933 (eq->cons_index & (eq->entries - 1)) *
5934 eq->eqe_size);
5935
5936 return (hr_reg_read(aeqe, AEQE_OWNER) ^
5937 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5938 }
5939
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5940 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5941 struct hns_roce_eq *eq)
5942 {
5943 struct device *dev = hr_dev->dev;
5944 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5945 irqreturn_t aeqe_found = IRQ_NONE;
5946 int event_type;
5947 u32 queue_num;
5948 int sub_type;
5949
5950 while (aeqe) {
5951 /* Make sure we read AEQ entry after we have checked the
5952 * ownership bit
5953 */
5954 dma_rmb();
5955
5956 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
5957 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
5958 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
5959
5960 switch (event_type) {
5961 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5962 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5963 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5964 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5965 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5966 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5967 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5968 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5969 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5970 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5971 hns_roce_qp_event(hr_dev, queue_num, event_type);
5972 break;
5973 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5974 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5975 hns_roce_srq_event(hr_dev, queue_num, event_type);
5976 break;
5977 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5978 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5979 hns_roce_cq_event(hr_dev, queue_num, event_type);
5980 break;
5981 case HNS_ROCE_EVENT_TYPE_MB:
5982 hns_roce_cmd_event(hr_dev,
5983 le16_to_cpu(aeqe->event.cmd.token),
5984 aeqe->event.cmd.status,
5985 le64_to_cpu(aeqe->event.cmd.out_param));
5986 break;
5987 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5988 case HNS_ROCE_EVENT_TYPE_FLR:
5989 break;
5990 default:
5991 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n",
5992 event_type, eq->eqn, eq->cons_index);
5993 break;
5994 }
5995
5996 eq->event_type = event_type;
5997 eq->sub_type = sub_type;
5998 ++eq->cons_index;
5999 aeqe_found = IRQ_HANDLED;
6000
6001 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6002
6003 aeqe = next_aeqe_sw_v2(eq);
6004 }
6005
6006 update_eq_db(eq);
6007
6008 return IRQ_RETVAL(aeqe_found);
6009 }
6010
next_ceqe_sw_v2(struct hns_roce_eq * eq)6011 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6012 {
6013 struct hns_roce_ceqe *ceqe;
6014
6015 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6016 (eq->cons_index & (eq->entries - 1)) *
6017 eq->eqe_size);
6018
6019 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6020 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6021 }
6022
hns_roce_v2_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6023 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6024 struct hns_roce_eq *eq)
6025 {
6026 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6027 irqreturn_t ceqe_found = IRQ_NONE;
6028 u32 cqn;
6029
6030 while (ceqe) {
6031 /* Make sure we read CEQ entry after we have checked the
6032 * ownership bit
6033 */
6034 dma_rmb();
6035
6036 cqn = hr_reg_read(ceqe, CEQE_CQN);
6037
6038 hns_roce_cq_completion(hr_dev, cqn);
6039
6040 ++eq->cons_index;
6041 ceqe_found = IRQ_HANDLED;
6042
6043 ceqe = next_ceqe_sw_v2(eq);
6044 }
6045
6046 update_eq_db(eq);
6047
6048 return IRQ_RETVAL(ceqe_found);
6049 }
6050
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)6051 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6052 {
6053 struct hns_roce_eq *eq = eq_ptr;
6054 struct hns_roce_dev *hr_dev = eq->hr_dev;
6055 irqreturn_t int_work;
6056
6057 if (eq->type_flag == HNS_ROCE_CEQ)
6058 /* Completion event interrupt */
6059 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6060 else
6061 /* Asynchronous event interrupt */
6062 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6063
6064 return IRQ_RETVAL(int_work);
6065 }
6066
abnormal_interrupt_basic(struct hns_roce_dev * hr_dev,u32 int_st)6067 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6068 u32 int_st)
6069 {
6070 struct pci_dev *pdev = hr_dev->pci_dev;
6071 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6072 const struct hnae3_ae_ops *ops = ae_dev->ops;
6073 enum hnae3_reset_type reset_type;
6074 irqreturn_t int_work = IRQ_NONE;
6075 u32 int_en;
6076
6077 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6078
6079 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6080 dev_err(hr_dev->dev, "AEQ overflow!\n");
6081
6082 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6083 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6084
6085 reset_type = hr_dev->is_vf ?
6086 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET;
6087
6088 /* Set reset level for reset_event() */
6089 if (ops->set_default_reset_request)
6090 ops->set_default_reset_request(ae_dev, reset_type);
6091 if (ops->reset_event)
6092 ops->reset_event(pdev, NULL);
6093
6094 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6095 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6096
6097 int_work = IRQ_HANDLED;
6098 } else {
6099 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6100 }
6101
6102 return IRQ_RETVAL(int_work);
6103 }
6104
fmea_ram_ecc_query(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6105 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6106 struct fmea_ram_ecc *ecc_info)
6107 {
6108 struct hns_roce_cmq_desc desc;
6109 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6110 int ret;
6111
6112 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6113 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6114 if (ret)
6115 return ret;
6116
6117 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6118 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6119 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6120
6121 return 0;
6122 }
6123
fmea_recover_gmv(struct hns_roce_dev * hr_dev,u32 idx)6124 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6125 {
6126 struct hns_roce_cmq_desc desc;
6127 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6128 u32 addr_upper;
6129 u32 addr_low;
6130 int ret;
6131
6132 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6133 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6134
6135 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6136 if (ret) {
6137 dev_err(hr_dev->dev,
6138 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6139 return ret;
6140 }
6141
6142 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6143 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6144
6145 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6146 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6147 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6148 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6149
6150 return hns_roce_cmq_send(hr_dev, &desc, 1);
6151 }
6152
fmea_get_ram_res_addr(u32 res_type,__le64 * data)6153 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6154 {
6155 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6156 res_type == ECC_RESOURCE_CQC_TIMER ||
6157 res_type == ECC_RESOURCE_SCCC)
6158 return le64_to_cpu(*data);
6159
6160 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT;
6161 }
6162
fmea_recover_others(struct hns_roce_dev * hr_dev,u32 res_type,u32 index)6163 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6164 u32 index)
6165 {
6166 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6167 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6168 struct hns_roce_cmd_mailbox *mailbox;
6169 u64 addr;
6170 int ret;
6171
6172 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6173 if (IS_ERR(mailbox))
6174 return PTR_ERR(mailbox);
6175
6176 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6177 if (ret) {
6178 dev_err(hr_dev->dev,
6179 "failed to execute cmd to read fmea ram, ret = %d.\n",
6180 ret);
6181 goto out;
6182 }
6183
6184 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6185
6186 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6187 if (ret)
6188 dev_err(hr_dev->dev,
6189 "failed to execute cmd to write fmea ram, ret = %d.\n",
6190 ret);
6191
6192 out:
6193 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6194 return ret;
6195 }
6196
fmea_ram_ecc_recover(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6197 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6198 struct fmea_ram_ecc *ecc_info)
6199 {
6200 u32 res_type = ecc_info->res_type;
6201 u32 index = ecc_info->index;
6202 int ret;
6203
6204 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6205
6206 if (res_type >= ECC_RESOURCE_COUNT) {
6207 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6208 res_type);
6209 return;
6210 }
6211
6212 if (res_type == ECC_RESOURCE_GMV)
6213 ret = fmea_recover_gmv(hr_dev, index);
6214 else
6215 ret = fmea_recover_others(hr_dev, res_type, index);
6216 if (ret)
6217 dev_err(hr_dev->dev,
6218 "failed to recover %s, index = %u, ret = %d.\n",
6219 fmea_ram_res[res_type].name, index, ret);
6220 }
6221
fmea_ram_ecc_work(struct work_struct * ecc_work)6222 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6223 {
6224 struct hns_roce_dev *hr_dev =
6225 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6226 struct fmea_ram_ecc ecc_info = {};
6227
6228 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6229 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6230 return;
6231 }
6232
6233 if (!ecc_info.is_ecc_err) {
6234 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6235 return;
6236 }
6237
6238 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6239 }
6240
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)6241 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6242 {
6243 struct hns_roce_dev *hr_dev = dev_id;
6244 irqreturn_t int_work = IRQ_NONE;
6245 u32 int_st;
6246
6247 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6248
6249 if (int_st) {
6250 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6251 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6252 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6253 int_work = IRQ_HANDLED;
6254 } else {
6255 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6256 }
6257
6258 return IRQ_RETVAL(int_work);
6259 }
6260
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,u32 enable_flag)6261 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6262 int eq_num, u32 enable_flag)
6263 {
6264 int i;
6265
6266 for (i = 0; i < eq_num; i++)
6267 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6268 i * EQ_REG_OFFSET, enable_flag);
6269
6270 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6271 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6272 }
6273
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6274 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6275 {
6276 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6277 }
6278
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6279 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6280 struct hns_roce_eq *eq)
6281 {
6282 struct device *dev = hr_dev->dev;
6283 int eqn = eq->eqn;
6284 int ret;
6285 u8 cmd;
6286
6287 if (eqn < hr_dev->caps.num_comp_vectors)
6288 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6289 else
6290 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6291
6292 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6293 if (ret)
6294 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6295
6296 free_eq_buf(hr_dev, eq);
6297 }
6298
init_eq_config(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6299 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6300 {
6301 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6302 eq->cons_index = 0;
6303 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6304 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6305 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6306 eq->shift = ilog2((unsigned int)eq->entries);
6307 }
6308
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)6309 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6310 void *mb_buf)
6311 {
6312 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6313 struct hns_roce_eq_context *eqc;
6314 u64 bt_ba = 0;
6315 int count;
6316
6317 eqc = mb_buf;
6318 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6319
6320 init_eq_config(hr_dev, eq);
6321
6322 /* if not multi-hop, eqe buffer only use one trunk */
6323 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
6324 &bt_ba);
6325 if (count < 1) {
6326 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
6327 return -ENOBUFS;
6328 }
6329
6330 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6331 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6332 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6333 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6334 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6335 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6336 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6337 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6338 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6339 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6340 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6341 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6342 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6343
6344 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6345 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6346 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6347 eq->eq_period);
6348 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6349 }
6350 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6351 }
6352
6353 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6354 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6355 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6356 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6357 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6358 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6359 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6360 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6361 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6362 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6363 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6364 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6365 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6366
6367 return 0;
6368 }
6369
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6370 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6371 {
6372 struct hns_roce_buf_attr buf_attr = {};
6373 int err;
6374
6375 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6376 eq->hop_num = 0;
6377 else
6378 eq->hop_num = hr_dev->caps.eqe_hop_num;
6379
6380 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6381 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6382 buf_attr.region[0].hopnum = eq->hop_num;
6383 buf_attr.region_count = 1;
6384
6385 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6386 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6387 0);
6388 if (err)
6389 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6390
6391 return err;
6392 }
6393
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u8 eq_cmd)6394 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6395 struct hns_roce_eq *eq, u8 eq_cmd)
6396 {
6397 struct hns_roce_cmd_mailbox *mailbox;
6398 int ret;
6399
6400 /* Allocate mailbox memory */
6401 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6402 if (IS_ERR(mailbox))
6403 return PTR_ERR(mailbox);
6404
6405 ret = alloc_eq_buf(hr_dev, eq);
6406 if (ret)
6407 goto free_cmd_mbox;
6408
6409 ret = config_eqc(hr_dev, eq, mailbox->buf);
6410 if (ret)
6411 goto err_cmd_mbox;
6412
6413 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6414 if (ret) {
6415 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6416 goto err_cmd_mbox;
6417 }
6418
6419 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6420
6421 return 0;
6422
6423 err_cmd_mbox:
6424 free_eq_buf(hr_dev, eq);
6425
6426 free_cmd_mbox:
6427 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6428
6429 return ret;
6430 }
6431
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)6432 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6433 int comp_num, int aeq_num, int other_num)
6434 {
6435 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6436 int i, j;
6437 int ret;
6438
6439 for (i = 0; i < irq_num; i++) {
6440 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6441 GFP_KERNEL);
6442 if (!hr_dev->irq_names[i]) {
6443 ret = -ENOMEM;
6444 goto err_kzalloc_failed;
6445 }
6446 }
6447
6448 /* irq contains: abnormal + AEQ + CEQ */
6449 for (j = 0; j < other_num; j++)
6450 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6451 "hns-abn-%d", j);
6452
6453 for (j = other_num; j < (other_num + aeq_num); j++)
6454 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6455 "hns-aeq-%d", j - other_num);
6456
6457 for (j = (other_num + aeq_num); j < irq_num; j++)
6458 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6459 "hns-ceq-%d", j - other_num - aeq_num);
6460
6461 for (j = 0; j < irq_num; j++) {
6462 if (j < other_num)
6463 ret = request_irq(hr_dev->irq[j],
6464 hns_roce_v2_msix_interrupt_abn,
6465 0, hr_dev->irq_names[j], hr_dev);
6466
6467 else if (j < (other_num + comp_num))
6468 ret = request_irq(eq_table->eq[j - other_num].irq,
6469 hns_roce_v2_msix_interrupt_eq,
6470 0, hr_dev->irq_names[j + aeq_num],
6471 &eq_table->eq[j - other_num]);
6472 else
6473 ret = request_irq(eq_table->eq[j - other_num].irq,
6474 hns_roce_v2_msix_interrupt_eq,
6475 0, hr_dev->irq_names[j - comp_num],
6476 &eq_table->eq[j - other_num]);
6477 if (ret) {
6478 dev_err(hr_dev->dev, "request irq error!\n");
6479 goto err_request_failed;
6480 }
6481 }
6482
6483 return 0;
6484
6485 err_request_failed:
6486 for (j -= 1; j >= 0; j--)
6487 if (j < other_num)
6488 free_irq(hr_dev->irq[j], hr_dev);
6489 else
6490 free_irq(eq_table->eq[j - other_num].irq,
6491 &eq_table->eq[j - other_num]);
6492
6493 err_kzalloc_failed:
6494 for (i -= 1; i >= 0; i--)
6495 kfree(hr_dev->irq_names[i]);
6496
6497 return ret;
6498 }
6499
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6500 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6501 {
6502 int irq_num;
6503 int eq_num;
6504 int i;
6505
6506 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6507 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6508
6509 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6510 free_irq(hr_dev->irq[i], hr_dev);
6511
6512 for (i = 0; i < eq_num; i++)
6513 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6514
6515 for (i = 0; i < irq_num; i++)
6516 kfree(hr_dev->irq_names[i]);
6517 }
6518
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6519 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6520 {
6521 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6522 struct device *dev = hr_dev->dev;
6523 struct hns_roce_eq *eq;
6524 int other_num;
6525 int comp_num;
6526 int aeq_num;
6527 int irq_num;
6528 int eq_num;
6529 u8 eq_cmd;
6530 int ret;
6531 int i;
6532
6533 other_num = hr_dev->caps.num_other_vectors;
6534 comp_num = hr_dev->caps.num_comp_vectors;
6535 aeq_num = hr_dev->caps.num_aeq_vectors;
6536
6537 eq_num = comp_num + aeq_num;
6538 irq_num = eq_num + other_num;
6539
6540 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6541 if (!eq_table->eq)
6542 return -ENOMEM;
6543
6544 /* create eq */
6545 for (i = 0; i < eq_num; i++) {
6546 eq = &eq_table->eq[i];
6547 eq->hr_dev = hr_dev;
6548 eq->eqn = i;
6549 if (i < comp_num) {
6550 /* CEQ */
6551 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6552 eq->type_flag = HNS_ROCE_CEQ;
6553 eq->entries = hr_dev->caps.ceqe_depth;
6554 eq->eqe_size = hr_dev->caps.ceqe_size;
6555 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6556 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6557 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6558 } else {
6559 /* AEQ */
6560 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6561 eq->type_flag = HNS_ROCE_AEQ;
6562 eq->entries = hr_dev->caps.aeqe_depth;
6563 eq->eqe_size = hr_dev->caps.aeqe_size;
6564 eq->irq = hr_dev->irq[i - comp_num + other_num];
6565 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6566 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6567 }
6568
6569 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6570 if (ret) {
6571 dev_err(dev, "failed to create eq.\n");
6572 goto err_create_eq_fail;
6573 }
6574 }
6575
6576 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6577
6578 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6579 if (!hr_dev->irq_workq) {
6580 dev_err(dev, "failed to create irq workqueue.\n");
6581 ret = -ENOMEM;
6582 goto err_create_eq_fail;
6583 }
6584
6585 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6586 other_num);
6587 if (ret) {
6588 dev_err(dev, "failed to request irq.\n");
6589 goto err_request_irq_fail;
6590 }
6591
6592 /* enable irq */
6593 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6594
6595 return 0;
6596
6597 err_request_irq_fail:
6598 destroy_workqueue(hr_dev->irq_workq);
6599
6600 err_create_eq_fail:
6601 for (i -= 1; i >= 0; i--)
6602 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6603 kfree(eq_table->eq);
6604
6605 return ret;
6606 }
6607
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6608 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6609 {
6610 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6611 int eq_num;
6612 int i;
6613
6614 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6615
6616 /* Disable irq */
6617 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6618
6619 __hns_roce_free_irq(hr_dev);
6620 destroy_workqueue(hr_dev->irq_workq);
6621
6622 for (i = 0; i < eq_num; i++)
6623 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6624
6625 kfree(eq_table->eq);
6626 }
6627
6628 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6629 .destroy_qp = hns_roce_v2_destroy_qp,
6630 .modify_cq = hns_roce_v2_modify_cq,
6631 .poll_cq = hns_roce_v2_poll_cq,
6632 .post_recv = hns_roce_v2_post_recv,
6633 .post_send = hns_roce_v2_post_send,
6634 .query_qp = hns_roce_v2_query_qp,
6635 .req_notify_cq = hns_roce_v2_req_notify_cq,
6636 };
6637
6638 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6639 .modify_srq = hns_roce_v2_modify_srq,
6640 .post_srq_recv = hns_roce_v2_post_srq_recv,
6641 .query_srq = hns_roce_v2_query_srq,
6642 };
6643
6644 static const struct hns_roce_hw hns_roce_hw_v2 = {
6645 .cmq_init = hns_roce_v2_cmq_init,
6646 .cmq_exit = hns_roce_v2_cmq_exit,
6647 .hw_profile = hns_roce_v2_profile,
6648 .hw_init = hns_roce_v2_init,
6649 .hw_exit = hns_roce_v2_exit,
6650 .post_mbox = v2_post_mbox,
6651 .poll_mbox_done = v2_poll_mbox_done,
6652 .chk_mbox_avail = v2_chk_mbox_is_avail,
6653 .set_gid = hns_roce_v2_set_gid,
6654 .set_mac = hns_roce_v2_set_mac,
6655 .write_mtpt = hns_roce_v2_write_mtpt,
6656 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6657 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6658 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6659 .write_cqc = hns_roce_v2_write_cqc,
6660 .set_hem = hns_roce_v2_set_hem,
6661 .clear_hem = hns_roce_v2_clear_hem,
6662 .modify_qp = hns_roce_v2_modify_qp,
6663 .dereg_mr = hns_roce_v2_dereg_mr,
6664 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6665 .init_eq = hns_roce_v2_init_eq_table,
6666 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6667 .write_srqc = hns_roce_v2_write_srqc,
6668 .query_cqc = hns_roce_v2_query_cqc,
6669 .query_qpc = hns_roce_v2_query_qpc,
6670 .query_mpt = hns_roce_v2_query_mpt,
6671 .query_hw_counter = hns_roce_hw_v2_query_counter,
6672 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6673 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6674 };
6675
6676 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6677 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6678 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6679 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6680 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6681 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6682 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6683 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6684 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6685 /* required last entry */
6686 {0, }
6687 };
6688
6689 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6690
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)6691 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6692 struct hnae3_handle *handle)
6693 {
6694 struct hns_roce_v2_priv *priv = hr_dev->priv;
6695 const struct pci_device_id *id;
6696 int i;
6697
6698 hr_dev->pci_dev = handle->pdev;
6699 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6700 hr_dev->is_vf = id->driver_data;
6701 hr_dev->dev = &handle->pdev->dev;
6702 hr_dev->hw = &hns_roce_hw_v2;
6703 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6704 hr_dev->odb_offset = hr_dev->sdb_offset;
6705
6706 /* Get info from NIC driver. */
6707 hr_dev->reg_base = handle->rinfo.roce_io_base;
6708 hr_dev->mem_base = handle->rinfo.roce_mem_base;
6709 hr_dev->caps.num_ports = 1;
6710 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6711 hr_dev->iboe.phy_port[0] = 0;
6712
6713 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6714 hr_dev->iboe.netdevs[0]->dev_addr);
6715
6716 for (i = 0; i < handle->rinfo.num_vectors; i++)
6717 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6718 i + handle->rinfo.base_vector);
6719
6720 /* cmd issue mode: 0 is poll, 1 is event */
6721 hr_dev->cmd_mod = 1;
6722 hr_dev->loop_idc = 0;
6723
6724 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6725 priv->handle = handle;
6726 }
6727
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6728 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6729 {
6730 struct hns_roce_dev *hr_dev;
6731 int ret;
6732
6733 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6734 if (!hr_dev)
6735 return -ENOMEM;
6736
6737 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6738 if (!hr_dev->priv) {
6739 ret = -ENOMEM;
6740 goto error_failed_kzalloc;
6741 }
6742
6743 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6744
6745 ret = hns_roce_init(hr_dev);
6746 if (ret) {
6747 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6748 goto error_failed_roce_init;
6749 }
6750
6751 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6752 ret = free_mr_init(hr_dev);
6753 if (ret) {
6754 dev_err(hr_dev->dev, "failed to init free mr!\n");
6755 goto error_failed_free_mr_init;
6756 }
6757 }
6758
6759 handle->priv = hr_dev;
6760
6761 return 0;
6762
6763 error_failed_free_mr_init:
6764 hns_roce_exit(hr_dev);
6765
6766 error_failed_roce_init:
6767 kfree(hr_dev->priv);
6768
6769 error_failed_kzalloc:
6770 ib_dealloc_device(&hr_dev->ib_dev);
6771
6772 return ret;
6773 }
6774
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6775 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6776 bool reset)
6777 {
6778 struct hns_roce_dev *hr_dev = handle->priv;
6779
6780 if (!hr_dev)
6781 return;
6782
6783 handle->priv = NULL;
6784
6785 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6786 hns_roce_handle_device_err(hr_dev);
6787
6788 hns_roce_exit(hr_dev);
6789 kfree(hr_dev->priv);
6790 ib_dealloc_device(&hr_dev->ib_dev);
6791 }
6792
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6793 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6794 {
6795 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6796 const struct pci_device_id *id;
6797 struct device *dev = &handle->pdev->dev;
6798 int ret;
6799
6800 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6801
6802 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6803 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6804 goto reset_chk_err;
6805 }
6806
6807 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6808 if (!id)
6809 return 0;
6810
6811 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6812 return 0;
6813
6814 ret = __hns_roce_hw_v2_init_instance(handle);
6815 if (ret) {
6816 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6817 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6818 if (ops->ae_dev_resetting(handle) ||
6819 ops->get_hw_reset_stat(handle))
6820 goto reset_chk_err;
6821 else
6822 return ret;
6823 }
6824
6825 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6826
6827 return 0;
6828
6829 reset_chk_err:
6830 dev_err(dev, "Device is busy in resetting state.\n"
6831 "please retry later.\n");
6832
6833 return -EBUSY;
6834 }
6835
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6836 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6837 bool reset)
6838 {
6839 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6840 return;
6841
6842 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6843
6844 __hns_roce_hw_v2_uninit_instance(handle, reset);
6845
6846 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6847 }
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)6848 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6849 {
6850 struct hns_roce_dev *hr_dev;
6851
6852 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6853 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6854 return 0;
6855 }
6856
6857 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6858 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6859
6860 hr_dev = handle->priv;
6861 if (!hr_dev)
6862 return 0;
6863
6864 hr_dev->active = false;
6865 hr_dev->dis_db = true;
6866 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6867
6868 return 0;
6869 }
6870
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)6871 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6872 {
6873 struct device *dev = &handle->pdev->dev;
6874 int ret;
6875
6876 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6877 &handle->rinfo.state)) {
6878 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6879 return 0;
6880 }
6881
6882 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6883
6884 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6885 ret = __hns_roce_hw_v2_init_instance(handle);
6886 if (ret) {
6887 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6888 * callback function, RoCE Engine reinitialize. If RoCE reinit
6889 * failed, we should inform NIC driver.
6890 */
6891 handle->priv = NULL;
6892 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6893 } else {
6894 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6895 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6896 }
6897
6898 return ret;
6899 }
6900
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)6901 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6902 {
6903 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6904 return 0;
6905
6906 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6907 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6908 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6909 __hns_roce_hw_v2_uninit_instance(handle, false);
6910
6911 return 0;
6912 }
6913
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)6914 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6915 enum hnae3_reset_notify_type type)
6916 {
6917 int ret = 0;
6918
6919 switch (type) {
6920 case HNAE3_DOWN_CLIENT:
6921 ret = hns_roce_hw_v2_reset_notify_down(handle);
6922 break;
6923 case HNAE3_INIT_CLIENT:
6924 ret = hns_roce_hw_v2_reset_notify_init(handle);
6925 break;
6926 case HNAE3_UNINIT_CLIENT:
6927 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6928 break;
6929 default:
6930 break;
6931 }
6932
6933 return ret;
6934 }
6935
6936 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6937 .init_instance = hns_roce_hw_v2_init_instance,
6938 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6939 .reset_notify = hns_roce_hw_v2_reset_notify,
6940 };
6941
6942 static struct hnae3_client hns_roce_hw_v2_client = {
6943 .name = "hns_roce_hw_v2",
6944 .type = HNAE3_CLIENT_ROCE,
6945 .ops = &hns_roce_hw_v2_ops,
6946 };
6947
hns_roce_hw_v2_init(void)6948 static int __init hns_roce_hw_v2_init(void)
6949 {
6950 return hnae3_register_client(&hns_roce_hw_v2_client);
6951 }
6952
hns_roce_hw_v2_exit(void)6953 static void __exit hns_roce_hw_v2_exit(void)
6954 {
6955 hnae3_unregister_client(&hns_roce_hw_v2_client);
6956 }
6957
6958 module_init(hns_roce_hw_v2_init);
6959 module_exit(hns_roce_hw_v2_exit);
6960
6961 MODULE_LICENSE("Dual BSD/GPL");
6962 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6963 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6964 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6965 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
6966