1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35
36 #include "i915_drv.h"
37 #include "i915_irq.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crt.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
43 #include "intel_ddi_buf_trans.h"
44 #include "intel_de.h"
45 #include "intel_display_types.h"
46 #include "intel_fdi.h"
47 #include "intel_fdi_regs.h"
48 #include "intel_fifo_underrun.h"
49 #include "intel_gmbus.h"
50 #include "intel_hotplug.h"
51 #include "intel_hotplug_irq.h"
52 #include "intel_load_detect.h"
53 #include "intel_pch_display.h"
54 #include "intel_pch_refclk.h"
55
56 /* Here's the desired hotplug mode */
57 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
58 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
59 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
60 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
61 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
62 ADPA_CRT_HOTPLUG_ENABLE)
63
64 struct intel_crt {
65 struct intel_encoder base;
66 /* DPMS state is stored in the connector, which we need in the
67 * encoder's enable/disable callbacks */
68 struct intel_connector *connector;
69 bool force_hotplug_required;
70 i915_reg_t adpa_reg;
71 };
72
intel_encoder_to_crt(struct intel_encoder * encoder)73 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
74 {
75 return container_of(encoder, struct intel_crt, base);
76 }
77
intel_attached_crt(struct intel_connector * connector)78 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
79 {
80 return intel_encoder_to_crt(intel_attached_encoder(connector));
81 }
82
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)83 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
84 i915_reg_t adpa_reg, enum pipe *pipe)
85 {
86 u32 val;
87
88 val = intel_de_read(dev_priv, adpa_reg);
89
90 /* asserts want to know the pipe even if the port is disabled */
91 if (HAS_PCH_CPT(dev_priv))
92 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
93 else
94 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
95
96 return val & ADPA_DAC_ENABLE;
97 }
98
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)99 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
100 enum pipe *pipe)
101 {
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
103 struct intel_crt *crt = intel_encoder_to_crt(encoder);
104 intel_wakeref_t wakeref;
105 bool ret;
106
107 wakeref = intel_display_power_get_if_enabled(dev_priv,
108 encoder->power_domain);
109 if (!wakeref)
110 return false;
111
112 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
113
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
115
116 return ret;
117 }
118
intel_crt_get_flags(struct intel_encoder * encoder)119 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
120 {
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
122 struct intel_crt *crt = intel_encoder_to_crt(encoder);
123 u32 tmp, flags = 0;
124
125 tmp = intel_de_read(dev_priv, crt->adpa_reg);
126
127 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
128 flags |= DRM_MODE_FLAG_PHSYNC;
129 else
130 flags |= DRM_MODE_FLAG_NHSYNC;
131
132 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
133 flags |= DRM_MODE_FLAG_PVSYNC;
134 else
135 flags |= DRM_MODE_FLAG_NVSYNC;
136
137 return flags;
138 }
139
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)140 static void intel_crt_get_config(struct intel_encoder *encoder,
141 struct intel_crtc_state *pipe_config)
142 {
143 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
144
145 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
146
147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
148 }
149
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)150 static void hsw_crt_get_config(struct intel_encoder *encoder,
151 struct intel_crtc_state *pipe_config)
152 {
153 lpt_pch_get_config(pipe_config);
154
155 hsw_ddi_get_config(encoder, pipe_config);
156
157 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
158 DRM_MODE_FLAG_NHSYNC |
159 DRM_MODE_FLAG_PVSYNC |
160 DRM_MODE_FLAG_NVSYNC);
161 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
162 }
163
164 /* Note: The caller is required to filter out dpms modes not supported by the
165 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)166 static void intel_crt_set_dpms(struct intel_encoder *encoder,
167 const struct intel_crtc_state *crtc_state,
168 int mode)
169 {
170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
171 struct intel_crt *crt = intel_encoder_to_crt(encoder);
172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
173 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
174 u32 adpa;
175
176 if (DISPLAY_VER(dev_priv) >= 5)
177 adpa = ADPA_HOTPLUG_BITS;
178 else
179 adpa = 0;
180
181 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
182 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
183 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
184 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
185
186 /* For CPT allow 3 pipe config, for others just use A or B */
187 if (HAS_PCH_LPT(dev_priv))
188 ; /* Those bits don't exist here */
189 else if (HAS_PCH_CPT(dev_priv))
190 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
191 else
192 adpa |= ADPA_PIPE_SEL(crtc->pipe);
193
194 if (!HAS_PCH_SPLIT(dev_priv))
195 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
196
197 switch (mode) {
198 case DRM_MODE_DPMS_ON:
199 adpa |= ADPA_DAC_ENABLE;
200 break;
201 case DRM_MODE_DPMS_STANDBY:
202 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
203 break;
204 case DRM_MODE_DPMS_SUSPEND:
205 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
206 break;
207 case DRM_MODE_DPMS_OFF:
208 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
209 break;
210 }
211
212 intel_de_write(dev_priv, crt->adpa_reg, adpa);
213 }
214
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)215 static void intel_disable_crt(struct intel_atomic_state *state,
216 struct intel_encoder *encoder,
217 const struct intel_crtc_state *old_crtc_state,
218 const struct drm_connector_state *old_conn_state)
219 {
220 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
221 }
222
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)223 static void pch_disable_crt(struct intel_atomic_state *state,
224 struct intel_encoder *encoder,
225 const struct intel_crtc_state *old_crtc_state,
226 const struct drm_connector_state *old_conn_state)
227 {
228 }
229
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)230 static void pch_post_disable_crt(struct intel_atomic_state *state,
231 struct intel_encoder *encoder,
232 const struct intel_crtc_state *old_crtc_state,
233 const struct drm_connector_state *old_conn_state)
234 {
235 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
236 }
237
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)238 static void hsw_disable_crt(struct intel_atomic_state *state,
239 struct intel_encoder *encoder,
240 const struct intel_crtc_state *old_crtc_state,
241 const struct drm_connector_state *old_conn_state)
242 {
243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
244
245 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
246
247 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
248 }
249
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)250 static void hsw_post_disable_crt(struct intel_atomic_state *state,
251 struct intel_encoder *encoder,
252 const struct intel_crtc_state *old_crtc_state,
253 const struct drm_connector_state *old_conn_state)
254 {
255 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
257
258 intel_crtc_vblank_off(old_crtc_state);
259
260 intel_disable_transcoder(old_crtc_state);
261
262 intel_ddi_disable_transcoder_func(old_crtc_state);
263
264 ilk_pfit_disable(old_crtc_state);
265
266 intel_ddi_disable_transcoder_clock(old_crtc_state);
267
268 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
269
270 lpt_pch_disable(state, crtc);
271
272 hsw_fdi_disable(encoder);
273
274 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
275
276 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
277 }
278
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)279 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
280 struct intel_encoder *encoder,
281 const struct intel_crtc_state *crtc_state,
282 const struct drm_connector_state *conn_state)
283 {
284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
285
286 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
287
288 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
289 }
290
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)291 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
292 struct intel_encoder *encoder,
293 const struct intel_crtc_state *crtc_state,
294 const struct drm_connector_state *conn_state)
295 {
296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
298 enum pipe pipe = crtc->pipe;
299
300 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
301
302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
303
304 hsw_fdi_link_train(encoder, crtc_state);
305
306 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
307 }
308
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)309 static void hsw_enable_crt(struct intel_atomic_state *state,
310 struct intel_encoder *encoder,
311 const struct intel_crtc_state *crtc_state,
312 const struct drm_connector_state *conn_state)
313 {
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
316 enum pipe pipe = crtc->pipe;
317
318 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
319
320 intel_ddi_enable_transcoder_func(encoder, crtc_state);
321
322 intel_enable_transcoder(crtc_state);
323
324 lpt_pch_enable(state, crtc);
325
326 intel_crtc_vblank_on(crtc_state);
327
328 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
329
330 intel_crtc_wait_for_next_vblank(crtc);
331 intel_crtc_wait_for_next_vblank(crtc);
332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
333 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
334 }
335
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)336 static void intel_enable_crt(struct intel_atomic_state *state,
337 struct intel_encoder *encoder,
338 const struct intel_crtc_state *crtc_state,
339 const struct drm_connector_state *conn_state)
340 {
341 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
342 }
343
344 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)345 intel_crt_mode_valid(struct drm_connector *connector,
346 struct drm_display_mode *mode)
347 {
348 struct drm_device *dev = connector->dev;
349 struct drm_i915_private *dev_priv = to_i915(dev);
350 int max_dotclk = dev_priv->max_dotclk_freq;
351 enum drm_mode_status status;
352 int max_clock;
353
354 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
355 if (status != MODE_OK)
356 return status;
357
358 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
359 return MODE_NO_DBLESCAN;
360
361 if (mode->clock < 25000)
362 return MODE_CLOCK_LOW;
363
364 if (HAS_PCH_LPT(dev_priv))
365 max_clock = 180000;
366 else if (IS_VALLEYVIEW(dev_priv))
367 /*
368 * 270 MHz due to current DPLL limits,
369 * DAC limit supposedly 355 MHz.
370 */
371 max_clock = 270000;
372 else if (IS_DISPLAY_VER(dev_priv, 3, 4))
373 max_clock = 400000;
374 else
375 max_clock = 350000;
376 if (mode->clock > max_clock)
377 return MODE_CLOCK_HIGH;
378
379 if (mode->clock > max_dotclk)
380 return MODE_CLOCK_HIGH;
381
382 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
383 if (HAS_PCH_LPT(dev_priv) &&
384 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
385 return MODE_CLOCK_HIGH;
386
387 /* HSW/BDW FDI limited to 4k */
388 if (mode->hdisplay > 4096)
389 return MODE_H_ILLEGAL;
390
391 return MODE_OK;
392 }
393
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)394 static int intel_crt_compute_config(struct intel_encoder *encoder,
395 struct intel_crtc_state *pipe_config,
396 struct drm_connector_state *conn_state)
397 {
398 struct drm_display_mode *adjusted_mode =
399 &pipe_config->hw.adjusted_mode;
400
401 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
402 return -EINVAL;
403
404 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
405 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
406
407 return 0;
408 }
409
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)410 static int pch_crt_compute_config(struct intel_encoder *encoder,
411 struct intel_crtc_state *pipe_config,
412 struct drm_connector_state *conn_state)
413 {
414 struct drm_display_mode *adjusted_mode =
415 &pipe_config->hw.adjusted_mode;
416
417 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
418 return -EINVAL;
419
420 pipe_config->has_pch_encoder = true;
421 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
422
423 return 0;
424 }
425
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)426 static int hsw_crt_compute_config(struct intel_encoder *encoder,
427 struct intel_crtc_state *pipe_config,
428 struct drm_connector_state *conn_state)
429 {
430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
431 struct drm_display_mode *adjusted_mode =
432 &pipe_config->hw.adjusted_mode;
433
434 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
435 return -EINVAL;
436
437 /* HSW/BDW FDI limited to 4k */
438 if (adjusted_mode->crtc_hdisplay > 4096 ||
439 adjusted_mode->crtc_hblank_start > 4096)
440 return -EINVAL;
441
442 pipe_config->has_pch_encoder = true;
443 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
444
445 /* LPT FDI RX only supports 8bpc. */
446 if (HAS_PCH_LPT(dev_priv)) {
447 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
448 drm_dbg_kms(&dev_priv->drm,
449 "LPT only supports 24bpp\n");
450 return -EINVAL;
451 }
452
453 pipe_config->pipe_bpp = 24;
454 }
455
456 /* FDI must always be 2.7 GHz */
457 pipe_config->port_clock = 135000 * 2;
458
459 pipe_config->enhanced_framing = true;
460
461 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
462
463 return 0;
464 }
465
ilk_crt_detect_hotplug(struct drm_connector * connector)466 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
467 {
468 struct drm_device *dev = connector->dev;
469 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
470 struct drm_i915_private *dev_priv = to_i915(dev);
471 u32 adpa;
472 bool ret;
473
474 /* The first time through, trigger an explicit detection cycle */
475 if (crt->force_hotplug_required) {
476 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
477 u32 save_adpa;
478
479 crt->force_hotplug_required = false;
480
481 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
482 drm_dbg_kms(&dev_priv->drm,
483 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
484
485 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
486 if (turn_off_dac)
487 adpa &= ~ADPA_DAC_ENABLE;
488
489 intel_de_write(dev_priv, crt->adpa_reg, adpa);
490
491 if (intel_de_wait_for_clear(dev_priv,
492 crt->adpa_reg,
493 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
494 1000))
495 drm_dbg_kms(&dev_priv->drm,
496 "timed out waiting for FORCE_TRIGGER");
497
498 if (turn_off_dac) {
499 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
500 intel_de_posting_read(dev_priv, crt->adpa_reg);
501 }
502 }
503
504 /* Check the status to see if both blue and green are on now */
505 adpa = intel_de_read(dev_priv, crt->adpa_reg);
506 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
507 ret = true;
508 else
509 ret = false;
510 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
511 adpa, ret);
512
513 return ret;
514 }
515
valleyview_crt_detect_hotplug(struct drm_connector * connector)516 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
517 {
518 struct drm_device *dev = connector->dev;
519 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
520 struct drm_i915_private *dev_priv = to_i915(dev);
521 bool reenable_hpd;
522 u32 adpa;
523 bool ret;
524 u32 save_adpa;
525
526 /*
527 * Doing a force trigger causes a hpd interrupt to get sent, which can
528 * get us stuck in a loop if we're polling:
529 * - We enable power wells and reset the ADPA
530 * - output_poll_exec does force probe on VGA, triggering a hpd
531 * - HPD handler waits for poll to unlock dev->mode_config.mutex
532 * - output_poll_exec shuts off the ADPA, unlocks
533 * dev->mode_config.mutex
534 * - HPD handler runs, resets ADPA and brings us back to the start
535 *
536 * Just disable HPD interrupts here to prevent this
537 */
538 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
539
540 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
541 drm_dbg_kms(&dev_priv->drm,
542 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
543
544 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
545
546 intel_de_write(dev_priv, crt->adpa_reg, adpa);
547
548 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
549 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
550 drm_dbg_kms(&dev_priv->drm,
551 "timed out waiting for FORCE_TRIGGER");
552 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
553 }
554
555 /* Check the status to see if both blue and green are on now */
556 adpa = intel_de_read(dev_priv, crt->adpa_reg);
557 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
558 ret = true;
559 else
560 ret = false;
561
562 drm_dbg_kms(&dev_priv->drm,
563 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
564
565 if (reenable_hpd)
566 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
567
568 return ret;
569 }
570
intel_crt_detect_hotplug(struct drm_connector * connector)571 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
572 {
573 struct drm_device *dev = connector->dev;
574 struct drm_i915_private *dev_priv = to_i915(dev);
575 u32 stat;
576 bool ret = false;
577 int i, tries = 0;
578
579 if (HAS_PCH_SPLIT(dev_priv))
580 return ilk_crt_detect_hotplug(connector);
581
582 if (IS_VALLEYVIEW(dev_priv))
583 return valleyview_crt_detect_hotplug(connector);
584
585 /*
586 * On 4 series desktop, CRT detect sequence need to be done twice
587 * to get a reliable result.
588 */
589
590 if (IS_G45(dev_priv))
591 tries = 2;
592 else
593 tries = 1;
594
595 for (i = 0; i < tries ; i++) {
596 /* turn on the FORCE_DETECT */
597 i915_hotplug_interrupt_update(dev_priv,
598 CRT_HOTPLUG_FORCE_DETECT,
599 CRT_HOTPLUG_FORCE_DETECT);
600 /* wait for FORCE_DETECT to go off */
601 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
602 CRT_HOTPLUG_FORCE_DETECT, 1000))
603 drm_dbg_kms(&dev_priv->drm,
604 "timed out waiting for FORCE_DETECT to go off");
605 }
606
607 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
608 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
609 ret = true;
610
611 /* clear the interrupt we just generated, if any */
612 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
613
614 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
615
616 return ret;
617 }
618
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)619 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
620 struct i2c_adapter *i2c)
621 {
622 const struct drm_edid *drm_edid;
623
624 drm_edid = drm_edid_read_ddc(connector, i2c);
625
626 if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
627 drm_dbg_kms(connector->dev,
628 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
629 intel_gmbus_force_bit(i2c, true);
630 drm_edid = drm_edid_read_ddc(connector, i2c);
631 intel_gmbus_force_bit(i2c, false);
632 }
633
634 return drm_edid;
635 }
636
637 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)638 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
639 struct i2c_adapter *adapter)
640 {
641 const struct drm_edid *drm_edid;
642 int ret;
643
644 drm_edid = intel_crt_get_edid(connector, adapter);
645 if (!drm_edid)
646 return 0;
647
648 ret = intel_connector_update_modes(connector, drm_edid);
649
650 drm_edid_free(drm_edid);
651
652 return ret;
653 }
654
intel_crt_detect_ddc(struct drm_connector * connector)655 static bool intel_crt_detect_ddc(struct drm_connector *connector)
656 {
657 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
658 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
659 const struct drm_edid *drm_edid;
660 struct i2c_adapter *i2c;
661 bool ret = false;
662
663 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
664 drm_edid = intel_crt_get_edid(connector, i2c);
665
666 if (drm_edid) {
667 const struct edid *edid = drm_edid_raw(drm_edid);
668 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
669
670 /*
671 * This may be a DVI-I connector with a shared DDC
672 * link between analog and digital outputs, so we
673 * have to check the EDID input spec of the attached device.
674 */
675 if (!is_digital) {
676 drm_dbg_kms(&dev_priv->drm,
677 "CRT detected via DDC:0x50 [EDID]\n");
678 ret = true;
679 } else {
680 drm_dbg_kms(&dev_priv->drm,
681 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
682 }
683 } else {
684 drm_dbg_kms(&dev_priv->drm,
685 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
686 }
687
688 drm_edid_free(drm_edid);
689
690 return ret;
691 }
692
693 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,enum pipe pipe)694 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
695 {
696 struct drm_device *dev = crt->base.base.dev;
697 struct drm_i915_private *dev_priv = to_i915(dev);
698 enum transcoder cpu_transcoder = (enum transcoder)pipe;
699 u32 save_bclrpat;
700 u32 save_vtotal;
701 u32 vtotal, vactive;
702 u32 vsample;
703 u32 vblank, vblank_start, vblank_end;
704 u32 dsl;
705 u8 st00;
706 enum drm_connector_status status;
707
708 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
709
710 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
711 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
712 vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
713
714 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
715 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
716
717 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
718 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
719
720 /* Set the border color to purple. */
721 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
722
723 if (DISPLAY_VER(dev_priv) != 2) {
724 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
725
726 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
727 transconf | TRANSCONF_FORCE_BORDER);
728 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
729 /* Wait for next Vblank to substitue
730 * border color for Color info */
731 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
732 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
733 status = ((st00 & (1 << 4)) != 0) ?
734 connector_status_connected :
735 connector_status_disconnected;
736
737 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
738 } else {
739 bool restore_vblank = false;
740 int count, detect;
741
742 /*
743 * If there isn't any border, add some.
744 * Yes, this will flicker
745 */
746 if (vblank_start <= vactive && vblank_end >= vtotal) {
747 u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
748 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
749
750 vblank_start = vsync_start;
751 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
752 VBLANK_START(vblank_start - 1) |
753 VBLANK_END(vblank_end - 1));
754 restore_vblank = true;
755 }
756 /* sample in the vertical border, selecting the larger one */
757 if (vblank_start - vactive >= vtotal - vblank_end)
758 vsample = (vblank_start + vactive) >> 1;
759 else
760 vsample = (vtotal + vblank_end) >> 1;
761
762 /*
763 * Wait for the border to be displayed
764 */
765 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
766 ;
767 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
768 ;
769 /*
770 * Watch ST00 for an entire scanline
771 */
772 detect = 0;
773 count = 0;
774 do {
775 count++;
776 /* Read the ST00 VGA status register */
777 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
778 if (st00 & (1 << 4))
779 detect++;
780 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
781
782 /* restore vblank if necessary */
783 if (restore_vblank)
784 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
785 /*
786 * If more than 3/4 of the scanline detected a monitor,
787 * then it is assumed to be present. This works even on i830,
788 * where there isn't any way to force the border color across
789 * the screen
790 */
791 status = detect * 4 > count * 3 ?
792 connector_status_connected :
793 connector_status_disconnected;
794 }
795
796 /* Restore previous settings */
797 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
798
799 return status;
800 }
801
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)802 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
803 {
804 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
805 return 1;
806 }
807
808 static const struct dmi_system_id intel_spurious_crt_detect[] = {
809 {
810 .callback = intel_spurious_crt_detect_dmi_callback,
811 .ident = "ACER ZGB",
812 .matches = {
813 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
814 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
815 },
816 },
817 {
818 .callback = intel_spurious_crt_detect_dmi_callback,
819 .ident = "Intel DZ77BH-55K",
820 .matches = {
821 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
822 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
823 },
824 },
825 { }
826 };
827
828 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)829 intel_crt_detect(struct drm_connector *connector,
830 struct drm_modeset_acquire_ctx *ctx,
831 bool force)
832 {
833 struct drm_i915_private *dev_priv = to_i915(connector->dev);
834 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
835 struct intel_encoder *intel_encoder = &crt->base;
836 struct drm_atomic_state *state;
837 intel_wakeref_t wakeref;
838 int status;
839
840 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
841 connector->base.id, connector->name,
842 force);
843
844 if (!INTEL_DISPLAY_ENABLED(dev_priv))
845 return connector_status_disconnected;
846
847 if (dev_priv->params.load_detect_test) {
848 wakeref = intel_display_power_get(dev_priv,
849 intel_encoder->power_domain);
850 goto load_detect;
851 }
852
853 /* Skip machines without VGA that falsely report hotplug events */
854 if (dmi_check_system(intel_spurious_crt_detect))
855 return connector_status_disconnected;
856
857 wakeref = intel_display_power_get(dev_priv,
858 intel_encoder->power_domain);
859
860 if (I915_HAS_HOTPLUG(dev_priv)) {
861 /* We can not rely on the HPD pin always being correctly wired
862 * up, for example many KVM do not pass it through, and so
863 * only trust an assertion that the monitor is connected.
864 */
865 if (intel_crt_detect_hotplug(connector)) {
866 drm_dbg_kms(&dev_priv->drm,
867 "CRT detected via hotplug\n");
868 status = connector_status_connected;
869 goto out;
870 } else
871 drm_dbg_kms(&dev_priv->drm,
872 "CRT not detected via hotplug\n");
873 }
874
875 if (intel_crt_detect_ddc(connector)) {
876 status = connector_status_connected;
877 goto out;
878 }
879
880 /* Load detection is broken on HPD capable machines. Whoever wants a
881 * broken monitor (without edid) to work behind a broken kvm (that fails
882 * to have the right resistors for HP detection) needs to fix this up.
883 * For now just bail out. */
884 if (I915_HAS_HOTPLUG(dev_priv)) {
885 status = connector_status_disconnected;
886 goto out;
887 }
888
889 load_detect:
890 if (!force) {
891 status = connector->status;
892 goto out;
893 }
894
895 /* for pre-945g platforms use load detect */
896 state = intel_load_detect_get_pipe(connector, ctx);
897 if (IS_ERR(state)) {
898 status = PTR_ERR(state);
899 } else if (!state) {
900 status = connector_status_unknown;
901 } else {
902 if (intel_crt_detect_ddc(connector))
903 status = connector_status_connected;
904 else if (DISPLAY_VER(dev_priv) < 4)
905 status = intel_crt_load_detect(crt,
906 to_intel_crtc(connector->state->crtc)->pipe);
907 else if (dev_priv->params.load_detect_test)
908 status = connector_status_disconnected;
909 else
910 status = connector_status_unknown;
911 intel_load_detect_release_pipe(connector, state, ctx);
912 }
913
914 out:
915 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
916
917 /*
918 * Make sure the refs for power wells enabled during detect are
919 * dropped to avoid a new detect cycle triggered by HPD polling.
920 */
921 intel_display_power_flush_work(dev_priv);
922
923 return status;
924 }
925
intel_crt_get_modes(struct drm_connector * connector)926 static int intel_crt_get_modes(struct drm_connector *connector)
927 {
928 struct drm_device *dev = connector->dev;
929 struct drm_i915_private *dev_priv = to_i915(dev);
930 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
931 struct intel_encoder *intel_encoder = &crt->base;
932 intel_wakeref_t wakeref;
933 struct i2c_adapter *i2c;
934 int ret;
935
936 wakeref = intel_display_power_get(dev_priv,
937 intel_encoder->power_domain);
938
939 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
940 ret = intel_crt_ddc_get_modes(connector, i2c);
941 if (ret || !IS_G4X(dev_priv))
942 goto out;
943
944 /* Try to probe digital port for output in DVI-I -> VGA mode. */
945 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
946 ret = intel_crt_ddc_get_modes(connector, i2c);
947
948 out:
949 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
950
951 return ret;
952 }
953
intel_crt_reset(struct drm_encoder * encoder)954 void intel_crt_reset(struct drm_encoder *encoder)
955 {
956 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
957 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
958
959 if (DISPLAY_VER(dev_priv) >= 5) {
960 u32 adpa;
961
962 adpa = intel_de_read(dev_priv, crt->adpa_reg);
963 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
964 adpa |= ADPA_HOTPLUG_BITS;
965 intel_de_write(dev_priv, crt->adpa_reg, adpa);
966 intel_de_posting_read(dev_priv, crt->adpa_reg);
967
968 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
969 crt->force_hotplug_required = true;
970 }
971
972 }
973
974 /*
975 * Routines for controlling stuff on the analog port
976 */
977
978 static const struct drm_connector_funcs intel_crt_connector_funcs = {
979 .fill_modes = drm_helper_probe_single_connector_modes,
980 .late_register = intel_connector_register,
981 .early_unregister = intel_connector_unregister,
982 .destroy = intel_connector_destroy,
983 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
984 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
985 };
986
987 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
988 .detect_ctx = intel_crt_detect,
989 .mode_valid = intel_crt_mode_valid,
990 .get_modes = intel_crt_get_modes,
991 };
992
993 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
994 .reset = intel_crt_reset,
995 .destroy = intel_encoder_destroy,
996 };
997
intel_crt_init(struct drm_i915_private * dev_priv)998 void intel_crt_init(struct drm_i915_private *dev_priv)
999 {
1000 struct drm_connector *connector;
1001 struct intel_crt *crt;
1002 struct intel_connector *intel_connector;
1003 i915_reg_t adpa_reg;
1004 u32 adpa;
1005
1006 if (HAS_PCH_SPLIT(dev_priv))
1007 adpa_reg = PCH_ADPA;
1008 else if (IS_VALLEYVIEW(dev_priv))
1009 adpa_reg = VLV_ADPA;
1010 else
1011 adpa_reg = ADPA;
1012
1013 adpa = intel_de_read(dev_priv, adpa_reg);
1014 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1015 /*
1016 * On some machines (some IVB at least) CRT can be
1017 * fused off, but there's no known fuse bit to
1018 * indicate that. On these machine the ADPA register
1019 * works normally, except the DAC enable bit won't
1020 * take. So the only way to tell is attempt to enable
1021 * it and see what happens.
1022 */
1023 intel_de_write(dev_priv, adpa_reg,
1024 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1025 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1026 return;
1027 intel_de_write(dev_priv, adpa_reg, adpa);
1028 }
1029
1030 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1031 if (!crt)
1032 return;
1033
1034 intel_connector = intel_connector_alloc();
1035 if (!intel_connector) {
1036 kfree(crt);
1037 return;
1038 }
1039
1040 connector = &intel_connector->base;
1041 crt->connector = intel_connector;
1042 drm_connector_init(&dev_priv->drm, &intel_connector->base,
1043 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1044
1045 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1046 DRM_MODE_ENCODER_DAC, "CRT");
1047
1048 intel_connector_attach_encoder(intel_connector, &crt->base);
1049
1050 crt->base.type = INTEL_OUTPUT_ANALOG;
1051 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1052 if (IS_I830(dev_priv))
1053 crt->base.pipe_mask = BIT(PIPE_A);
1054 else
1055 crt->base.pipe_mask = ~0;
1056
1057 if (DISPLAY_VER(dev_priv) != 2)
1058 connector->interlace_allowed = true;
1059
1060 crt->adpa_reg = adpa_reg;
1061
1062 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1063
1064 if (I915_HAS_HOTPLUG(dev_priv) &&
1065 !dmi_check_system(intel_spurious_crt_detect)) {
1066 crt->base.hpd_pin = HPD_CRT;
1067 crt->base.hotplug = intel_encoder_hotplug;
1068 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1069 } else {
1070 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1071 }
1072
1073 if (HAS_DDI(dev_priv)) {
1074 assert_port_valid(dev_priv, PORT_E);
1075
1076 crt->base.port = PORT_E;
1077 crt->base.get_config = hsw_crt_get_config;
1078 crt->base.get_hw_state = intel_ddi_get_hw_state;
1079 crt->base.compute_config = hsw_crt_compute_config;
1080 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1081 crt->base.pre_enable = hsw_pre_enable_crt;
1082 crt->base.enable = hsw_enable_crt;
1083 crt->base.disable = hsw_disable_crt;
1084 crt->base.post_disable = hsw_post_disable_crt;
1085 crt->base.enable_clock = hsw_ddi_enable_clock;
1086 crt->base.disable_clock = hsw_ddi_disable_clock;
1087 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1088
1089 intel_ddi_buf_trans_init(&crt->base);
1090 } else {
1091 if (HAS_PCH_SPLIT(dev_priv)) {
1092 crt->base.compute_config = pch_crt_compute_config;
1093 crt->base.disable = pch_disable_crt;
1094 crt->base.post_disable = pch_post_disable_crt;
1095 } else {
1096 crt->base.compute_config = intel_crt_compute_config;
1097 crt->base.disable = intel_disable_crt;
1098 }
1099 crt->base.port = PORT_NONE;
1100 crt->base.get_config = intel_crt_get_config;
1101 crt->base.get_hw_state = intel_crt_get_hw_state;
1102 crt->base.enable = intel_enable_crt;
1103 }
1104 intel_connector->get_hw_state = intel_connector_get_hw_state;
1105
1106 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1107
1108 /*
1109 * TODO: find a proper way to discover whether we need to set the the
1110 * polarity and link reversal bits or not, instead of relying on the
1111 * BIOS.
1112 */
1113 if (HAS_PCH_LPT(dev_priv)) {
1114 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1115 FDI_RX_LINK_REVERSAL_OVERRIDE;
1116
1117 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1118 FDI_RX_CTL(PIPE_A)) & fdi_config;
1119 }
1120
1121 intel_crt_reset(&crt->base.base);
1122 }
1123