xref: /openbmc/linux/drivers/hwmon/w83627ehf.c (revision 8fecb75b)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  w83627ehf - Driver for the hardware monitoring functionality of
4  *		the Winbond W83627EHF Super-I/O chip
5  *  Copyright (C) 2005-2012  Jean Delvare <jdelvare@suse.de>
6  *  Copyright (C) 2006  Yuan Mu (Winbond),
7  *			Rudolf Marek <r.marek@assembler.cz>
8  *			David Hubbard <david.c.hubbard@gmail.com>
9  *			Daniel J Blueman <daniel.blueman@gmail.com>
10  *  Copyright (C) 2010  Sheng-Yuan Huang (Nuvoton) (PS00)
11  *
12  *  Shamelessly ripped from the w83627hf driver
13  *  Copyright (C) 2003  Mark Studebaker
14  *
15  *  Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
16  *  in testing and debugging this driver.
17  *
18  *  This driver also supports the W83627EHG, which is the lead-free
19  *  version of the W83627EHF.
20  *
21  *  Supports the following chips:
22  *
23  *  Chip        #vin    #fan    #pwm    #temp  chip IDs       man ID
24  *  w83627ehf   10      5       4       3      0x8850 0x88    0x5ca3
25  *					       0x8860 0xa1
26  *  w83627dhg    9      5       4       3      0xa020 0xc1    0x5ca3
27  *  w83627dhg-p  9      5       4       3      0xb070 0xc1    0x5ca3
28  *  w83627uhg    8      2       2       3      0xa230 0xc1    0x5ca3
29  *  w83667hg     9      5       3       3      0xa510 0xc1    0x5ca3
30  *  w83667hg-b   9      5       3       4      0xb350 0xc1    0x5ca3
31  */
32 
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/slab.h>
38 #include <linux/jiffies.h>
39 #include <linux/platform_device.h>
40 #include <linux/hwmon.h>
41 #include <linux/hwmon-sysfs.h>
42 #include <linux/hwmon-vid.h>
43 #include <linux/err.h>
44 #include <linux/mutex.h>
45 #include <linux/acpi.h>
46 #include <linux/io.h>
47 #include "lm75.h"
48 
49 enum kinds {
50 	w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
51 	w83667hg, w83667hg_b,
52 };
53 
54 /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
55 static const char * const w83627ehf_device_names[] = {
56 	"w83627ehf",
57 	"w83627dhg",
58 	"w83627dhg",
59 	"w83627uhg",
60 	"w83667hg",
61 	"w83667hg",
62 };
63 
64 static unsigned short force_id;
65 module_param(force_id, ushort, 0);
66 MODULE_PARM_DESC(force_id, "Override the detected device ID");
67 
68 #define DRVNAME "w83627ehf"
69 
70 /*
71  * Super-I/O constants and functions
72  */
73 
74 #define W83627EHF_LD_HWM	0x0b
75 #define W83667HG_LD_VID		0x0d
76 
77 #define SIO_REG_LDSEL		0x07	/* Logical device select */
78 #define SIO_REG_DEVID		0x20	/* Device ID (2 bytes) */
79 #define SIO_REG_EN_VRM10	0x2C	/* GPIO3, GPIO4 selection */
80 #define SIO_REG_ENABLE		0x30	/* Logical device enable */
81 #define SIO_REG_ADDR		0x60	/* Logical device address (2 bytes) */
82 #define SIO_REG_VID_CTRL	0xF0	/* VID control */
83 #define SIO_REG_VID_DATA	0xF1	/* VID data */
84 
85 #define SIO_W83627EHF_ID	0x8850
86 #define SIO_W83627EHG_ID	0x8860
87 #define SIO_W83627DHG_ID	0xa020
88 #define SIO_W83627DHG_P_ID	0xb070
89 #define SIO_W83627UHG_ID	0xa230
90 #define SIO_W83667HG_ID		0xa510
91 #define SIO_W83667HG_B_ID	0xb350
92 #define SIO_ID_MASK		0xFFF0
93 
94 static inline void
superio_outb(int ioreg,int reg,int val)95 superio_outb(int ioreg, int reg, int val)
96 {
97 	outb(reg, ioreg);
98 	outb(val, ioreg + 1);
99 }
100 
101 static inline int
superio_inb(int ioreg,int reg)102 superio_inb(int ioreg, int reg)
103 {
104 	outb(reg, ioreg);
105 	return inb(ioreg + 1);
106 }
107 
108 static inline void
superio_select(int ioreg,int ld)109 superio_select(int ioreg, int ld)
110 {
111 	outb(SIO_REG_LDSEL, ioreg);
112 	outb(ld, ioreg + 1);
113 }
114 
115 static inline int
superio_enter(int ioreg)116 superio_enter(int ioreg)
117 {
118 	if (!request_muxed_region(ioreg, 2, DRVNAME))
119 		return -EBUSY;
120 
121 	outb(0x87, ioreg);
122 	outb(0x87, ioreg);
123 
124 	return 0;
125 }
126 
127 static inline void
superio_exit(int ioreg)128 superio_exit(int ioreg)
129 {
130 	outb(0xaa, ioreg);
131 	outb(0x02, ioreg);
132 	outb(0x02, ioreg + 1);
133 	release_region(ioreg, 2);
134 }
135 
136 /*
137  * ISA constants
138  */
139 
140 #define IOREGION_ALIGNMENT	(~7)
141 #define IOREGION_OFFSET		5
142 #define IOREGION_LENGTH		2
143 #define ADDR_REG_OFFSET		0
144 #define DATA_REG_OFFSET		1
145 
146 #define W83627EHF_REG_BANK		0x4E
147 #define W83627EHF_REG_CONFIG		0x40
148 
149 /*
150  * Not currently used:
151  * REG_MAN_ID has the value 0x5ca3 for all supported chips.
152  * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
153  * REG_MAN_ID is at port 0x4f
154  * REG_CHIP_ID is at port 0x58
155  */
156 
157 static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
158 static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
159 
160 /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
161 #define W83627EHF_REG_IN_MAX(nr)	((nr < 7) ? (0x2b + (nr) * 2) : \
162 					 (0x554 + (((nr) - 7) * 2)))
163 #define W83627EHF_REG_IN_MIN(nr)	((nr < 7) ? (0x2c + (nr) * 2) : \
164 					 (0x555 + (((nr) - 7) * 2)))
165 #define W83627EHF_REG_IN(nr)		((nr < 7) ? (0x20 + (nr)) : \
166 					 (0x550 + (nr) - 7))
167 
168 static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
169 static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
170 static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
171 static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
172 
173 /* Fan clock dividers are spread over the following five registers */
174 #define W83627EHF_REG_FANDIV1		0x47
175 #define W83627EHF_REG_FANDIV2		0x4B
176 #define W83627EHF_REG_VBAT		0x5D
177 #define W83627EHF_REG_DIODE		0x59
178 #define W83627EHF_REG_SMI_OVT		0x4C
179 
180 #define W83627EHF_REG_ALARM1		0x459
181 #define W83627EHF_REG_ALARM2		0x45A
182 #define W83627EHF_REG_ALARM3		0x45B
183 
184 #define W83627EHF_REG_CASEOPEN_DET	0x42 /* SMI STATUS #2 */
185 #define W83627EHF_REG_CASEOPEN_CLR	0x46 /* SMI MASK #3 */
186 
187 /* SmartFan registers */
188 #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
189 #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
190 
191 /* DC or PWM output fan configuration */
192 static const u8 W83627EHF_REG_PWM_ENABLE[] = {
193 	0x04,			/* SYS FAN0 output mode and PWM mode */
194 	0x04,			/* CPU FAN0 output mode and PWM mode */
195 	0x12,			/* AUX FAN mode */
196 	0x62,			/* CPU FAN1 mode */
197 };
198 
199 static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
200 static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
201 
202 /* FAN Duty Cycle, be used to control */
203 static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
204 static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
205 static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
206 
207 /* Advanced Fan control, some values are common for all fans */
208 static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
209 static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
210 static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
211 
212 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
213 						= { 0xff, 0x67, 0xff, 0x69 };
214 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
215 						= { 0xff, 0x68, 0xff, 0x6a };
216 
217 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
218 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
219 						= { 0x68, 0x6a, 0x6c };
220 
221 static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
222 
223 static const char *const w83667hg_b_temp_label[] = {
224 	"SYSTIN",
225 	"CPUTIN",
226 	"AUXTIN",
227 	"AMDTSI",
228 	"PECI Agent 1",
229 	"PECI Agent 2",
230 	"PECI Agent 3",
231 	"PECI Agent 4"
232 };
233 
234 #define NUM_REG_TEMP	ARRAY_SIZE(W83627EHF_REG_TEMP)
235 
is_word_sized(u16 reg)236 static int is_word_sized(u16 reg)
237 {
238 	return ((((reg & 0xff00) == 0x100
239 	      || (reg & 0xff00) == 0x200)
240 	     && ((reg & 0x00ff) == 0x50
241 	      || (reg & 0x00ff) == 0x53
242 	      || (reg & 0x00ff) == 0x55))
243 	     || (reg & 0xfff0) == 0x630
244 	     || reg == 0x640 || reg == 0x642
245 	     || ((reg & 0xfff0) == 0x650
246 		 && (reg & 0x000f) >= 0x06)
247 	     || reg == 0x73 || reg == 0x75 || reg == 0x77
248 		);
249 }
250 
251 /*
252  * Conversions
253  */
254 
255 /* 1 is PWM mode, output in ms */
step_time_from_reg(u8 reg,u8 mode)256 static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
257 {
258 	return mode ? 100 * reg : 400 * reg;
259 }
260 
step_time_to_reg(unsigned int msec,u8 mode)261 static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
262 {
263 	return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
264 			 1, 255);
265 }
266 
fan_from_reg8(u16 reg,unsigned int divreg)267 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
268 {
269 	if (reg == 0 || reg == 255)
270 		return 0;
271 	return 1350000U / (reg << divreg);
272 }
273 
274 static inline unsigned int
div_from_reg(u8 reg)275 div_from_reg(u8 reg)
276 {
277 	return 1 << reg;
278 }
279 
280 /*
281  * Some of the voltage inputs have internal scaling, the tables below
282  * contain 8 (the ADC LSB in mV) * scaling factor * 100
283  */
284 static const u16 scale_in_common[10] = {
285 	800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
286 };
287 static const u16 scale_in_w83627uhg[9] = {
288 	800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
289 };
290 
in_from_reg(u8 reg,u8 nr,const u16 * scale_in)291 static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
292 {
293 	return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
294 }
295 
in_to_reg(u32 val,u8 nr,const u16 * scale_in)296 static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
297 {
298 	return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
299 }
300 
301 /*
302  * Data structures and manipulation thereof
303  */
304 
305 struct w83627ehf_data {
306 	int addr;	/* IO base of hw monitor block */
307 	const char *name;
308 
309 	struct mutex lock;
310 
311 	u16 reg_temp[NUM_REG_TEMP];
312 	u16 reg_temp_over[NUM_REG_TEMP];
313 	u16 reg_temp_hyst[NUM_REG_TEMP];
314 	u16 reg_temp_config[NUM_REG_TEMP];
315 	u8 temp_src[NUM_REG_TEMP];
316 	const char * const *temp_label;
317 
318 	const u16 *REG_FAN_MAX_OUTPUT;
319 	const u16 *REG_FAN_STEP_OUTPUT;
320 	const u16 *scale_in;
321 
322 	struct mutex update_lock;
323 	bool valid;		/* true if following fields are valid */
324 	unsigned long last_updated;	/* In jiffies */
325 
326 	/* Register values */
327 	u8 bank;		/* current register bank */
328 	u8 in_num;		/* number of in inputs we have */
329 	u8 in[10];		/* Register value */
330 	u8 in_max[10];		/* Register value */
331 	u8 in_min[10];		/* Register value */
332 	unsigned int rpm[5];
333 	u16 fan_min[5];
334 	u8 fan_div[5];
335 	u8 has_fan;		/* some fan inputs can be disabled */
336 	u8 has_fan_min;		/* some fans don't have min register */
337 	u8 temp_type[3];
338 	s8 temp_offset[3];
339 	s16 temp[9];
340 	s16 temp_max[9];
341 	s16 temp_max_hyst[9];
342 	u32 alarms;
343 	u8 caseopen;
344 
345 	u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
346 	u8 pwm_enable[4]; /* 1->manual
347 			   * 2->thermal cruise mode (also called SmartFan I)
348 			   * 3->fan speed cruise mode
349 			   * 4->variable thermal cruise (also called
350 			   * SmartFan III)
351 			   * 5->enhanced variable thermal cruise (also called
352 			   * SmartFan IV)
353 			   */
354 	u8 pwm_enable_orig[4];	/* original value of pwm_enable */
355 	u8 pwm_num;		/* number of pwm */
356 	u8 pwm[4];
357 	u8 target_temp[4];
358 	u8 tolerance[4];
359 
360 	u8 fan_start_output[4]; /* minimum fan speed when spinning up */
361 	u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
362 	u8 fan_stop_time[4]; /* time at minimum before disabling fan */
363 	u8 fan_max_output[4]; /* maximum fan speed */
364 	u8 fan_step_output[4]; /* rate of change output value */
365 
366 	u8 vid;
367 	u8 vrm;
368 
369 	u16 have_temp;
370 	u16 have_temp_offset;
371 	u8 in6_skip:1;
372 	u8 temp3_val_only:1;
373 	u8 have_vid:1;
374 
375 	/* Remember extra register values over suspend/resume */
376 	u8 vbat;
377 	u8 fandiv1;
378 	u8 fandiv2;
379 };
380 
381 struct w83627ehf_sio_data {
382 	int sioreg;
383 	enum kinds kind;
384 };
385 
386 /*
387  * On older chips, only registers 0x50-0x5f are banked.
388  * On more recent chips, all registers are banked.
389  * Assume that is the case and set the bank number for each access.
390  * Cache the bank number so it only needs to be set if it changes.
391  */
w83627ehf_set_bank(struct w83627ehf_data * data,u16 reg)392 static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
393 {
394 	u8 bank = reg >> 8;
395 	if (data->bank != bank) {
396 		outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
397 		outb_p(bank, data->addr + DATA_REG_OFFSET);
398 		data->bank = bank;
399 	}
400 }
401 
w83627ehf_read_value(struct w83627ehf_data * data,u16 reg)402 static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
403 {
404 	int res, word_sized = is_word_sized(reg);
405 
406 	mutex_lock(&data->lock);
407 
408 	w83627ehf_set_bank(data, reg);
409 	outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
410 	res = inb_p(data->addr + DATA_REG_OFFSET);
411 	if (word_sized) {
412 		outb_p((reg & 0xff) + 1,
413 		       data->addr + ADDR_REG_OFFSET);
414 		res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
415 	}
416 
417 	mutex_unlock(&data->lock);
418 	return res;
419 }
420 
w83627ehf_write_value(struct w83627ehf_data * data,u16 reg,u16 value)421 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
422 				 u16 value)
423 {
424 	int word_sized = is_word_sized(reg);
425 
426 	mutex_lock(&data->lock);
427 
428 	w83627ehf_set_bank(data, reg);
429 	outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
430 	if (word_sized) {
431 		outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
432 		outb_p((reg & 0xff) + 1,
433 		       data->addr + ADDR_REG_OFFSET);
434 	}
435 	outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
436 
437 	mutex_unlock(&data->lock);
438 	return 0;
439 }
440 
441 /* We left-align 8-bit temperature values to make the code simpler */
w83627ehf_read_temp(struct w83627ehf_data * data,u16 reg)442 static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
443 {
444 	u16 res;
445 
446 	res = w83627ehf_read_value(data, reg);
447 	if (!is_word_sized(reg))
448 		res <<= 8;
449 
450 	return res;
451 }
452 
w83627ehf_write_temp(struct w83627ehf_data * data,u16 reg,u16 value)453 static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
454 				       u16 value)
455 {
456 	if (!is_word_sized(reg))
457 		value >>= 8;
458 	return w83627ehf_write_value(data, reg, value);
459 }
460 
461 /* This function assumes that the caller holds data->update_lock */
w83627ehf_write_fan_div(struct w83627ehf_data * data,int nr)462 static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
463 {
464 	u8 reg;
465 
466 	switch (nr) {
467 	case 0:
468 		reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
469 		    | ((data->fan_div[0] & 0x03) << 4);
470 		/* fan5 input control bit is write only, compute the value */
471 		reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
472 		w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
473 		reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
474 		    | ((data->fan_div[0] & 0x04) << 3);
475 		w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
476 		break;
477 	case 1:
478 		reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
479 		    | ((data->fan_div[1] & 0x03) << 6);
480 		/* fan5 input control bit is write only, compute the value */
481 		reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
482 		w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
483 		reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
484 		    | ((data->fan_div[1] & 0x04) << 4);
485 		w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
486 		break;
487 	case 2:
488 		reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
489 		    | ((data->fan_div[2] & 0x03) << 6);
490 		w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
491 		reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
492 		    | ((data->fan_div[2] & 0x04) << 5);
493 		w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
494 		break;
495 	case 3:
496 		reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
497 		    | (data->fan_div[3] & 0x03);
498 		w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
499 		reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
500 		    | ((data->fan_div[3] & 0x04) << 5);
501 		w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
502 		break;
503 	case 4:
504 		reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
505 		    | ((data->fan_div[4] & 0x03) << 2)
506 		    | ((data->fan_div[4] & 0x04) << 5);
507 		w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
508 		break;
509 	}
510 }
511 
w83627ehf_update_fan_div(struct w83627ehf_data * data)512 static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
513 {
514 	int i;
515 
516 	i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
517 	data->fan_div[0] = (i >> 4) & 0x03;
518 	data->fan_div[1] = (i >> 6) & 0x03;
519 	i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
520 	data->fan_div[2] = (i >> 6) & 0x03;
521 	i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
522 	data->fan_div[0] |= (i >> 3) & 0x04;
523 	data->fan_div[1] |= (i >> 4) & 0x04;
524 	data->fan_div[2] |= (i >> 5) & 0x04;
525 	if (data->has_fan & ((1 << 3) | (1 << 4))) {
526 		i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
527 		data->fan_div[3] = i & 0x03;
528 		data->fan_div[4] = ((i >> 2) & 0x03)
529 				 | ((i >> 5) & 0x04);
530 	}
531 	if (data->has_fan & (1 << 3)) {
532 		i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
533 		data->fan_div[3] |= (i >> 5) & 0x04;
534 	}
535 }
536 
w83627ehf_update_pwm(struct w83627ehf_data * data)537 static void w83627ehf_update_pwm(struct w83627ehf_data *data)
538 {
539 	int i;
540 	int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
541 
542 	for (i = 0; i < data->pwm_num; i++) {
543 		if (!(data->has_fan & (1 << i)))
544 			continue;
545 
546 		/* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
547 		if (i != 1) {
548 			pwmcfg = w83627ehf_read_value(data,
549 					W83627EHF_REG_PWM_ENABLE[i]);
550 			tolerance = w83627ehf_read_value(data,
551 					W83627EHF_REG_TOLERANCE[i]);
552 		}
553 		data->pwm_mode[i] =
554 			((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
555 		data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
556 				       & 3) + 1;
557 		data->pwm[i] = w83627ehf_read_value(data, W83627EHF_REG_PWM[i]);
558 
559 		data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
560 	}
561 }
562 
w83627ehf_update_device(struct device * dev)563 static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
564 {
565 	struct w83627ehf_data *data = dev_get_drvdata(dev);
566 	int i;
567 
568 	mutex_lock(&data->update_lock);
569 
570 	if (time_after(jiffies, data->last_updated + HZ + HZ/2)
571 	 || !data->valid) {
572 		/* Fan clock dividers */
573 		w83627ehf_update_fan_div(data);
574 
575 		/* Measured voltages and limits */
576 		for (i = 0; i < data->in_num; i++) {
577 			if ((i == 6) && data->in6_skip)
578 				continue;
579 
580 			data->in[i] = w83627ehf_read_value(data,
581 				      W83627EHF_REG_IN(i));
582 			data->in_min[i] = w83627ehf_read_value(data,
583 					  W83627EHF_REG_IN_MIN(i));
584 			data->in_max[i] = w83627ehf_read_value(data,
585 					  W83627EHF_REG_IN_MAX(i));
586 		}
587 
588 		/* Measured fan speeds and limits */
589 		for (i = 0; i < 5; i++) {
590 			u16 reg;
591 
592 			if (!(data->has_fan & (1 << i)))
593 				continue;
594 
595 			reg = w83627ehf_read_value(data, W83627EHF_REG_FAN[i]);
596 			data->rpm[i] = fan_from_reg8(reg, data->fan_div[i]);
597 
598 			if (data->has_fan_min & (1 << i))
599 				data->fan_min[i] = w83627ehf_read_value(data,
600 					   W83627EHF_REG_FAN_MIN[i]);
601 
602 			/*
603 			 * If we failed to measure the fan speed and clock
604 			 * divider can be increased, let's try that for next
605 			 * time
606 			 */
607 			if (reg >= 0xff && data->fan_div[i] < 0x07) {
608 				dev_dbg(dev,
609 					"Increasing fan%d clock divider from %u to %u\n",
610 					i + 1, div_from_reg(data->fan_div[i]),
611 					div_from_reg(data->fan_div[i] + 1));
612 				data->fan_div[i]++;
613 				w83627ehf_write_fan_div(data, i);
614 				/* Preserve min limit if possible */
615 				if ((data->has_fan_min & (1 << i))
616 				 && data->fan_min[i] >= 2
617 				 && data->fan_min[i] != 255)
618 					w83627ehf_write_value(data,
619 						W83627EHF_REG_FAN_MIN[i],
620 						(data->fan_min[i] /= 2));
621 			}
622 		}
623 
624 		w83627ehf_update_pwm(data);
625 
626 		for (i = 0; i < data->pwm_num; i++) {
627 			if (!(data->has_fan & (1 << i)))
628 				continue;
629 
630 			data->fan_start_output[i] =
631 			  w83627ehf_read_value(data,
632 					     W83627EHF_REG_FAN_START_OUTPUT[i]);
633 			data->fan_stop_output[i] =
634 			  w83627ehf_read_value(data,
635 					     W83627EHF_REG_FAN_STOP_OUTPUT[i]);
636 			data->fan_stop_time[i] =
637 			  w83627ehf_read_value(data,
638 					       W83627EHF_REG_FAN_STOP_TIME[i]);
639 
640 			if (data->REG_FAN_MAX_OUTPUT &&
641 			    data->REG_FAN_MAX_OUTPUT[i] != 0xff)
642 				data->fan_max_output[i] =
643 				  w83627ehf_read_value(data,
644 						data->REG_FAN_MAX_OUTPUT[i]);
645 
646 			if (data->REG_FAN_STEP_OUTPUT &&
647 			    data->REG_FAN_STEP_OUTPUT[i] != 0xff)
648 				data->fan_step_output[i] =
649 				  w83627ehf_read_value(data,
650 						data->REG_FAN_STEP_OUTPUT[i]);
651 
652 			data->target_temp[i] =
653 				w83627ehf_read_value(data,
654 					W83627EHF_REG_TARGET[i]) &
655 					(data->pwm_mode[i] == 1 ? 0x7f : 0xff);
656 		}
657 
658 		/* Measured temperatures and limits */
659 		for (i = 0; i < NUM_REG_TEMP; i++) {
660 			if (!(data->have_temp & (1 << i)))
661 				continue;
662 			data->temp[i] = w83627ehf_read_temp(data,
663 						data->reg_temp[i]);
664 			if (data->reg_temp_over[i])
665 				data->temp_max[i]
666 				  = w83627ehf_read_temp(data,
667 						data->reg_temp_over[i]);
668 			if (data->reg_temp_hyst[i])
669 				data->temp_max_hyst[i]
670 				  = w83627ehf_read_temp(data,
671 						data->reg_temp_hyst[i]);
672 			if (i > 2)
673 				continue;
674 			if (data->have_temp_offset & (1 << i))
675 				data->temp_offset[i]
676 				  = w83627ehf_read_value(data,
677 						W83627EHF_REG_TEMP_OFFSET[i]);
678 		}
679 
680 		data->alarms = w83627ehf_read_value(data,
681 					W83627EHF_REG_ALARM1) |
682 			       (w83627ehf_read_value(data,
683 					W83627EHF_REG_ALARM2) << 8) |
684 			       (w83627ehf_read_value(data,
685 					W83627EHF_REG_ALARM3) << 16);
686 
687 		data->caseopen = w83627ehf_read_value(data,
688 						W83627EHF_REG_CASEOPEN_DET);
689 
690 		data->last_updated = jiffies;
691 		data->valid = true;
692 	}
693 
694 	mutex_unlock(&data->update_lock);
695 	return data;
696 }
697 
698 #define store_in_reg(REG, reg) \
699 static int \
700 store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
701 	       long val) \
702 { \
703 	if (val < 0) \
704 		return -EINVAL; \
705 	mutex_lock(&data->update_lock); \
706 	data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
707 	w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
708 			      data->in_##reg[channel]); \
709 	mutex_unlock(&data->update_lock); \
710 	return 0; \
711 }
712 
store_in_reg(MIN,min)713 store_in_reg(MIN, min)
714 store_in_reg(MAX, max)
715 
716 static int
717 store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
718 	      long val)
719 {
720 	unsigned int reg;
721 	u8 new_div;
722 
723 	if (val < 0)
724 		return -EINVAL;
725 
726 	mutex_lock(&data->update_lock);
727 	if (!val) {
728 		/* No min limit, alarm disabled */
729 		data->fan_min[channel] = 255;
730 		new_div = data->fan_div[channel]; /* No change */
731 		dev_info(dev, "fan%u low limit and alarm disabled\n",
732 			 channel + 1);
733 	} else if ((reg = 1350000U / val) >= 128 * 255) {
734 		/*
735 		 * Speed below this value cannot possibly be represented,
736 		 * even with the highest divider (128)
737 		 */
738 		data->fan_min[channel] = 254;
739 		new_div = 7; /* 128 == (1 << 7) */
740 		dev_warn(dev,
741 			 "fan%u low limit %lu below minimum %u, set to minimum\n",
742 			 channel + 1, val, fan_from_reg8(254, 7));
743 	} else if (!reg) {
744 		/*
745 		 * Speed above this value cannot possibly be represented,
746 		 * even with the lowest divider (1)
747 		 */
748 		data->fan_min[channel] = 1;
749 		new_div = 0; /* 1 == (1 << 0) */
750 		dev_warn(dev,
751 			 "fan%u low limit %lu above maximum %u, set to maximum\n",
752 			 channel + 1, val, fan_from_reg8(1, 0));
753 	} else {
754 		/*
755 		 * Automatically pick the best divider, i.e. the one such
756 		 * that the min limit will correspond to a register value
757 		 * in the 96..192 range
758 		 */
759 		new_div = 0;
760 		while (reg > 192 && new_div < 7) {
761 			reg >>= 1;
762 			new_div++;
763 		}
764 		data->fan_min[channel] = reg;
765 	}
766 
767 	/*
768 	 * Write both the fan clock divider (if it changed) and the new
769 	 * fan min (unconditionally)
770 	 */
771 	if (new_div != data->fan_div[channel]) {
772 		dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
773 			channel + 1, div_from_reg(data->fan_div[channel]),
774 			div_from_reg(new_div));
775 		data->fan_div[channel] = new_div;
776 		w83627ehf_write_fan_div(data, channel);
777 		/* Give the chip time to sample a new speed value */
778 		data->last_updated = jiffies;
779 	}
780 
781 	w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
782 			      data->fan_min[channel]);
783 	mutex_unlock(&data->update_lock);
784 
785 	return 0;
786 }
787 
788 #define store_temp_reg(addr, reg) \
789 static int \
790 store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
791 	    long val) \
792 { \
793 	mutex_lock(&data->update_lock); \
794 	data->reg[channel] = LM75_TEMP_TO_REG(val); \
795 	w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
796 	mutex_unlock(&data->update_lock); \
797 	return 0; \
798 }
799 store_temp_reg(reg_temp_over, temp_max);
800 store_temp_reg(reg_temp_hyst, temp_max_hyst);
801 
802 static int
store_temp_offset(struct device * dev,struct w83627ehf_data * data,int channel,long val)803 store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
804 		  long val)
805 {
806 	val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
807 
808 	mutex_lock(&data->update_lock);
809 	data->temp_offset[channel] = val;
810 	w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
811 	mutex_unlock(&data->update_lock);
812 	return 0;
813 }
814 
815 static int
store_pwm_mode(struct device * dev,struct w83627ehf_data * data,int channel,long val)816 store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
817 	       long val)
818 {
819 	u16 reg;
820 
821 	if (val < 0 || val > 1)
822 		return -EINVAL;
823 
824 	mutex_lock(&data->update_lock);
825 	reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
826 	data->pwm_mode[channel] = val;
827 	reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
828 	if (!val)
829 		reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
830 	w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
831 	mutex_unlock(&data->update_lock);
832 	return 0;
833 }
834 
835 static int
store_pwm(struct device * dev,struct w83627ehf_data * data,int channel,long val)836 store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
837 	  long val)
838 {
839 	val = clamp_val(val, 0, 255);
840 
841 	mutex_lock(&data->update_lock);
842 	data->pwm[channel] = val;
843 	w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
844 	mutex_unlock(&data->update_lock);
845 	return 0;
846 }
847 
848 static int
store_pwm_enable(struct device * dev,struct w83627ehf_data * data,int channel,long val)849 store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
850 		 long val)
851 {
852 	u16 reg;
853 
854 	if (!val || val < 0 ||
855 	    (val > 4 && val != data->pwm_enable_orig[channel]))
856 		return -EINVAL;
857 
858 	mutex_lock(&data->update_lock);
859 	data->pwm_enable[channel] = val;
860 	reg = w83627ehf_read_value(data,
861 				   W83627EHF_REG_PWM_ENABLE[channel]);
862 	reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
863 	reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
864 	w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
865 			      reg);
866 	mutex_unlock(&data->update_lock);
867 	return 0;
868 }
869 
870 #define show_tol_temp(reg) \
871 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
872 				char *buf) \
873 { \
874 	struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
875 	struct sensor_device_attribute *sensor_attr = \
876 		to_sensor_dev_attr(attr); \
877 	int nr = sensor_attr->index; \
878 	return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
879 }
880 
881 show_tol_temp(tolerance)
show_tol_temp(target_temp)882 show_tol_temp(target_temp)
883 
884 static ssize_t
885 store_target_temp(struct device *dev, struct device_attribute *attr,
886 			const char *buf, size_t count)
887 {
888 	struct w83627ehf_data *data = dev_get_drvdata(dev);
889 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
890 	int nr = sensor_attr->index;
891 	long val;
892 	int err;
893 
894 	err = kstrtol(buf, 10, &val);
895 	if (err < 0)
896 		return err;
897 
898 	val = DIV_ROUND_CLOSEST(clamp_val(val, 0, 127000), 1000);
899 
900 	mutex_lock(&data->update_lock);
901 	data->target_temp[nr] = val;
902 	w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
903 	mutex_unlock(&data->update_lock);
904 	return count;
905 }
906 
907 static ssize_t
store_tolerance(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)908 store_tolerance(struct device *dev, struct device_attribute *attr,
909 			const char *buf, size_t count)
910 {
911 	struct w83627ehf_data *data = dev_get_drvdata(dev);
912 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
913 	int nr = sensor_attr->index;
914 	u16 reg;
915 	long val;
916 	int err;
917 
918 	err = kstrtol(buf, 10, &val);
919 	if (err < 0)
920 		return err;
921 
922 	/* Limit the temp to 0C - 15C */
923 	val = DIV_ROUND_CLOSEST(clamp_val(val, 0, 15000), 1000);
924 
925 	mutex_lock(&data->update_lock);
926 	reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
927 	if (nr == 1)
928 		reg = (reg & 0x0f) | (val << 4);
929 	else
930 		reg = (reg & 0xf0) | val;
931 	w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
932 	data->tolerance[nr] = val;
933 	mutex_unlock(&data->update_lock);
934 	return count;
935 }
936 
937 static SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
938 	    store_target_temp, 0);
939 static SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
940 	    store_target_temp, 1);
941 static SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
942 	    store_target_temp, 2);
943 static SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
944 	    store_target_temp, 3);
945 
946 static SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
947 	    store_tolerance, 0);
948 static SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
949 	    store_tolerance, 1);
950 static SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
951 	    store_tolerance, 2);
952 static SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
953 	    store_tolerance, 3);
954 
955 /* Smart Fan registers */
956 
957 #define fan_functions(reg, REG) \
958 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
959 		       char *buf) \
960 { \
961 	struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
962 	struct sensor_device_attribute *sensor_attr = \
963 		to_sensor_dev_attr(attr); \
964 	int nr = sensor_attr->index; \
965 	return sprintf(buf, "%d\n", data->reg[nr]); \
966 } \
967 static ssize_t \
968 store_##reg(struct device *dev, struct device_attribute *attr, \
969 			    const char *buf, size_t count) \
970 { \
971 	struct w83627ehf_data *data = dev_get_drvdata(dev); \
972 	struct sensor_device_attribute *sensor_attr = \
973 		to_sensor_dev_attr(attr); \
974 	int nr = sensor_attr->index; \
975 	unsigned long val; \
976 	int err; \
977 	err = kstrtoul(buf, 10, &val); \
978 	if (err < 0) \
979 		return err; \
980 	val = clamp_val(val, 1, 255); \
981 	mutex_lock(&data->update_lock); \
982 	data->reg[nr] = val; \
983 	w83627ehf_write_value(data, REG[nr], val); \
984 	mutex_unlock(&data->update_lock); \
985 	return count; \
986 }
987 
988 fan_functions(fan_start_output, W83627EHF_REG_FAN_START_OUTPUT)
989 fan_functions(fan_stop_output, W83627EHF_REG_FAN_STOP_OUTPUT)
990 fan_functions(fan_max_output, data->REG_FAN_MAX_OUTPUT)
991 fan_functions(fan_step_output, data->REG_FAN_STEP_OUTPUT)
992 
993 #define fan_time_functions(reg, REG) \
994 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
995 				char *buf) \
996 { \
997 	struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
998 	struct sensor_device_attribute *sensor_attr = \
999 		to_sensor_dev_attr(attr); \
1000 	int nr = sensor_attr->index; \
1001 	return sprintf(buf, "%d\n", \
1002 			step_time_from_reg(data->reg[nr], \
1003 					   data->pwm_mode[nr])); \
1004 } \
1005 \
1006 static ssize_t \
1007 store_##reg(struct device *dev, struct device_attribute *attr, \
1008 			const char *buf, size_t count) \
1009 { \
1010 	struct w83627ehf_data *data = dev_get_drvdata(dev); \
1011 	struct sensor_device_attribute *sensor_attr = \
1012 		to_sensor_dev_attr(attr); \
1013 	int nr = sensor_attr->index; \
1014 	unsigned long val; \
1015 	int err; \
1016 	err = kstrtoul(buf, 10, &val); \
1017 	if (err < 0) \
1018 		return err; \
1019 	val = step_time_to_reg(val, data->pwm_mode[nr]); \
1020 	mutex_lock(&data->update_lock); \
1021 	data->reg[nr] = val; \
1022 	w83627ehf_write_value(data, REG[nr], val); \
1023 	mutex_unlock(&data->update_lock); \
1024 	return count; \
1025 } \
1026 
1027 fan_time_functions(fan_stop_time, W83627EHF_REG_FAN_STOP_TIME)
1028 
1029 static SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
1030 	    store_fan_stop_time, 3);
1031 static SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
1032 	    store_fan_start_output, 3);
1033 static SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
1034 	    store_fan_stop_output, 3);
1035 static SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
1036 	    store_fan_max_output, 3);
1037 static SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
1038 	    store_fan_step_output, 3);
1039 
1040 static SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
1041 	    store_fan_stop_time, 2);
1042 static SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
1043 	    store_fan_start_output, 2);
1044 static SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
1045 		    store_fan_stop_output, 2);
1046 
1047 static SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
1048 	    store_fan_stop_time, 0);
1049 static SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
1050 	    store_fan_stop_time, 1);
1051 static SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
1052 	    store_fan_start_output, 0);
1053 static SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
1054 	    store_fan_start_output, 1);
1055 static SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
1056 	    store_fan_stop_output, 0);
1057 static SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
1058 	    store_fan_stop_output, 1);
1059 
1060 
1061 /*
1062  * pwm1 and pwm3 don't support max and step settings on all chips.
1063  * Need to check support while generating/removing attribute files.
1064  */
1065 static SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
1066 	    store_fan_max_output, 0);
1067 static SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
1068 	    store_fan_step_output, 0);
1069 static SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
1070 	    store_fan_max_output, 1);
1071 static SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
1072 	    store_fan_step_output, 1);
1073 static SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
1074 	    store_fan_max_output, 2);
1075 static SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
1076 	    store_fan_step_output, 2);
1077 
1078 static ssize_t
cpu0_vid_show(struct device * dev,struct device_attribute * attr,char * buf)1079 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
1080 {
1081 	struct w83627ehf_data *data = dev_get_drvdata(dev);
1082 	return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1083 }
1084 static DEVICE_ATTR_RO(cpu0_vid);
1085 
1086 
1087 /* Case open detection */
1088 static int
clear_caseopen(struct device * dev,struct w83627ehf_data * data,int channel,long val)1089 clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
1090 	       long val)
1091 {
1092 	const u16 mask = 0x80;
1093 	u16 reg;
1094 
1095 	if (val != 0 || channel != 0)
1096 		return -EINVAL;
1097 
1098 	mutex_lock(&data->update_lock);
1099 	reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1100 	w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1101 	w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1102 	data->valid = false;	/* Force cache refresh */
1103 	mutex_unlock(&data->update_lock);
1104 
1105 	return 0;
1106 }
1107 
w83627ehf_attrs_visible(struct kobject * kobj,struct attribute * a,int n)1108 static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
1109 				       struct attribute *a, int n)
1110 {
1111 	struct device *dev = kobj_to_dev(kobj);
1112 	struct w83627ehf_data *data = dev_get_drvdata(dev);
1113 	struct device_attribute *devattr;
1114 	struct sensor_device_attribute *sda;
1115 
1116 	devattr = container_of(a, struct device_attribute, attr);
1117 
1118 	/* Not sensor */
1119 	if (devattr->show == cpu0_vid_show && data->have_vid)
1120 		return a->mode;
1121 
1122 	sda = (struct sensor_device_attribute *)devattr;
1123 
1124 	if (sda->index < 2 &&
1125 		(devattr->show == show_fan_stop_time ||
1126 		 devattr->show == show_fan_start_output ||
1127 		 devattr->show == show_fan_stop_output))
1128 		return a->mode;
1129 
1130 	if (sda->index < 3 &&
1131 		(devattr->show == show_fan_max_output ||
1132 		 devattr->show == show_fan_step_output) &&
1133 		data->REG_FAN_STEP_OUTPUT &&
1134 		data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
1135 		return a->mode;
1136 
1137 	/* if fan3 and fan4 are enabled create the files for them */
1138 	if (sda->index == 2 &&
1139 		(data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
1140 		(devattr->show == show_fan_stop_time ||
1141 		 devattr->show == show_fan_start_output ||
1142 		 devattr->show == show_fan_stop_output))
1143 		return a->mode;
1144 
1145 	if (sda->index == 3 &&
1146 		(data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
1147 		(devattr->show == show_fan_stop_time ||
1148 		 devattr->show == show_fan_start_output ||
1149 		 devattr->show == show_fan_stop_output ||
1150 		 devattr->show == show_fan_max_output ||
1151 		 devattr->show == show_fan_step_output))
1152 		return a->mode;
1153 
1154 	if ((devattr->show == show_target_temp ||
1155 	    devattr->show == show_tolerance) &&
1156 	    (data->has_fan & (1 << sda->index)) &&
1157 	    sda->index < data->pwm_num)
1158 		return a->mode;
1159 
1160 	return 0;
1161 }
1162 
1163 /* These groups handle non-standard attributes used in this device */
1164 static struct attribute *w83627ehf_attrs[] = {
1165 
1166 	&sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
1167 	&sensor_dev_attr_pwm1_start_output.dev_attr.attr,
1168 	&sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
1169 	&sensor_dev_attr_pwm1_max_output.dev_attr.attr,
1170 	&sensor_dev_attr_pwm1_step_output.dev_attr.attr,
1171 	&sensor_dev_attr_pwm1_target.dev_attr.attr,
1172 	&sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
1173 
1174 	&sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
1175 	&sensor_dev_attr_pwm2_start_output.dev_attr.attr,
1176 	&sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
1177 	&sensor_dev_attr_pwm2_max_output.dev_attr.attr,
1178 	&sensor_dev_attr_pwm2_step_output.dev_attr.attr,
1179 	&sensor_dev_attr_pwm2_target.dev_attr.attr,
1180 	&sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
1181 
1182 	&sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
1183 	&sensor_dev_attr_pwm3_start_output.dev_attr.attr,
1184 	&sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
1185 	&sensor_dev_attr_pwm3_max_output.dev_attr.attr,
1186 	&sensor_dev_attr_pwm3_step_output.dev_attr.attr,
1187 	&sensor_dev_attr_pwm3_target.dev_attr.attr,
1188 	&sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
1189 
1190 	&sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
1191 	&sensor_dev_attr_pwm4_start_output.dev_attr.attr,
1192 	&sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
1193 	&sensor_dev_attr_pwm4_max_output.dev_attr.attr,
1194 	&sensor_dev_attr_pwm4_step_output.dev_attr.attr,
1195 	&sensor_dev_attr_pwm4_target.dev_attr.attr,
1196 	&sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
1197 
1198 	&dev_attr_cpu0_vid.attr,
1199 	NULL
1200 };
1201 
1202 static const struct attribute_group w83627ehf_group = {
1203 	.attrs = w83627ehf_attrs,
1204 	.is_visible = w83627ehf_attrs_visible,
1205 };
1206 
1207 static const struct attribute_group *w83627ehf_groups[] = {
1208 	&w83627ehf_group,
1209 	NULL
1210 };
1211 
1212 /*
1213  * Driver and device management
1214  */
1215 
1216 /* Get the monitoring functions started */
w83627ehf_init_device(struct w83627ehf_data * data,enum kinds kind)1217 static inline void w83627ehf_init_device(struct w83627ehf_data *data,
1218 						   enum kinds kind)
1219 {
1220 	int i;
1221 	u8 tmp, diode;
1222 
1223 	/* Start monitoring is needed */
1224 	tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
1225 	if (!(tmp & 0x01))
1226 		w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1227 				      tmp | 0x01);
1228 
1229 	/* Enable temperature sensors if needed */
1230 	for (i = 0; i < NUM_REG_TEMP; i++) {
1231 		if (!(data->have_temp & (1 << i)))
1232 			continue;
1233 		if (!data->reg_temp_config[i])
1234 			continue;
1235 		tmp = w83627ehf_read_value(data,
1236 					   data->reg_temp_config[i]);
1237 		if (tmp & 0x01)
1238 			w83627ehf_write_value(data,
1239 					      data->reg_temp_config[i],
1240 					      tmp & 0xfe);
1241 	}
1242 
1243 	/* Enable VBAT monitoring if needed */
1244 	tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1245 	if (!(tmp & 0x01))
1246 		w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
1247 
1248 	/* Get thermal sensor types */
1249 	switch (kind) {
1250 	case w83627ehf:
1251 		diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1252 		break;
1253 	case w83627uhg:
1254 		diode = 0x00;
1255 		break;
1256 	default:
1257 		diode = 0x70;
1258 	}
1259 	for (i = 0; i < 3; i++) {
1260 		const char *label = NULL;
1261 
1262 		if (data->temp_label)
1263 			label = data->temp_label[data->temp_src[i]];
1264 
1265 		/* Digital source overrides analog type */
1266 		if (label && strncmp(label, "PECI", 4) == 0)
1267 			data->temp_type[i] = 6;
1268 		else if (label && strncmp(label, "AMD", 3) == 0)
1269 			data->temp_type[i] = 5;
1270 		else if ((tmp & (0x02 << i)))
1271 			data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
1272 		else
1273 			data->temp_type[i] = 4; /* thermistor */
1274 	}
1275 }
1276 
1277 static void
w83627ehf_set_temp_reg_ehf(struct w83627ehf_data * data,int n_temp)1278 w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1279 {
1280 	int i;
1281 
1282 	for (i = 0; i < n_temp; i++) {
1283 		data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1284 		data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1285 		data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1286 		data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1287 	}
1288 }
1289 
1290 static void
w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data * sio_data,struct w83627ehf_data * data)1291 w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1292 			   struct w83627ehf_data *data)
1293 {
1294 	int fan3pin, fan4pin, fan5pin, regval;
1295 
1296 	/* The W83627UHG is simple, only two fan inputs, no config */
1297 	if (sio_data->kind == w83627uhg) {
1298 		data->has_fan = 0x03; /* fan1 and fan2 */
1299 		data->has_fan_min = 0x03;
1300 		return;
1301 	}
1302 
1303 	/* fan4 and fan5 share some pins with the GPIO and serial flash */
1304 	if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1305 		fan3pin = 1;
1306 		fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1307 		fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1308 	} else {
1309 		fan3pin = 1;
1310 		fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1311 		fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1312 	}
1313 
1314 	data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
1315 	data->has_fan |= (fan3pin << 2);
1316 	data->has_fan_min |= (fan3pin << 2);
1317 
1318 	/*
1319 	 * It looks like fan4 and fan5 pins can be alternatively used
1320 	 * as fan on/off switches, but fan5 control is write only :/
1321 	 * We assume that if the serial interface is disabled, designers
1322 	 * connected fan5 as input unless they are emitting log 1, which
1323 	 * is not the default.
1324 	 */
1325 	regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1326 	if ((regval & (1 << 2)) && fan4pin) {
1327 		data->has_fan |= (1 << 3);
1328 		data->has_fan_min |= (1 << 3);
1329 	}
1330 	if (!(regval & (1 << 1)) && fan5pin) {
1331 		data->has_fan |= (1 << 4);
1332 		data->has_fan_min |= (1 << 4);
1333 	}
1334 }
1335 
1336 static umode_t
w83627ehf_is_visible(const void * drvdata,enum hwmon_sensor_types type,u32 attr,int channel)1337 w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
1338 		     u32 attr, int channel)
1339 {
1340 	const struct w83627ehf_data *data = drvdata;
1341 
1342 	switch (type) {
1343 	case hwmon_temp:
1344 		/* channel 0.., name 1.. */
1345 		if (!(data->have_temp & (1 << channel)))
1346 			return 0;
1347 		if (attr == hwmon_temp_input)
1348 			return 0444;
1349 		if (attr == hwmon_temp_label) {
1350 			if (data->temp_label)
1351 				return 0444;
1352 			return 0;
1353 		}
1354 		if (channel == 2 && data->temp3_val_only)
1355 			return 0;
1356 		if (attr == hwmon_temp_max) {
1357 			if (data->reg_temp_over[channel])
1358 				return 0644;
1359 			else
1360 				return 0;
1361 		}
1362 		if (attr == hwmon_temp_max_hyst) {
1363 			if (data->reg_temp_hyst[channel])
1364 				return 0644;
1365 			else
1366 				return 0;
1367 		}
1368 		if (channel > 2)
1369 			return 0;
1370 		if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
1371 			return 0444;
1372 		if (attr == hwmon_temp_offset) {
1373 			if (data->have_temp_offset & (1 << channel))
1374 				return 0644;
1375 			else
1376 				return 0;
1377 		}
1378 		break;
1379 
1380 	case hwmon_fan:
1381 		/* channel 0.., name 1.. */
1382 		if (!(data->has_fan & (1 << channel)))
1383 			return 0;
1384 		if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
1385 			return 0444;
1386 		if (attr == hwmon_fan_div) {
1387 			return 0444;
1388 		}
1389 		if (attr == hwmon_fan_min) {
1390 			if (data->has_fan_min & (1 << channel))
1391 				return 0644;
1392 			else
1393 				return 0;
1394 		}
1395 		break;
1396 
1397 	case hwmon_in:
1398 		/* channel 0.., name 0.. */
1399 		if (channel >= data->in_num)
1400 			return 0;
1401 		if (channel == 6 && data->in6_skip)
1402 			return 0;
1403 		if (attr == hwmon_in_alarm || attr == hwmon_in_input)
1404 			return 0444;
1405 		if (attr == hwmon_in_min || attr == hwmon_in_max)
1406 			return 0644;
1407 		break;
1408 
1409 	case hwmon_pwm:
1410 		/* channel 0.., name 1.. */
1411 		if (!(data->has_fan & (1 << channel)) ||
1412 		    channel >= data->pwm_num)
1413 			return 0;
1414 		if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
1415 		    attr == hwmon_pwm_input)
1416 			return 0644;
1417 		break;
1418 
1419 	case hwmon_intrusion:
1420 		return 0644;
1421 
1422 	default: /* Shouldn't happen */
1423 		return 0;
1424 	}
1425 
1426 	return 0; /* Shouldn't happen */
1427 }
1428 
1429 static int
w83627ehf_do_read_temp(struct w83627ehf_data * data,u32 attr,int channel,long * val)1430 w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
1431 		       int channel, long *val)
1432 {
1433 	switch (attr) {
1434 	case hwmon_temp_input:
1435 		*val = LM75_TEMP_FROM_REG(data->temp[channel]);
1436 		return 0;
1437 	case hwmon_temp_max:
1438 		*val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
1439 		return 0;
1440 	case hwmon_temp_max_hyst:
1441 		*val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
1442 		return 0;
1443 	case hwmon_temp_offset:
1444 		*val = data->temp_offset[channel] * 1000;
1445 		return 0;
1446 	case hwmon_temp_type:
1447 		*val = (int)data->temp_type[channel];
1448 		return 0;
1449 	case hwmon_temp_alarm:
1450 		if (channel < 3) {
1451 			int bit[] = { 4, 5, 13 };
1452 			*val = (data->alarms >> bit[channel]) & 1;
1453 			return 0;
1454 		}
1455 		break;
1456 
1457 	default:
1458 		break;
1459 	}
1460 
1461 	return -EOPNOTSUPP;
1462 }
1463 
1464 static int
w83627ehf_do_read_in(struct w83627ehf_data * data,u32 attr,int channel,long * val)1465 w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
1466 		     int channel, long *val)
1467 {
1468 	switch (attr) {
1469 	case hwmon_in_input:
1470 		*val = in_from_reg(data->in[channel], channel, data->scale_in);
1471 		return 0;
1472 	case hwmon_in_min:
1473 		*val = in_from_reg(data->in_min[channel], channel,
1474 				   data->scale_in);
1475 		return 0;
1476 	case hwmon_in_max:
1477 		*val = in_from_reg(data->in_max[channel], channel,
1478 				   data->scale_in);
1479 		return 0;
1480 	case hwmon_in_alarm:
1481 		if (channel < 10) {
1482 			int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
1483 			*val = (data->alarms >> bit[channel]) & 1;
1484 			return 0;
1485 		}
1486 		break;
1487 	default:
1488 		break;
1489 	}
1490 	return -EOPNOTSUPP;
1491 }
1492 
1493 static int
w83627ehf_do_read_fan(struct w83627ehf_data * data,u32 attr,int channel,long * val)1494 w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
1495 		      int channel, long *val)
1496 {
1497 	switch (attr) {
1498 	case hwmon_fan_input:
1499 		*val = data->rpm[channel];
1500 		return 0;
1501 	case hwmon_fan_min:
1502 		*val = fan_from_reg8(data->fan_min[channel],
1503 				     data->fan_div[channel]);
1504 		return 0;
1505 	case hwmon_fan_div:
1506 		*val = div_from_reg(data->fan_div[channel]);
1507 		return 0;
1508 	case hwmon_fan_alarm:
1509 		if (channel < 5) {
1510 			int bit[] = { 6, 7, 11, 10, 23 };
1511 			*val = (data->alarms >> bit[channel]) & 1;
1512 			return 0;
1513 		}
1514 		break;
1515 	default:
1516 		break;
1517 	}
1518 	return -EOPNOTSUPP;
1519 }
1520 
1521 static int
w83627ehf_do_read_pwm(struct w83627ehf_data * data,u32 attr,int channel,long * val)1522 w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
1523 		      int channel, long *val)
1524 {
1525 	switch (attr) {
1526 	case hwmon_pwm_input:
1527 		*val = data->pwm[channel];
1528 		return 0;
1529 	case hwmon_pwm_enable:
1530 		*val = data->pwm_enable[channel];
1531 		return 0;
1532 	case hwmon_pwm_mode:
1533 		*val = data->pwm_enable[channel];
1534 		return 0;
1535 	default:
1536 		break;
1537 	}
1538 	return -EOPNOTSUPP;
1539 }
1540 
1541 static int
w83627ehf_do_read_intrusion(struct w83627ehf_data * data,u32 attr,int channel,long * val)1542 w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
1543 			    int channel, long *val)
1544 {
1545 	if (attr != hwmon_intrusion_alarm || channel != 0)
1546 		return -EOPNOTSUPP; /* shouldn't happen */
1547 
1548 	*val = !!(data->caseopen & 0x10);
1549 	return 0;
1550 }
1551 
1552 static int
w83627ehf_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)1553 w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
1554 			u32 attr, int channel, long *val)
1555 {
1556 	struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
1557 
1558 	switch (type) {
1559 	case hwmon_fan:
1560 		return w83627ehf_do_read_fan(data, attr, channel, val);
1561 
1562 	case hwmon_in:
1563 		return w83627ehf_do_read_in(data, attr, channel, val);
1564 
1565 	case hwmon_pwm:
1566 		return w83627ehf_do_read_pwm(data, attr, channel, val);
1567 
1568 	case hwmon_temp:
1569 		return w83627ehf_do_read_temp(data, attr, channel, val);
1570 
1571 	case hwmon_intrusion:
1572 		return w83627ehf_do_read_intrusion(data, attr, channel, val);
1573 
1574 	default:
1575 		break;
1576 	}
1577 
1578 	return -EOPNOTSUPP;
1579 }
1580 
1581 static int
w83627ehf_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)1582 w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
1583 		      u32 attr, int channel, const char **str)
1584 {
1585 	struct w83627ehf_data *data = dev_get_drvdata(dev);
1586 
1587 	switch (type) {
1588 	case hwmon_temp:
1589 		if (attr == hwmon_temp_label) {
1590 			*str = data->temp_label[data->temp_src[channel]];
1591 			return 0;
1592 		}
1593 		break;
1594 
1595 	default:
1596 		break;
1597 	}
1598 	/* Nothing else should be read as a string */
1599 	return -EOPNOTSUPP;
1600 }
1601 
1602 static int
w83627ehf_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)1603 w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
1604 			u32 attr, int channel, long val)
1605 {
1606 	struct w83627ehf_data *data = dev_get_drvdata(dev);
1607 
1608 	if (type == hwmon_in && attr == hwmon_in_min)
1609 		return store_in_min(dev, data, channel, val);
1610 	if (type == hwmon_in && attr == hwmon_in_max)
1611 		return store_in_max(dev, data, channel, val);
1612 
1613 	if (type == hwmon_fan && attr == hwmon_fan_min)
1614 		return store_fan_min(dev, data, channel, val);
1615 
1616 	if (type == hwmon_temp && attr == hwmon_temp_max)
1617 		return store_temp_max(dev, data, channel, val);
1618 	if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
1619 		return store_temp_max_hyst(dev, data, channel, val);
1620 	if (type == hwmon_temp && attr == hwmon_temp_offset)
1621 		return store_temp_offset(dev, data, channel, val);
1622 
1623 	if (type == hwmon_pwm && attr == hwmon_pwm_mode)
1624 		return store_pwm_mode(dev, data, channel, val);
1625 	if (type == hwmon_pwm && attr == hwmon_pwm_enable)
1626 		return store_pwm_enable(dev, data, channel, val);
1627 	if (type == hwmon_pwm && attr == hwmon_pwm_input)
1628 		return store_pwm(dev, data, channel, val);
1629 
1630 	if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
1631 		return clear_caseopen(dev, data, channel, val);
1632 
1633 	return -EOPNOTSUPP;
1634 }
1635 
1636 static const struct hwmon_ops w83627ehf_ops = {
1637 	.is_visible = w83627ehf_is_visible,
1638 	.read = w83627ehf_read,
1639 	.read_string = w83627ehf_read_string,
1640 	.write = w83627ehf_write,
1641 };
1642 
1643 static const struct hwmon_channel_info * const w83627ehf_info[] = {
1644 	HWMON_CHANNEL_INFO(fan,
1645 		HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1646 		HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1647 		HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1648 		HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
1649 		HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
1650 	HWMON_CHANNEL_INFO(in,
1651 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1652 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1653 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1654 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1655 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1656 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1657 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1658 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1659 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
1660 		HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
1661 	HWMON_CHANNEL_INFO(pwm,
1662 		HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1663 		HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1664 		HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
1665 		HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
1666 	HWMON_CHANNEL_INFO(temp,
1667 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1668 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1669 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1670 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1671 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1672 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1673 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1674 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1675 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1676 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1677 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1678 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1679 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1680 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1681 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1682 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
1683 		HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
1684 			HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
1685 	HWMON_CHANNEL_INFO(intrusion,
1686 		HWMON_INTRUSION_ALARM),
1687 	NULL
1688 };
1689 
1690 static const struct hwmon_chip_info w83627ehf_chip_info = {
1691 	.ops = &w83627ehf_ops,
1692 	.info = w83627ehf_info,
1693 };
1694 
w83627ehf_probe(struct platform_device * pdev)1695 static int __init w83627ehf_probe(struct platform_device *pdev)
1696 {
1697 	struct device *dev = &pdev->dev;
1698 	struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
1699 	struct w83627ehf_data *data;
1700 	struct resource *res;
1701 	u8 en_vrm10;
1702 	int i, err = 0;
1703 	struct device *hwmon_dev;
1704 
1705 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1706 	if (!devm_request_region(dev, res->start, IOREGION_LENGTH, DRVNAME))
1707 		return -EBUSY;
1708 
1709 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1710 	if (!data)
1711 		return -ENOMEM;
1712 
1713 	data->addr = res->start;
1714 	mutex_init(&data->lock);
1715 	mutex_init(&data->update_lock);
1716 	data->name = w83627ehf_device_names[sio_data->kind];
1717 	data->bank = 0xff;		/* Force initial bank selection */
1718 	platform_set_drvdata(pdev, data);
1719 
1720 	/* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1721 	data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1722 	/* 667HG has 3 pwms, and 627UHG has only 2 */
1723 	switch (sio_data->kind) {
1724 	default:
1725 		data->pwm_num = 4;
1726 		break;
1727 	case w83667hg:
1728 	case w83667hg_b:
1729 		data->pwm_num = 3;
1730 		break;
1731 	case w83627uhg:
1732 		data->pwm_num = 2;
1733 		break;
1734 	}
1735 
1736 	/* Default to 3 temperature inputs, code below will adjust as needed */
1737 	data->have_temp = 0x07;
1738 
1739 	/* Deal with temperature register setup first. */
1740 	if (sio_data->kind == w83667hg_b) {
1741 		u8 reg;
1742 
1743 		w83627ehf_set_temp_reg_ehf(data, 4);
1744 
1745 		/*
1746 		 * Temperature sources are selected with bank 0, registers 0x49
1747 		 * and 0x4a.
1748 		 */
1749 		reg = w83627ehf_read_value(data, 0x4a);
1750 		data->temp_src[0] = reg >> 5;
1751 		reg = w83627ehf_read_value(data, 0x49);
1752 		data->temp_src[1] = reg & 0x07;
1753 		data->temp_src[2] = (reg >> 4) & 0x07;
1754 
1755 		/*
1756 		 * W83667HG-B has another temperature register at 0x7e.
1757 		 * The temperature source is selected with register 0x7d.
1758 		 * Support it if the source differs from already reported
1759 		 * sources.
1760 		 */
1761 		reg = w83627ehf_read_value(data, 0x7d);
1762 		reg &= 0x07;
1763 		if (reg != data->temp_src[0] && reg != data->temp_src[1]
1764 		    && reg != data->temp_src[2]) {
1765 			data->temp_src[3] = reg;
1766 			data->have_temp |= 1 << 3;
1767 		}
1768 
1769 		/*
1770 		 * Chip supports either AUXTIN or VIN3. Try to find out which
1771 		 * one.
1772 		 */
1773 		reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1774 		if (data->temp_src[2] == 2 && (reg & 0x01))
1775 			data->have_temp &= ~(1 << 2);
1776 
1777 		if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
1778 		    || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
1779 			data->in6_skip = 1;
1780 
1781 		data->temp_label = w83667hg_b_temp_label;
1782 		data->have_temp_offset = data->have_temp & 0x07;
1783 		for (i = 0; i < 3; i++) {
1784 			if (data->temp_src[i] > 2)
1785 				data->have_temp_offset &= ~(1 << i);
1786 		}
1787 	} else if (sio_data->kind == w83627uhg) {
1788 		u8 reg;
1789 
1790 		w83627ehf_set_temp_reg_ehf(data, 3);
1791 
1792 		/*
1793 		 * Temperature sources for temp2 and temp3 are selected with
1794 		 * bank 0, registers 0x49 and 0x4a.
1795 		 */
1796 		data->temp_src[0] = 0;	/* SYSTIN */
1797 		reg = w83627ehf_read_value(data, 0x49) & 0x07;
1798 		/* Adjust to have the same mapping as other source registers */
1799 		if (reg == 0)
1800 			data->temp_src[1] = 1;
1801 		else if (reg >= 2 && reg <= 5)
1802 			data->temp_src[1] = reg + 2;
1803 		else	/* should never happen */
1804 			data->have_temp &= ~(1 << 1);
1805 		reg = w83627ehf_read_value(data, 0x4a);
1806 		data->temp_src[2] = reg >> 5;
1807 
1808 		/*
1809 		 * Skip temp3 if source is invalid or the same as temp1
1810 		 * or temp2.
1811 		 */
1812 		if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
1813 		    data->temp_src[2] == data->temp_src[0] ||
1814 		    ((data->have_temp & (1 << 1)) &&
1815 		     data->temp_src[2] == data->temp_src[1]))
1816 			data->have_temp &= ~(1 << 2);
1817 		else
1818 			data->temp3_val_only = 1;	/* No limit regs */
1819 
1820 		data->in6_skip = 1;			/* No VIN3 */
1821 
1822 		data->temp_label = w83667hg_b_temp_label;
1823 		data->have_temp_offset = data->have_temp & 0x03;
1824 		for (i = 0; i < 3; i++) {
1825 			if (data->temp_src[i] > 1)
1826 				data->have_temp_offset &= ~(1 << i);
1827 		}
1828 	} else {
1829 		w83627ehf_set_temp_reg_ehf(data, 3);
1830 
1831 		/* Temperature sources are fixed */
1832 
1833 		if (sio_data->kind == w83667hg) {
1834 			u8 reg;
1835 
1836 			/*
1837 			 * Chip supports either AUXTIN or VIN3. Try to find
1838 			 * out which one.
1839 			 */
1840 			reg = w83627ehf_read_value(data,
1841 						W83627EHF_REG_TEMP_CONFIG[2]);
1842 			if (reg & 0x01)
1843 				data->have_temp &= ~(1 << 2);
1844 			else
1845 				data->in6_skip = 1;
1846 		}
1847 		data->have_temp_offset = data->have_temp & 0x07;
1848 	}
1849 
1850 	if (sio_data->kind == w83667hg_b) {
1851 		data->REG_FAN_MAX_OUTPUT =
1852 		  W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
1853 		data->REG_FAN_STEP_OUTPUT =
1854 		  W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
1855 	} else {
1856 		data->REG_FAN_MAX_OUTPUT =
1857 		  W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
1858 		data->REG_FAN_STEP_OUTPUT =
1859 		  W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
1860 	}
1861 
1862 	/* Setup input voltage scaling factors */
1863 	if (sio_data->kind == w83627uhg)
1864 		data->scale_in = scale_in_w83627uhg;
1865 	else
1866 		data->scale_in = scale_in_common;
1867 
1868 	/* Initialize the chip */
1869 	w83627ehf_init_device(data, sio_data->kind);
1870 
1871 	data->vrm = vid_which_vrm();
1872 
1873 	err = superio_enter(sio_data->sioreg);
1874 	if (err)
1875 		return err;
1876 
1877 	/* Read VID value */
1878 	if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1879 		/*
1880 		 * W83667HG has different pins for VID input and output, so
1881 		 * we can get the VID input values directly at logical device D
1882 		 * 0xe3.
1883 		 */
1884 		superio_select(sio_data->sioreg, W83667HG_LD_VID);
1885 		data->vid = superio_inb(sio_data->sioreg, 0xe3);
1886 		data->have_vid = true;
1887 	} else if (sio_data->kind != w83627uhg) {
1888 		superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1889 		if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
1890 			/*
1891 			 * Set VID input sensibility if needed. In theory the
1892 			 * BIOS should have set it, but in practice it's not
1893 			 * always the case. We only do it for the W83627EHF/EHG
1894 			 * because the W83627DHG is more complex in this
1895 			 * respect.
1896 			 */
1897 			if (sio_data->kind == w83627ehf) {
1898 				en_vrm10 = superio_inb(sio_data->sioreg,
1899 						       SIO_REG_EN_VRM10);
1900 				if ((en_vrm10 & 0x08) && data->vrm == 90) {
1901 					dev_warn(dev,
1902 						 "Setting VID input voltage to TTL\n");
1903 					superio_outb(sio_data->sioreg,
1904 						     SIO_REG_EN_VRM10,
1905 						     en_vrm10 & ~0x08);
1906 				} else if (!(en_vrm10 & 0x08)
1907 					   && data->vrm == 100) {
1908 					dev_warn(dev,
1909 						 "Setting VID input voltage to VRM10\n");
1910 					superio_outb(sio_data->sioreg,
1911 						     SIO_REG_EN_VRM10,
1912 						     en_vrm10 | 0x08);
1913 				}
1914 			}
1915 
1916 			data->vid = superio_inb(sio_data->sioreg,
1917 						SIO_REG_VID_DATA);
1918 			if (sio_data->kind == w83627ehf) /* 6 VID pins only */
1919 				data->vid &= 0x3f;
1920 			data->have_vid = true;
1921 		} else {
1922 			dev_info(dev,
1923 				 "VID pins in output mode, CPU VID not available\n");
1924 		}
1925 	}
1926 
1927 	w83627ehf_check_fan_inputs(sio_data, data);
1928 
1929 	superio_exit(sio_data->sioreg);
1930 
1931 	/* Read fan clock dividers immediately */
1932 	w83627ehf_update_fan_div(data);
1933 
1934 	/* Read pwm data to save original values */
1935 	w83627ehf_update_pwm(data);
1936 	for (i = 0; i < data->pwm_num; i++)
1937 		data->pwm_enable_orig[i] = data->pwm_enable[i];
1938 
1939 	hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
1940 							 data->name,
1941 							 data,
1942 							 &w83627ehf_chip_info,
1943 							 w83627ehf_groups);
1944 	return PTR_ERR_OR_ZERO(hwmon_dev);
1945 }
1946 
w83627ehf_suspend(struct device * dev)1947 static int w83627ehf_suspend(struct device *dev)
1948 {
1949 	struct w83627ehf_data *data = w83627ehf_update_device(dev);
1950 
1951 	mutex_lock(&data->update_lock);
1952 	data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1953 	mutex_unlock(&data->update_lock);
1954 
1955 	return 0;
1956 }
1957 
w83627ehf_resume(struct device * dev)1958 static int w83627ehf_resume(struct device *dev)
1959 {
1960 	struct w83627ehf_data *data = dev_get_drvdata(dev);
1961 	int i;
1962 
1963 	mutex_lock(&data->update_lock);
1964 	data->bank = 0xff;		/* Force initial bank selection */
1965 
1966 	/* Restore limits */
1967 	for (i = 0; i < data->in_num; i++) {
1968 		if ((i == 6) && data->in6_skip)
1969 			continue;
1970 
1971 		w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
1972 				      data->in_min[i]);
1973 		w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
1974 				      data->in_max[i]);
1975 	}
1976 
1977 	for (i = 0; i < 5; i++) {
1978 		if (!(data->has_fan_min & (1 << i)))
1979 			continue;
1980 
1981 		w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
1982 				      data->fan_min[i]);
1983 	}
1984 
1985 	for (i = 0; i < NUM_REG_TEMP; i++) {
1986 		if (!(data->have_temp & (1 << i)))
1987 			continue;
1988 
1989 		if (data->reg_temp_over[i])
1990 			w83627ehf_write_temp(data, data->reg_temp_over[i],
1991 					     data->temp_max[i]);
1992 		if (data->reg_temp_hyst[i])
1993 			w83627ehf_write_temp(data, data->reg_temp_hyst[i],
1994 					     data->temp_max_hyst[i]);
1995 		if (i > 2)
1996 			continue;
1997 		if (data->have_temp_offset & (1 << i))
1998 			w83627ehf_write_value(data,
1999 					      W83627EHF_REG_TEMP_OFFSET[i],
2000 					      data->temp_offset[i]);
2001 	}
2002 
2003 	/* Restore other settings */
2004 	w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
2005 
2006 	/* Force re-reading all values */
2007 	data->valid = false;
2008 	mutex_unlock(&data->update_lock);
2009 
2010 	return 0;
2011 }
2012 
2013 static DEFINE_SIMPLE_DEV_PM_OPS(w83627ehf_dev_pm_ops, w83627ehf_suspend, w83627ehf_resume);
2014 
2015 static struct platform_driver w83627ehf_driver = {
2016 	.driver = {
2017 		.name	= DRVNAME,
2018 		.pm	= pm_sleep_ptr(&w83627ehf_dev_pm_ops),
2019 	},
2020 };
2021 
2022 /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
w83627ehf_find(int sioaddr,unsigned short * addr,struct w83627ehf_sio_data * sio_data)2023 static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2024 				 struct w83627ehf_sio_data *sio_data)
2025 {
2026 	static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2027 	static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2028 	static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2029 	static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2030 	static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2031 	static const char sio_name_W83667HG[] __initconst = "W83667HG";
2032 	static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2033 
2034 	u16 val;
2035 	const char *sio_name;
2036 	int err;
2037 
2038 	err = superio_enter(sioaddr);
2039 	if (err)
2040 		return err;
2041 
2042 	if (force_id)
2043 		val = force_id;
2044 	else
2045 		val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2046 		    | superio_inb(sioaddr, SIO_REG_DEVID + 1);
2047 	switch (val & SIO_ID_MASK) {
2048 	case SIO_W83627EHF_ID:
2049 		sio_data->kind = w83627ehf;
2050 		sio_name = sio_name_W83627EHF;
2051 		break;
2052 	case SIO_W83627EHG_ID:
2053 		sio_data->kind = w83627ehf;
2054 		sio_name = sio_name_W83627EHG;
2055 		break;
2056 	case SIO_W83627DHG_ID:
2057 		sio_data->kind = w83627dhg;
2058 		sio_name = sio_name_W83627DHG;
2059 		break;
2060 	case SIO_W83627DHG_P_ID:
2061 		sio_data->kind = w83627dhg_p;
2062 		sio_name = sio_name_W83627DHG_P;
2063 		break;
2064 	case SIO_W83627UHG_ID:
2065 		sio_data->kind = w83627uhg;
2066 		sio_name = sio_name_W83627UHG;
2067 		break;
2068 	case SIO_W83667HG_ID:
2069 		sio_data->kind = w83667hg;
2070 		sio_name = sio_name_W83667HG;
2071 		break;
2072 	case SIO_W83667HG_B_ID:
2073 		sio_data->kind = w83667hg_b;
2074 		sio_name = sio_name_W83667HG_B;
2075 		break;
2076 	default:
2077 		if (val != 0xffff)
2078 			pr_debug("unsupported chip ID: 0x%04x\n", val);
2079 		superio_exit(sioaddr);
2080 		return -ENODEV;
2081 	}
2082 
2083 	/* We have a known chip, find the HWM I/O address */
2084 	superio_select(sioaddr, W83627EHF_LD_HWM);
2085 	val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2086 	    | superio_inb(sioaddr, SIO_REG_ADDR + 1);
2087 	*addr = val & IOREGION_ALIGNMENT;
2088 	if (*addr == 0) {
2089 		pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
2090 		superio_exit(sioaddr);
2091 		return -ENODEV;
2092 	}
2093 
2094 	/* Activate logical device if needed */
2095 	val = superio_inb(sioaddr, SIO_REG_ENABLE);
2096 	if (!(val & 0x01)) {
2097 		pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
2098 		superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
2099 	}
2100 
2101 	superio_exit(sioaddr);
2102 	pr_info("Found %s chip at %#x\n", sio_name, *addr);
2103 	sio_data->sioreg = sioaddr;
2104 
2105 	return 0;
2106 }
2107 
2108 /*
2109  * when Super-I/O functions move to a separate file, the Super-I/O
2110  * bus will manage the lifetime of the device and this module will only keep
2111  * track of the w83627ehf driver.
2112  */
2113 static struct platform_device *pdev;
2114 
sensors_w83627ehf_init(void)2115 static int __init sensors_w83627ehf_init(void)
2116 {
2117 	int err;
2118 	unsigned short address;
2119 	struct resource res = {
2120 		.name	= DRVNAME,
2121 		.flags	= IORESOURCE_IO,
2122 	};
2123 	struct w83627ehf_sio_data sio_data;
2124 
2125 	/*
2126 	 * initialize sio_data->kind and sio_data->sioreg.
2127 	 *
2128 	 * when Super-I/O functions move to a separate file, the Super-I/O
2129 	 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2130 	 * w83627ehf hardware monitor, and call probe()
2131 	 */
2132 	if (w83627ehf_find(0x2e, &address, &sio_data) &&
2133 	    w83627ehf_find(0x4e, &address, &sio_data))
2134 		return -ENODEV;
2135 
2136 	res.start = address + IOREGION_OFFSET;
2137 	res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2138 
2139 	err = acpi_check_resource_conflict(&res);
2140 	if (err)
2141 		return err;
2142 
2143 	pdev = platform_create_bundle(&w83627ehf_driver, w83627ehf_probe, &res, 1, &sio_data,
2144 				      sizeof(struct w83627ehf_sio_data));
2145 
2146 	return PTR_ERR_OR_ZERO(pdev);
2147 }
2148 
sensors_w83627ehf_exit(void)2149 static void __exit sensors_w83627ehf_exit(void)
2150 {
2151 	platform_device_unregister(pdev);
2152 	platform_driver_unregister(&w83627ehf_driver);
2153 }
2154 
2155 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
2156 MODULE_DESCRIPTION("W83627EHF driver");
2157 MODULE_LICENSE("GPL");
2158 
2159 module_init(sensors_w83627ehf_init);
2160 module_exit(sensors_w83627ehf_exit);
2161