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"verify_chip_mark_7", 1797 "01": "verify_chip_mark_7" 1798 }, 1799 "09": { 1800 "00": "mainline_nce_tce_handling", 1801 "01": "mainline_nce_tce_handling" 1802 }, 1803 "0a": { 1804 "00": "mainline_nce_tce_handling", 1805 "01": "mainline_nce_tce_handling" 1806 }, 1807 "0b": { 1808 "00": "level2_M_th_1", 1809 "01": "level2_M_th_1" 1810 }, 1811 "0c": { 1812 "00": "level2_M_th_1", 1813 "01": "level2_M_th_1" 1814 }, 1815 "0d": { 1816 "00": "level2_M_th_1", 1817 "01": "level2_M_th_1" 1818 }, 1819 "0e": { 1820 "00": "dimm0_H_mem_port0_L_th_1", 1821 "01": "dimm1_H_mem_port1_L_th_1", 1822 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1823 }, 1824 "0f": { 1825 "00": "mainline_ue_handling_0", 1826 "01": "mainline_ue_handling_1", 1827 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1828 }, 1829 "10": { 1830 "00": "dimm0_H_mem_port0_L_th_1", 1831 "01": "dimm1_H_mem_port1_L_th_1", 1832 "flags": ["sue_source"] 1833 }, 1834 "11": { 1835 "00": "dimm0_H_mem_port0_L_th_1", 1836 "01": "dimm1_H_mem_port1_L_th_1", 1837 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1838 }, 1839 "12": { 1840 "00": "mainline_iue_handling_0", 1841 "01": "mainline_iue_handling_1", 1842 "flags": ["sue_source", "odp_data_corrupt_side_effect"] 1843 }, 1844 "13": { 1845 "00": "dimm0_H_mem_port0_L_th_32perDay", 1846 "01": "dimm1_H_mem_port1_L_th_32perDay" 1847 }, 1848 "14": { 1849 "00": "memory_impe_handling_0", 1850 "01": "memory_impe_handling_1" 1851 }, 1852 "15": { 1853 "00": "level2_M_th_1", 1854 "01": "level2_M_th_1" 1855 }, 1856 "16": { 1857 "00": "level2_M_th_1", 1858 "01": "level2_M_th_1" 1859 }, 1860 "17": { 1861 "00": "level2_M_th_1", 1862 "01": "level2_M_th_1" 1863 }, 1864 "18": { 1865 "00": "level2_M_th_1", 1866 "01": "level2_M_th_1" 1867 }, 1868 "19": { 1869 "00": "level2_M_th_1", 1870 "01": "level2_M_th_1" 1871 }, 1872 "1a": { 1873 "00": "level2_M_th_1", 1874 "01": "level2_M_th_1" 1875 }, 1876 "1b": { 1877 "00": "level2_M_th_1", 1878 "01": "level2_M_th_1" 1879 }, 1880 "1c": { 1881 "00": "level2_M_th_1", 1882 "01": "level2_M_th_1" 1883 }, 1884 "1d": { 1885 "00": "level2_M_th_1", 1886 "01": "level2_M_th_1" 1887 }, 1888 "1e": { 1889 "00": "level2_M_th_1", 1890 "01": "level2_M_th_1" 1891 }, 1892 "1f": { 1893 "00": "level2_M_th_1", 1894 "01": "level2_M_th_1" 1895 }, 1896 "20": { 1897 "00": "level2_M_th_1", 1898 "01": "level2_M_th_1" 1899 }, 1900 "21": { 1901 "00": "level2_M_th_1", 1902 "01": "level2_M_th_1" 1903 }, 1904 "22": { 1905 "00": "dimm0_H_mem_port0_L_th_1", 1906 "01": "dimm1_H_mem_port1_L_th_1", 1907 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1908 }, 1909 "23": { 1910 "00": "level2_M_th_1", 1911 "01": "level2_M_th_1" 1912 }, 1913 "24": { 1914 "00": "dimm0_H_mem_port0_L_th_1", 1915 "01": "dimm1_H_mem_port1_L_th_1" 1916 }, 1917 "25": { 1918 "00": "dimm0_H_mem_port0_L_th_1", 1919 "01": "dimm1_H_mem_port1_L_th_1", 1920 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1921 }, 1922 "26": { 1923 "00": "maintenance_iue_handling_0", 1924 "01": "maintenance_iue_handling_1", 1925 "flags": ["sue_source", "odp_data_corrupt_side_effect"] 1926 }, 1927 "27": { 1928 "00": "dimm0_H_mem_port0_L_th_32perDay", 1929 "01": "dimm1_H_mem_port1_L_th_32perDay" 1930 }, 1931 "28": { 1932 "00": "memory_impe_handling_0", 1933 "01": "memory_impe_handling_1" 1934 }, 1935 "29": { 1936 "00": "mem_port0_M_th_1", 1937 "01": "mem_port1_M_th_1", 1938 "flags": ["sue_source"] 1939 }, 1940 "2a": { 1941 "00": "mem_port0_M_info_only", 1942 "01": "mem_port1_M_info_only" 1943 }, 1944 "2b": { 1945 "00": "mem_port0_M_th_1", 1946 "01": "mem_port1_M_th_1" 1947 }, 1948 "2c": { 1949 "00": "mem_port0_M_th_1", 1950 "01": "mem_port1_M_th_1", 1951 "flags": ["sue_source"] 1952 }, 1953 "2d": { 1954 "00": "mem_port0_M_th_1", 1955 "01": "mem_port1_M_th_1", 1956 "flags": ["sue_source"] 1957 }, 1958 "2e": { 1959 "00": "mem_port0_M_th_32perDay", 1960 "01": "mem_port1_M_th_32perDay" 1961 }, 1962 "2f": { 1963 "00": "mem_port0_M_th_32perDay", 1964 "01": "mem_port1_M_th_32perDay" 1965 }, 1966 "30": { 1967 "00": "mem_port0_M_th_1", 1968 "01": "mem_port1_M_th_1", 1969 "flags": ["sue_source"] 1970 }, 1971 "31": { 1972 "00": "mem_port0_M_th_1", 1973 "01": "mem_port1_M_th_1", 1974 "flags": ["sue_source"] 1975 }, 1976 "32": { 1977 "00": "level2_M_th_1", 1978 "01": "level2_M_th_1" 1979 }, 1980 "33": { 1981 "00": "level2_M_th_1", 1982 "01": "level2_M_th_1" 1983 }, 1984 "34": { 1985 "00": "level2_M_th_1", 1986 "01": "level2_M_th_1" 1987 }, 1988 "35": { 1989 "00": "level2_M_th_1", 1990 "01": "level2_M_th_1" 1991 }, 1992 "36": { 1993 "00": "mem_port0_M_th_1", 1994 "01": "mem_port1_M_th_1", 1995 "flags": ["sue_source"] 1996 }, 1997 "37": { 1998 "00": "level2_M_th_1", 1999 "01": "level2_M_th_1" 2000 }, 2001 "38": { 2002 "00": "level2_M_th_1", 2003 "01": "level2_M_th_1" 2004 }, 2005 "39": { 2006 "00": "level2_M_th_1", 2007 "01": "level2_M_th_1" 2008 }, 2009 "3a": { 2010 "00": "level2_M_th_1", 2011 "01": "level2_M_th_1" 2012 }, 2013 "3b": { 2014 "00": "level2_M_th_1", 2015 "01": "level2_M_th_1" 2016 }, 2017 "3c": { 2018 "00": "level2_M_th_1", 2019 "01": "level2_M_th_1" 2020 }, 2021 "3d": { 2022 "00": "level2_M_th_1", 2023 "01": "level2_M_th_1" 2024 }, 2025 "3e": { 2026 "00": "level2_M_th_1", 2027 "01": "level2_M_th_1" 2028 } 2029 } 2030 }, 2031 "units": { 2032 "dimm0": "mem_port0/dimm0", 2033 "dimm1": "mem_port1/dimm0", 2034 "mem_port0": "mem_port0", 2035 "mem_port1": "mem_port1" 2036 }, 2037 "version": 2 2038} 2039