xref: /openbmc/linux/drivers/gpu/drm/msm/msm_gpu.c (revision 9288a967)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include "drm/drm_drv.h"
8 
9 #include "msm_gpu.h"
10 #include "msm_gem.h"
11 #include "msm_mmu.h"
12 #include "msm_fence.h"
13 #include "msm_gpu_trace.h"
14 #include "adreno/adreno_gpu.h"
15 
16 #include <generated/utsrelease.h>
17 #include <linux/string_helpers.h>
18 #include <linux/devcoredump.h>
19 #include <linux/sched/task.h>
20 
21 /*
22  * Power Management:
23  */
24 
enable_pwrrail(struct msm_gpu * gpu)25 static int enable_pwrrail(struct msm_gpu *gpu)
26 {
27 	struct drm_device *dev = gpu->dev;
28 	int ret = 0;
29 
30 	if (gpu->gpu_reg) {
31 		ret = regulator_enable(gpu->gpu_reg);
32 		if (ret) {
33 			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
34 			return ret;
35 		}
36 	}
37 
38 	if (gpu->gpu_cx) {
39 		ret = regulator_enable(gpu->gpu_cx);
40 		if (ret) {
41 			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
42 			return ret;
43 		}
44 	}
45 
46 	return 0;
47 }
48 
disable_pwrrail(struct msm_gpu * gpu)49 static int disable_pwrrail(struct msm_gpu *gpu)
50 {
51 	if (gpu->gpu_cx)
52 		regulator_disable(gpu->gpu_cx);
53 	if (gpu->gpu_reg)
54 		regulator_disable(gpu->gpu_reg);
55 	return 0;
56 }
57 
enable_clk(struct msm_gpu * gpu)58 static int enable_clk(struct msm_gpu *gpu)
59 {
60 	if (gpu->core_clk && gpu->fast_rate)
61 		dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate);
62 
63 	/* Set the RBBM timer rate to 19.2Mhz */
64 	if (gpu->rbbmtimer_clk)
65 		clk_set_rate(gpu->rbbmtimer_clk, 19200000);
66 
67 	return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
68 }
69 
disable_clk(struct msm_gpu * gpu)70 static int disable_clk(struct msm_gpu *gpu)
71 {
72 	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
73 
74 	/*
75 	 * Set the clock to a deliberately low rate. On older targets the clock
76 	 * speed had to be non zero to avoid problems. On newer targets this
77 	 * will be rounded down to zero anyway so it all works out.
78 	 */
79 	if (gpu->core_clk)
80 		dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000);
81 
82 	if (gpu->rbbmtimer_clk)
83 		clk_set_rate(gpu->rbbmtimer_clk, 0);
84 
85 	return 0;
86 }
87 
enable_axi(struct msm_gpu * gpu)88 static int enable_axi(struct msm_gpu *gpu)
89 {
90 	return clk_prepare_enable(gpu->ebi1_clk);
91 }
92 
disable_axi(struct msm_gpu * gpu)93 static int disable_axi(struct msm_gpu *gpu)
94 {
95 	clk_disable_unprepare(gpu->ebi1_clk);
96 	return 0;
97 }
98 
msm_gpu_pm_resume(struct msm_gpu * gpu)99 int msm_gpu_pm_resume(struct msm_gpu *gpu)
100 {
101 	int ret;
102 
103 	DBG("%s", gpu->name);
104 	trace_msm_gpu_resume(0);
105 
106 	ret = enable_pwrrail(gpu);
107 	if (ret)
108 		return ret;
109 
110 	ret = enable_clk(gpu);
111 	if (ret)
112 		return ret;
113 
114 	ret = enable_axi(gpu);
115 	if (ret)
116 		return ret;
117 
118 	msm_devfreq_resume(gpu);
119 
120 	gpu->needs_hw_init = true;
121 
122 	return 0;
123 }
124 
msm_gpu_pm_suspend(struct msm_gpu * gpu)125 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
126 {
127 	int ret;
128 
129 	DBG("%s", gpu->name);
130 	trace_msm_gpu_suspend(0);
131 
132 	msm_devfreq_suspend(gpu);
133 
134 	ret = disable_axi(gpu);
135 	if (ret)
136 		return ret;
137 
138 	ret = disable_clk(gpu);
139 	if (ret)
140 		return ret;
141 
142 	ret = disable_pwrrail(gpu);
143 	if (ret)
144 		return ret;
145 
146 	gpu->suspend_count++;
147 
148 	return 0;
149 }
150 
msm_gpu_show_fdinfo(struct msm_gpu * gpu,struct msm_file_private * ctx,struct drm_printer * p)151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
152 			 struct drm_printer *p)
153 {
154 	drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
155 	drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
156 	drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
157 }
158 
msm_gpu_hw_init(struct msm_gpu * gpu)159 int msm_gpu_hw_init(struct msm_gpu *gpu)
160 {
161 	int ret;
162 
163 	WARN_ON(!mutex_is_locked(&gpu->lock));
164 
165 	if (!gpu->needs_hw_init)
166 		return 0;
167 
168 	disable_irq(gpu->irq);
169 	ret = gpu->funcs->hw_init(gpu);
170 	if (!ret)
171 		gpu->needs_hw_init = false;
172 	enable_irq(gpu->irq);
173 
174 	return ret;
175 }
176 
177 #ifdef CONFIG_DEV_COREDUMP
msm_gpu_devcoredump_read(char * buffer,loff_t offset,size_t count,void * data,size_t datalen)178 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
179 		size_t count, void *data, size_t datalen)
180 {
181 	struct msm_gpu *gpu = data;
182 	struct drm_print_iterator iter;
183 	struct drm_printer p;
184 	struct msm_gpu_state *state;
185 
186 	state = msm_gpu_crashstate_get(gpu);
187 	if (!state)
188 		return 0;
189 
190 	iter.data = buffer;
191 	iter.offset = 0;
192 	iter.start = offset;
193 	iter.remain = count;
194 
195 	p = drm_coredump_printer(&iter);
196 
197 	drm_printf(&p, "---\n");
198 	drm_printf(&p, "kernel: " UTS_RELEASE "\n");
199 	drm_printf(&p, "module: " KBUILD_MODNAME "\n");
200 	drm_printf(&p, "time: %lld.%09ld\n",
201 		state->time.tv_sec, state->time.tv_nsec);
202 	if (state->comm)
203 		drm_printf(&p, "comm: %s\n", state->comm);
204 	if (state->cmd)
205 		drm_printf(&p, "cmdline: %s\n", state->cmd);
206 
207 	gpu->funcs->show(gpu, state, &p);
208 
209 	msm_gpu_crashstate_put(gpu);
210 
211 	return count - iter.remain;
212 }
213 
msm_gpu_devcoredump_free(void * data)214 static void msm_gpu_devcoredump_free(void *data)
215 {
216 	struct msm_gpu *gpu = data;
217 
218 	msm_gpu_crashstate_put(gpu);
219 }
220 
msm_gpu_crashstate_get_bo(struct msm_gpu_state * state,struct drm_gem_object * obj,u64 iova,bool full)221 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
222 		struct drm_gem_object *obj, u64 iova, bool full)
223 {
224 	struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
225 
226 	/* Don't record write only objects */
227 	state_bo->size = obj->size;
228 	state_bo->iova = iova;
229 
230 	BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(to_msm_bo(obj)->name));
231 
232 	memcpy(state_bo->name, to_msm_bo(obj)->name, sizeof(state_bo->name));
233 
234 	if (full) {
235 		void *ptr;
236 
237 		state_bo->data = kvmalloc(obj->size, GFP_KERNEL);
238 		if (!state_bo->data)
239 			goto out;
240 
241 		msm_gem_lock(obj);
242 		ptr = msm_gem_get_vaddr_active(obj);
243 		msm_gem_unlock(obj);
244 		if (IS_ERR(ptr)) {
245 			kvfree(state_bo->data);
246 			state_bo->data = NULL;
247 			goto out;
248 		}
249 
250 		memcpy(state_bo->data, ptr, obj->size);
251 		msm_gem_put_vaddr(obj);
252 	}
253 out:
254 	state->nr_bos++;
255 }
256 
msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,char * comm,char * cmd)257 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
258 		struct msm_gem_submit *submit, char *comm, char *cmd)
259 {
260 	struct msm_gpu_state *state;
261 
262 	/* Check if the target supports capturing crash state */
263 	if (!gpu->funcs->gpu_state_get)
264 		return;
265 
266 	/* Only save one crash state at a time */
267 	if (gpu->crashstate)
268 		return;
269 
270 	state = gpu->funcs->gpu_state_get(gpu);
271 	if (IS_ERR_OR_NULL(state))
272 		return;
273 
274 	/* Fill in the additional crash state information */
275 	state->comm = kstrdup(comm, GFP_KERNEL);
276 	state->cmd = kstrdup(cmd, GFP_KERNEL);
277 	state->fault_info = gpu->fault_info;
278 
279 	if (submit) {
280 		int i;
281 
282 		state->bos = kcalloc(submit->nr_bos,
283 			sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
284 
285 		for (i = 0; state->bos && i < submit->nr_bos; i++) {
286 			msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
287 						  submit->bos[i].iova,
288 						  should_dump(submit, i));
289 		}
290 	}
291 
292 	/* Set the active crash state to be dumped on failure */
293 	gpu->crashstate = state;
294 
295 	/* FIXME: Release the crashstate if this errors out? */
296 	dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
297 		msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
298 }
299 #else
msm_gpu_crashstate_capture(struct msm_gpu * gpu,struct msm_gem_submit * submit,char * comm,char * cmd)300 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
301 		struct msm_gem_submit *submit, char *comm, char *cmd)
302 {
303 }
304 #endif
305 
306 /*
307  * Hangcheck detection for locked gpu:
308  */
309 
310 static struct msm_gem_submit *
find_submit(struct msm_ringbuffer * ring,uint32_t fence)311 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
312 {
313 	struct msm_gem_submit *submit;
314 	unsigned long flags;
315 
316 	spin_lock_irqsave(&ring->submit_lock, flags);
317 	list_for_each_entry(submit, &ring->submits, node) {
318 		if (submit->seqno == fence) {
319 			spin_unlock_irqrestore(&ring->submit_lock, flags);
320 			return submit;
321 		}
322 	}
323 	spin_unlock_irqrestore(&ring->submit_lock, flags);
324 
325 	return NULL;
326 }
327 
328 static void retire_submits(struct msm_gpu *gpu);
329 
get_comm_cmdline(struct msm_gem_submit * submit,char ** comm,char ** cmd)330 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
331 {
332 	struct msm_file_private *ctx = submit->queue->ctx;
333 	struct task_struct *task;
334 
335 	WARN_ON(!mutex_is_locked(&submit->gpu->lock));
336 
337 	/* Note that kstrdup will return NULL if argument is NULL: */
338 	*comm = kstrdup(ctx->comm, GFP_KERNEL);
339 	*cmd  = kstrdup(ctx->cmdline, GFP_KERNEL);
340 
341 	task = get_pid_task(submit->pid, PIDTYPE_PID);
342 	if (!task)
343 		return;
344 
345 	if (!*comm)
346 		*comm = kstrdup(task->comm, GFP_KERNEL);
347 
348 	if (!*cmd)
349 		*cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
350 
351 	put_task_struct(task);
352 }
353 
recover_worker(struct kthread_work * work)354 static void recover_worker(struct kthread_work *work)
355 {
356 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
357 	struct drm_device *dev = gpu->dev;
358 	struct msm_drm_private *priv = dev->dev_private;
359 	struct msm_gem_submit *submit;
360 	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
361 	char *comm = NULL, *cmd = NULL;
362 	int i;
363 
364 	mutex_lock(&gpu->lock);
365 
366 	DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
367 
368 	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
369 	if (submit) {
370 		/* Increment the fault counts */
371 		submit->queue->faults++;
372 		if (submit->aspace)
373 			submit->aspace->faults++;
374 
375 		get_comm_cmdline(submit, &comm, &cmd);
376 
377 		if (comm && cmd) {
378 			DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
379 				gpu->name, comm, cmd);
380 
381 			msm_rd_dump_submit(priv->hangrd, submit,
382 				"offending task: %s (%s)", comm, cmd);
383 		} else {
384 			msm_rd_dump_submit(priv->hangrd, submit, NULL);
385 		}
386 	} else {
387 		/*
388 		 * We couldn't attribute this fault to any particular context,
389 		 * so increment the global fault count instead.
390 		 */
391 		gpu->global_faults++;
392 	}
393 
394 	/* Record the crash state */
395 	pm_runtime_get_sync(&gpu->pdev->dev);
396 	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
397 
398 	kfree(cmd);
399 	kfree(comm);
400 
401 	/*
402 	 * Update all the rings with the latest and greatest fence.. this
403 	 * needs to happen after msm_rd_dump_submit() to ensure that the
404 	 * bo's referenced by the offending submit are still around.
405 	 */
406 	for (i = 0; i < gpu->nr_rings; i++) {
407 		struct msm_ringbuffer *ring = gpu->rb[i];
408 
409 		uint32_t fence = ring->memptrs->fence;
410 
411 		/*
412 		 * For the current (faulting?) ring/submit advance the fence by
413 		 * one more to clear the faulting submit
414 		 */
415 		if (ring == cur_ring)
416 			ring->memptrs->fence = ++fence;
417 
418 		msm_update_fence(ring->fctx, fence);
419 	}
420 
421 	if (msm_gpu_active(gpu)) {
422 		/* retire completed submits, plus the one that hung: */
423 		retire_submits(gpu);
424 
425 		gpu->funcs->recover(gpu);
426 
427 		/*
428 		 * Replay all remaining submits starting with highest priority
429 		 * ring
430 		 */
431 		for (i = 0; i < gpu->nr_rings; i++) {
432 			struct msm_ringbuffer *ring = gpu->rb[i];
433 			unsigned long flags;
434 
435 			spin_lock_irqsave(&ring->submit_lock, flags);
436 			list_for_each_entry(submit, &ring->submits, node)
437 				gpu->funcs->submit(gpu, submit);
438 			spin_unlock_irqrestore(&ring->submit_lock, flags);
439 		}
440 	}
441 
442 	pm_runtime_put(&gpu->pdev->dev);
443 
444 	mutex_unlock(&gpu->lock);
445 
446 	msm_gpu_retire(gpu);
447 }
448 
fault_worker(struct kthread_work * work)449 static void fault_worker(struct kthread_work *work)
450 {
451 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
452 	struct msm_gem_submit *submit;
453 	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
454 	char *comm = NULL, *cmd = NULL;
455 
456 	mutex_lock(&gpu->lock);
457 
458 	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
459 	if (submit && submit->fault_dumped)
460 		goto resume_smmu;
461 
462 	if (submit) {
463 		get_comm_cmdline(submit, &comm, &cmd);
464 
465 		/*
466 		 * When we get GPU iova faults, we can get 1000s of them,
467 		 * but we really only want to log the first one.
468 		 */
469 		submit->fault_dumped = true;
470 	}
471 
472 	/* Record the crash state */
473 	pm_runtime_get_sync(&gpu->pdev->dev);
474 	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
475 	pm_runtime_put_sync(&gpu->pdev->dev);
476 
477 	kfree(cmd);
478 	kfree(comm);
479 
480 resume_smmu:
481 	memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
482 	gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
483 
484 	mutex_unlock(&gpu->lock);
485 }
486 
hangcheck_timer_reset(struct msm_gpu * gpu)487 static void hangcheck_timer_reset(struct msm_gpu *gpu)
488 {
489 	struct msm_drm_private *priv = gpu->dev->dev_private;
490 	mod_timer(&gpu->hangcheck_timer,
491 			round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
492 }
493 
made_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring)494 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
495 {
496 	if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES)
497 		return false;
498 
499 	if (!gpu->funcs->progress)
500 		return false;
501 
502 	if (!gpu->funcs->progress(gpu, ring))
503 		return false;
504 
505 	ring->hangcheck_progress_retries++;
506 	return true;
507 }
508 
hangcheck_handler(struct timer_list * t)509 static void hangcheck_handler(struct timer_list *t)
510 {
511 	struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
512 	struct drm_device *dev = gpu->dev;
513 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
514 	uint32_t fence = ring->memptrs->fence;
515 
516 	if (fence != ring->hangcheck_fence) {
517 		/* some progress has been made.. ya! */
518 		ring->hangcheck_fence = fence;
519 		ring->hangcheck_progress_retries = 0;
520 	} else if (fence_before(fence, ring->fctx->last_fence) &&
521 			!made_progress(gpu, ring)) {
522 		/* no progress and not done.. hung! */
523 		ring->hangcheck_fence = fence;
524 		ring->hangcheck_progress_retries = 0;
525 		DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
526 				gpu->name, ring->id);
527 		DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
528 				gpu->name, fence);
529 		DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
530 				gpu->name, ring->fctx->last_fence);
531 
532 		kthread_queue_work(gpu->worker, &gpu->recover_work);
533 	}
534 
535 	/* if still more pending work, reset the hangcheck timer: */
536 	if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
537 		hangcheck_timer_reset(gpu);
538 
539 	/* workaround for missing irq: */
540 	msm_gpu_retire(gpu);
541 }
542 
543 /*
544  * Performance Counters:
545  */
546 
547 /* called under perf_lock */
update_hw_cntrs(struct msm_gpu * gpu,uint32_t ncntrs,uint32_t * cntrs)548 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
549 {
550 	uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
551 	int i, n = min(ncntrs, gpu->num_perfcntrs);
552 
553 	/* read current values: */
554 	for (i = 0; i < gpu->num_perfcntrs; i++)
555 		current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
556 
557 	/* update cntrs: */
558 	for (i = 0; i < n; i++)
559 		cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
560 
561 	/* save current values: */
562 	for (i = 0; i < gpu->num_perfcntrs; i++)
563 		gpu->last_cntrs[i] = current_cntrs[i];
564 
565 	return n;
566 }
567 
update_sw_cntrs(struct msm_gpu * gpu)568 static void update_sw_cntrs(struct msm_gpu *gpu)
569 {
570 	ktime_t time;
571 	uint32_t elapsed;
572 	unsigned long flags;
573 
574 	spin_lock_irqsave(&gpu->perf_lock, flags);
575 	if (!gpu->perfcntr_active)
576 		goto out;
577 
578 	time = ktime_get();
579 	elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
580 
581 	gpu->totaltime += elapsed;
582 	if (gpu->last_sample.active)
583 		gpu->activetime += elapsed;
584 
585 	gpu->last_sample.active = msm_gpu_active(gpu);
586 	gpu->last_sample.time = time;
587 
588 out:
589 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
590 }
591 
msm_gpu_perfcntr_start(struct msm_gpu * gpu)592 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
593 {
594 	unsigned long flags;
595 
596 	pm_runtime_get_sync(&gpu->pdev->dev);
597 
598 	spin_lock_irqsave(&gpu->perf_lock, flags);
599 	/* we could dynamically enable/disable perfcntr registers too.. */
600 	gpu->last_sample.active = msm_gpu_active(gpu);
601 	gpu->last_sample.time = ktime_get();
602 	gpu->activetime = gpu->totaltime = 0;
603 	gpu->perfcntr_active = true;
604 	update_hw_cntrs(gpu, 0, NULL);
605 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
606 }
607 
msm_gpu_perfcntr_stop(struct msm_gpu * gpu)608 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
609 {
610 	gpu->perfcntr_active = false;
611 	pm_runtime_put_sync(&gpu->pdev->dev);
612 }
613 
614 /* returns -errno or # of cntrs sampled */
msm_gpu_perfcntr_sample(struct msm_gpu * gpu,uint32_t * activetime,uint32_t * totaltime,uint32_t ncntrs,uint32_t * cntrs)615 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
616 		uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
617 {
618 	unsigned long flags;
619 	int ret;
620 
621 	spin_lock_irqsave(&gpu->perf_lock, flags);
622 
623 	if (!gpu->perfcntr_active) {
624 		ret = -EINVAL;
625 		goto out;
626 	}
627 
628 	*activetime = gpu->activetime;
629 	*totaltime = gpu->totaltime;
630 
631 	gpu->activetime = gpu->totaltime = 0;
632 
633 	ret = update_hw_cntrs(gpu, ncntrs, cntrs);
634 
635 out:
636 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
637 
638 	return ret;
639 }
640 
641 /*
642  * Cmdstream submission/retirement:
643  */
644 
retire_submit(struct msm_gpu * gpu,struct msm_ringbuffer * ring,struct msm_gem_submit * submit)645 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
646 		struct msm_gem_submit *submit)
647 {
648 	int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
649 	volatile struct msm_gpu_submit_stats *stats;
650 	u64 elapsed, clock = 0, cycles;
651 	unsigned long flags;
652 
653 	stats = &ring->memptrs->stats[index];
654 	/* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
655 	elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
656 	do_div(elapsed, 192);
657 
658 	cycles = stats->cpcycles_end - stats->cpcycles_start;
659 
660 	/* Calculate the clock frequency from the number of CP cycles */
661 	if (elapsed) {
662 		clock = cycles * 1000;
663 		do_div(clock, elapsed);
664 	}
665 
666 	submit->queue->ctx->elapsed_ns += elapsed;
667 	submit->queue->ctx->cycles     += cycles;
668 
669 	trace_msm_gpu_submit_retired(submit, elapsed, clock,
670 		stats->alwayson_start, stats->alwayson_end);
671 
672 	msm_submit_retire(submit);
673 
674 	pm_runtime_mark_last_busy(&gpu->pdev->dev);
675 
676 	spin_lock_irqsave(&ring->submit_lock, flags);
677 	list_del(&submit->node);
678 	spin_unlock_irqrestore(&ring->submit_lock, flags);
679 
680 	/* Update devfreq on transition from active->idle: */
681 	mutex_lock(&gpu->active_lock);
682 	gpu->active_submits--;
683 	WARN_ON(gpu->active_submits < 0);
684 	if (!gpu->active_submits) {
685 		msm_devfreq_idle(gpu);
686 		pm_runtime_put_autosuspend(&gpu->pdev->dev);
687 	}
688 
689 	mutex_unlock(&gpu->active_lock);
690 
691 	msm_gem_submit_put(submit);
692 }
693 
retire_submits(struct msm_gpu * gpu)694 static void retire_submits(struct msm_gpu *gpu)
695 {
696 	int i;
697 
698 	/* Retire the commits starting with highest priority */
699 	for (i = 0; i < gpu->nr_rings; i++) {
700 		struct msm_ringbuffer *ring = gpu->rb[i];
701 
702 		while (true) {
703 			struct msm_gem_submit *submit = NULL;
704 			unsigned long flags;
705 
706 			spin_lock_irqsave(&ring->submit_lock, flags);
707 			submit = list_first_entry_or_null(&ring->submits,
708 					struct msm_gem_submit, node);
709 			spin_unlock_irqrestore(&ring->submit_lock, flags);
710 
711 			/*
712 			 * If no submit, we are done.  If submit->fence hasn't
713 			 * been signalled, then later submits are not signalled
714 			 * either, so we are also done.
715 			 */
716 			if (submit && dma_fence_is_signaled(submit->hw_fence)) {
717 				retire_submit(gpu, ring, submit);
718 			} else {
719 				break;
720 			}
721 		}
722 	}
723 
724 	wake_up_all(&gpu->retire_event);
725 }
726 
retire_worker(struct kthread_work * work)727 static void retire_worker(struct kthread_work *work)
728 {
729 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
730 
731 	retire_submits(gpu);
732 }
733 
734 /* call from irq handler to schedule work to retire bo's */
msm_gpu_retire(struct msm_gpu * gpu)735 void msm_gpu_retire(struct msm_gpu *gpu)
736 {
737 	int i;
738 
739 	for (i = 0; i < gpu->nr_rings; i++)
740 		msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
741 
742 	kthread_queue_work(gpu->worker, &gpu->retire_work);
743 	update_sw_cntrs(gpu);
744 }
745 
746 /* add bo's to gpu's ring, and kick gpu: */
msm_gpu_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)747 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
748 {
749 	struct msm_ringbuffer *ring = submit->ring;
750 	unsigned long flags;
751 
752 	WARN_ON(!mutex_is_locked(&gpu->lock));
753 
754 	pm_runtime_get_sync(&gpu->pdev->dev);
755 
756 	msm_gpu_hw_init(gpu);
757 
758 	submit->seqno = submit->hw_fence->seqno;
759 
760 	update_sw_cntrs(gpu);
761 
762 	/*
763 	 * ring->submits holds a ref to the submit, to deal with the case
764 	 * that a submit completes before msm_ioctl_gem_submit() returns.
765 	 */
766 	msm_gem_submit_get(submit);
767 
768 	spin_lock_irqsave(&ring->submit_lock, flags);
769 	list_add_tail(&submit->node, &ring->submits);
770 	spin_unlock_irqrestore(&ring->submit_lock, flags);
771 
772 	/* Update devfreq on transition from idle->active: */
773 	mutex_lock(&gpu->active_lock);
774 	if (!gpu->active_submits) {
775 		pm_runtime_get(&gpu->pdev->dev);
776 		msm_devfreq_active(gpu);
777 	}
778 	gpu->active_submits++;
779 	mutex_unlock(&gpu->active_lock);
780 
781 	gpu->funcs->submit(gpu, submit);
782 	gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
783 
784 	pm_runtime_put(&gpu->pdev->dev);
785 	hangcheck_timer_reset(gpu);
786 }
787 
788 /*
789  * Init/Cleanup:
790  */
791 
irq_handler(int irq,void * data)792 static irqreturn_t irq_handler(int irq, void *data)
793 {
794 	struct msm_gpu *gpu = data;
795 	return gpu->funcs->irq(gpu);
796 }
797 
get_clocks(struct platform_device * pdev,struct msm_gpu * gpu)798 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
799 {
800 	int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
801 
802 	if (ret < 1) {
803 		gpu->nr_clocks = 0;
804 		return ret;
805 	}
806 
807 	gpu->nr_clocks = ret;
808 
809 	gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
810 		gpu->nr_clocks, "core");
811 
812 	gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
813 		gpu->nr_clocks, "rbbmtimer");
814 
815 	return 0;
816 }
817 
818 /* Return a new address space for a msm_drm_private instance */
819 struct msm_gem_address_space *
msm_gpu_create_private_address_space(struct msm_gpu * gpu,struct task_struct * task)820 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
821 {
822 	struct msm_gem_address_space *aspace = NULL;
823 	if (!gpu)
824 		return NULL;
825 
826 	/*
827 	 * If the target doesn't support private address spaces then return
828 	 * the global one
829 	 */
830 	if (gpu->funcs->create_private_address_space) {
831 		aspace = gpu->funcs->create_private_address_space(gpu);
832 		if (!IS_ERR(aspace))
833 			aspace->pid = get_pid(task_pid(task));
834 	}
835 
836 	if (IS_ERR_OR_NULL(aspace))
837 		aspace = msm_gem_address_space_get(gpu->aspace);
838 
839 	return aspace;
840 }
841 
msm_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct msm_gpu * gpu,const struct msm_gpu_funcs * funcs,const char * name,struct msm_gpu_config * config)842 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
843 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
844 		const char *name, struct msm_gpu_config *config)
845 {
846 	struct msm_drm_private *priv = drm->dev_private;
847 	int i, ret, nr_rings = config->nr_rings;
848 	void *memptrs;
849 	uint64_t memptrs_iova;
850 
851 	if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
852 		gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
853 
854 	gpu->dev = drm;
855 	gpu->funcs = funcs;
856 	gpu->name = name;
857 
858 	gpu->worker = kthread_create_worker(0, "gpu-worker");
859 	if (IS_ERR(gpu->worker)) {
860 		ret = PTR_ERR(gpu->worker);
861 		gpu->worker = NULL;
862 		goto fail;
863 	}
864 
865 	sched_set_fifo_low(gpu->worker->task);
866 
867 	mutex_init(&gpu->active_lock);
868 	mutex_init(&gpu->lock);
869 	init_waitqueue_head(&gpu->retire_event);
870 	kthread_init_work(&gpu->retire_work, retire_worker);
871 	kthread_init_work(&gpu->recover_work, recover_worker);
872 	kthread_init_work(&gpu->fault_work, fault_worker);
873 
874 	priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
875 
876 	/*
877 	 * If progress detection is supported, halve the hangcheck timer
878 	 * duration, as it takes two iterations of the hangcheck handler
879 	 * to detect a hang.
880 	 */
881 	if (funcs->progress)
882 		priv->hangcheck_period /= 2;
883 
884 	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
885 
886 	spin_lock_init(&gpu->perf_lock);
887 
888 
889 	/* Map registers: */
890 	gpu->mmio = msm_ioremap(pdev, config->ioname);
891 	if (IS_ERR(gpu->mmio)) {
892 		ret = PTR_ERR(gpu->mmio);
893 		goto fail;
894 	}
895 
896 	/* Get Interrupt: */
897 	gpu->irq = platform_get_irq(pdev, 0);
898 	if (gpu->irq < 0) {
899 		ret = gpu->irq;
900 		goto fail;
901 	}
902 
903 	ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
904 			IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
905 	if (ret) {
906 		DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
907 		goto fail;
908 	}
909 
910 	ret = get_clocks(pdev, gpu);
911 	if (ret)
912 		goto fail;
913 
914 	gpu->ebi1_clk = msm_clk_get(pdev, "bus");
915 	DBG("ebi1_clk: %p", gpu->ebi1_clk);
916 	if (IS_ERR(gpu->ebi1_clk))
917 		gpu->ebi1_clk = NULL;
918 
919 	/* Acquire regulators: */
920 	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
921 	DBG("gpu_reg: %p", gpu->gpu_reg);
922 	if (IS_ERR(gpu->gpu_reg))
923 		gpu->gpu_reg = NULL;
924 
925 	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
926 	DBG("gpu_cx: %p", gpu->gpu_cx);
927 	if (IS_ERR(gpu->gpu_cx))
928 		gpu->gpu_cx = NULL;
929 
930 	platform_set_drvdata(pdev, &gpu->adreno_smmu);
931 
932 	msm_devfreq_init(gpu);
933 
934 
935 	gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
936 
937 	if (gpu->aspace == NULL)
938 		DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
939 	else if (IS_ERR(gpu->aspace)) {
940 		ret = PTR_ERR(gpu->aspace);
941 		goto fail;
942 	}
943 
944 	memptrs = msm_gem_kernel_new(drm,
945 		sizeof(struct msm_rbmemptrs) * nr_rings,
946 		check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
947 		&memptrs_iova);
948 
949 	if (IS_ERR(memptrs)) {
950 		ret = PTR_ERR(memptrs);
951 		DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
952 		goto fail;
953 	}
954 
955 	msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
956 
957 	if (nr_rings > ARRAY_SIZE(gpu->rb)) {
958 		DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
959 			ARRAY_SIZE(gpu->rb));
960 		nr_rings = ARRAY_SIZE(gpu->rb);
961 	}
962 
963 	/* Create ringbuffer(s): */
964 	for (i = 0; i < nr_rings; i++) {
965 		gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
966 
967 		if (IS_ERR(gpu->rb[i])) {
968 			ret = PTR_ERR(gpu->rb[i]);
969 			DRM_DEV_ERROR(drm->dev,
970 				"could not create ringbuffer %d: %d\n", i, ret);
971 			goto fail;
972 		}
973 
974 		memptrs += sizeof(struct msm_rbmemptrs);
975 		memptrs_iova += sizeof(struct msm_rbmemptrs);
976 	}
977 
978 	gpu->nr_rings = nr_rings;
979 
980 	refcount_set(&gpu->sysprof_active, 1);
981 
982 	return 0;
983 
984 fail:
985 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
986 		msm_ringbuffer_destroy(gpu->rb[i]);
987 		gpu->rb[i] = NULL;
988 	}
989 
990 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
991 
992 	platform_set_drvdata(pdev, NULL);
993 	return ret;
994 }
995 
msm_gpu_cleanup(struct msm_gpu * gpu)996 void msm_gpu_cleanup(struct msm_gpu *gpu)
997 {
998 	int i;
999 
1000 	DBG("%s", gpu->name);
1001 
1002 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1003 		msm_ringbuffer_destroy(gpu->rb[i]);
1004 		gpu->rb[i] = NULL;
1005 	}
1006 
1007 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
1008 
1009 	if (!IS_ERR_OR_NULL(gpu->aspace)) {
1010 		gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1011 		msm_gem_address_space_put(gpu->aspace);
1012 	}
1013 
1014 	if (gpu->worker) {
1015 		kthread_destroy_worker(gpu->worker);
1016 	}
1017 
1018 	msm_devfreq_cleanup(gpu);
1019 
1020 	platform_set_drvdata(gpu->pdev, NULL);
1021 }
1022