xref: /openbmc/linux/arch/arm64/boot/dts/sprd/whale2.dtsi (revision f028328f)
1/*
2 * Spreadtrum Whale2 platform peripherals
3 *
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9#include <dt-bindings/clock/sprd,sc9860-clk.h>
10
11/ {
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	soc: soc {
17		compatible = "simple-bus";
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21
22		ap_ahb_regs: syscon@20210000 {
23			compatible = "syscon";
24			reg = <0 0x20210000 0 0x10000>;
25		};
26
27		pmu_regs: syscon@402b0000 {
28			compatible = "syscon";
29			reg = <0 0x402b0000 0 0x10000>;
30		};
31
32		aon_regs: syscon@402e0000 {
33			compatible = "syscon";
34			reg = <0 0x402e0000 0 0x10000>;
35		};
36
37		ana_regs: syscon@40400000 {
38			compatible = "syscon";
39			reg = <0 0x40400000 0 0x10000>;
40		};
41
42		agcp_regs: syscon@415e0000 {
43			compatible = "syscon";
44			reg = <0 0x415e0000 0 0x1000000>;
45		};
46
47		vsp_regs: syscon@61100000 {
48			compatible = "syscon";
49			reg = <0 0x61100000 0 0x10000>;
50		};
51
52		cam_regs: syscon@62100000 {
53			compatible = "syscon";
54			reg = <0 0x62100000 0 0x10000>;
55		};
56
57		disp_regs: syscon@63100000 {
58			compatible = "syscon";
59			reg = <0 0x63100000 0 0x10000>;
60		};
61
62		ap_apb_regs: syscon@70b00000 {
63			compatible = "syscon";
64			reg = <0 0x70b00000 0 0x40000>;
65		};
66
67		ap-apb {
68			compatible = "simple-bus";
69			#address-cells = <1>;
70			#size-cells = <1>;
71			ranges = <0 0x0 0x70000000 0x10000000>;
72
73			uart0: serial@0 {
74				compatible = "sprd,sc9860-uart",
75					     "sprd,sc9836-uart";
76				reg = <0x0 0x100>;
77				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
78				clock-names = "enable", "uart", "source";
79				clocks = <&apapb_gate CLK_UART0_EB>,
80				       <&ap_clk CLK_UART0>, <&ext_26m>;
81				status = "disabled";
82			};
83
84			uart1: serial@100000 {
85				compatible = "sprd,sc9860-uart",
86					     "sprd,sc9836-uart";
87				reg = <0x100000 0x100>;
88				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
89				clock-names = "enable", "uart", "source";
90				clocks = <&apapb_gate CLK_UART1_EB>,
91				       <&ap_clk CLK_UART1>, <&ext_26m>;
92				status = "disabled";
93			};
94
95			uart2: serial@200000 {
96				compatible = "sprd,sc9860-uart",
97					     "sprd,sc9836-uart";
98				reg = <0x200000 0x100>;
99				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
100				clock-names = "enable", "uart", "source";
101				clocks = <&apapb_gate CLK_UART2_EB>,
102				       <&ap_clk CLK_UART2>, <&ext_26m>;
103				status = "disabled";
104			};
105
106			uart3: serial@300000 {
107				compatible = "sprd,sc9860-uart",
108					     "sprd,sc9836-uart";
109				reg = <0x300000 0x100>;
110				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
111				clock-names = "enable", "uart", "source";
112				clocks = <&apapb_gate CLK_UART3_EB>,
113				       <&ap_clk CLK_UART3>, <&ext_26m>;
114				status = "disabled";
115			};
116		};
117
118		ap-ahb {
119			compatible = "simple-bus";
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges;
123
124			ap_dma: dma-controller@20100000 {
125				compatible = "sprd,sc9860-dma";
126				reg = <0 0x20100000 0 0x4000>;
127				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
128				#dma-cells = <1>;
129				/* For backwards compatibility: */
130				#dma-channels = <32>;
131				dma-channels = <32>;
132				clock-names = "enable";
133				clocks = <&apahb_gate CLK_DMA_EB>;
134			};
135
136			sdio3: sdio@50430000 {
137				compatible = "sprd,sdhci-r11";
138				reg = <0 0x50430000 0 0x1000>;
139				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
140
141				clock-names = "sdio", "enable", "2x_enable";
142				clocks = <&aon_prediv CLK_EMMC_2X>,
143				       <&apahb_gate CLK_EMMC_EB>,
144				       <&aon_gate CLK_EMMC_2X_EN>;
145				assigned-clocks = <&aon_prediv CLK_EMMC_2X>;
146				assigned-clock-parents = <&clk_l0_409m6>;
147
148				sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
149				sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
150				sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
151				sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
152				vmmc-supply = <&vddemmccore>;
153				bus-width = <8>;
154				non-removable;
155				no-sdio;
156				no-sd;
157				cap-mmc-hw-reset;
158				mmc-hs400-enhanced-strobe;
159				mmc-hs400-1_8v;
160				mmc-hs200-1_8v;
161				mmc-ddr-1_8v;
162			};
163		};
164
165		aon {
166			compatible = "simple-bus";
167			#address-cells = <2>;
168			#size-cells = <2>;
169			ranges;
170
171			adi_bus: spi@40030000 {
172				compatible = "sprd,sc9860-adi";
173				reg = <0 0x40030000 0 0x10000>;
174				hwlocks = <&hwlock 0>;
175				hwlock-names = "adi";
176				#address-cells = <1>;
177				#size-cells = <0>;
178			};
179
180			timer@40050000 {
181				compatible = "sprd,sc9860-timer";
182				reg = <0 0x40050000 0 0x20>;
183				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
184				clocks = <&ext_32k>;
185			};
186
187			timer@40050020 {
188				compatible = "sprd,sc9860-suspend-timer";
189				reg = <0 0x40050020 0 0x20>;
190				clocks = <&ext_32k>;
191			};
192
193			hwlock: hwspinlock@40500000 {
194				compatible = "sprd,hwspinlock-r3p0";
195				reg = <0 0x40500000 0 0x1000>;
196				#hwlock-cells = <1>;
197				clock-names = "enable";
198				clocks = <&aon_gate CLK_SPLK_EB>;
199			};
200
201			eic_debounce: gpio@40210000 {
202				compatible = "sprd,sc9860-eic-debounce";
203				reg = <0 0x40210000 0 0x80>;
204				gpio-controller;
205				#gpio-cells = <2>;
206				interrupt-controller;
207				#interrupt-cells = <2>;
208				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209			};
210
211			eic_latch: gpio@40210080 {
212				compatible = "sprd,sc9860-eic-latch";
213				reg = <0 0x40210080 0 0x20>;
214				gpio-controller;
215				#gpio-cells = <2>;
216				interrupt-controller;
217				#interrupt-cells = <2>;
218				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
219			};
220
221			eic_async: gpio@402100a0 {
222				compatible = "sprd,sc9860-eic-async";
223				reg = <0 0x402100a0 0 0x20>;
224				gpio-controller;
225				#gpio-cells = <2>;
226				interrupt-controller;
227				#interrupt-cells = <2>;
228				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
229			};
230
231			eic_sync: gpio@402100c0 {
232				compatible = "sprd,sc9860-eic-sync";
233				reg = <0 0x402100c0 0 0x20>;
234				gpio-controller;
235				#gpio-cells = <2>;
236				interrupt-controller;
237				#interrupt-cells = <2>;
238				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
239			};
240
241			ap_gpio: gpio@40280000 {
242				compatible = "sprd,sc9860-gpio";
243				reg = <0 0x40280000 0 0x1000>;
244				gpio-controller;
245				#gpio-cells = <2>;
246				interrupt-controller;
247				#interrupt-cells = <2>;
248				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
249			};
250
251			pin_controller: pinctrl@402a0000 {
252				compatible = "sprd,sc9860-pinctrl";
253				reg = <0 0x402a0000 0 0x10000>;
254			};
255
256			watchdog@40310000 {
257				compatible = "sprd,sp9860-wdt";
258				reg = <0 0x40310000 0 0x1000>;
259				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
260				timeout-sec = <12>;
261				clock-names = "enable", "rtc_enable";
262				clocks = <&aon_gate CLK_APCPU_WDG_EB>,
263				       <&aon_gate CLK_AP_WDG_RTC_EB>;
264			};
265		};
266
267		agcp {
268			compatible = "simple-bus";
269			#address-cells = <2>;
270			#size-cells = <2>;
271			ranges;
272
273			agcp_dma: dma-controller@41580000 {
274				compatible = "sprd,sc9860-dma";
275				reg = <0 0x41580000 0 0x4000>;
276				#dma-cells = <1>;
277				/* For backwards compatibility: */
278				#dma-channels = <32>;
279				dma-channels = <32>;
280				clock-names = "enable", "ashb_eb";
281				clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
282				       <&agcp_gate CLK_AGCP_AP_ASHB_EB>;
283			};
284		};
285	};
286
287	ext_32k: ext_32k {
288		compatible = "fixed-clock";
289		#clock-cells = <0>;
290		clock-frequency = <32768>;
291		clock-output-names = "ext-32k";
292	};
293
294	ext_26m: ext_26m {
295		compatible = "fixed-clock";
296		#clock-cells = <0>;
297		clock-frequency = <26000000>;
298		clock-output-names = "ext-26m";
299	};
300
301	ext_rco_100m: ext_rco_100m {
302		compatible = "fixed-clock";
303		#clock-cells = <0>;
304		clock-frequency = <100000000>;
305		clock-output-names = "ext-rco-100m";
306	};
307
308	clk_l0_409m6: clk_l0_409m6 {
309		compatible = "fixed-clock";
310		#clock-cells = <0>;
311		clock-frequency = <409600000>;
312		clock-output-names = "ext-409m6";
313	};
314};
315