1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2008 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <fsl_ddr_sdram.h>
8 
9 #include <fsl_ddr.h>
10 
11 /*
12  * Calculate the Density of each Physical Rank.
13  * Returned size is in bytes.
14  *
15  * Study these table from Byte 31 of JEDEC SPD Spec.
16  *
17  *		DDR I	DDR II
18  *	Bit	Size	Size
19  *	---	-----	------
20  *	7 high	512MB	512MB
21  *	6	256MB	256MB
22  *	5	128MB	128MB
23  *	4	 64MB	 16GB
24  *	3	 32MB	  8GB
25  *	2	 16MB	  4GB
26  *	1	  2GB	  2GB
27  *	0 low	  1GB	  1GB
28  *
29  * Reorder Table to be linear by stripping the bottom
30  * 2 or 5 bits off and shifting them up to the top.
31  */
32 
33 static unsigned long long
compute_ranksize(unsigned int mem_type,unsigned char row_dens)34 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
35 {
36 	unsigned long long bsize;
37 
38 	/* Bottom 2 bits up to the top. */
39 	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
40 	bsize <<= 24ULL;
41 	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
42 
43 	return bsize;
44 }
45 
46 /*
47  * Convert a two-nibble BCD value into a cycle time.
48  * While the spec calls for nano-seconds, picos are returned.
49  *
50  * This implements the tables for bytes 9, 23 and 25 for both
51  * DDR I and II.  No allowance for distinguishing the invalid
52  * fields absent for DDR I yet present in DDR II is made.
53  * (That is, cycle times of .25, .33, .66 and .75 ns are
54  * allowed for both DDR II and I.)
55  */
56 static unsigned int
convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)57 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
58 {
59 	/* Table look up the lower nibble, allow DDR I & II. */
60 	unsigned int tenths_ps[16] = {
61 		0,
62 		100,
63 		200,
64 		300,
65 		400,
66 		500,
67 		600,
68 		700,
69 		800,
70 		900,
71 		250,	/* This and the next 3 entries valid ... */
72 		330,	/* ...  only for tCK calculations. */
73 		660,
74 		750,
75 		0,	/* undefined */
76 		0	/* undefined */
77 	};
78 
79 	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
80 	unsigned int tenth_ns = spd_val & 0x0F;
81 	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
82 
83 	return ps;
84 }
85 
86 static unsigned int
convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)87 convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
88 {
89 	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
90 	unsigned int hundredth_ns = spd_val & 0x0F;
91 	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
92 
93 	return ps;
94 }
95 
96 static unsigned int byte40_table_ps[8] = {
97 	0,
98 	250,
99 	330,
100 	500,
101 	660,
102 	750,
103 	0,	/* supposed to be RFC, but not sure what that means */
104 	0	/* Undefined */
105 };
106 
107 static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext,unsigned char trfc)108 compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
109 {
110 	return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
111 		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
112 }
113 
114 static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext,unsigned char trc)115 compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
116 {
117 	return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
118 }
119 
120 /*
121  * tCKmax from DDR I SPD Byte 43
122  *
123  * Bits 7:2 == whole ns
124  * Bits 1:0 == quarter ns
125  *    00    == 0.00 ns
126  *    01    == 0.25 ns
127  *    10    == 0.50 ns
128  *    11    == 0.75 ns
129  *
130  * Returns picoseconds.
131  */
132 static unsigned int
compute_tckmax_from_spd_ps(unsigned int byte43)133 compute_tckmax_from_spd_ps(unsigned int byte43)
134 {
135 	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
136 }
137 
138 /*
139  * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
140  * Table from SPD Spec, Byte 12, converted to picoseconds and
141  * filled in with "default" normal values.
142  */
143 static unsigned int
determine_refresh_rate_ps(const unsigned int spd_refresh)144 determine_refresh_rate_ps(const unsigned int spd_refresh)
145 {
146 	unsigned int refresh_time_ps[8] = {
147 		15625000,	/* 0 Normal    1.00x */
148 		3900000,	/* 1 Reduced    .25x */
149 		7800000,	/* 2 Extended   .50x */
150 		31300000,	/* 3 Extended  2.00x */
151 		62500000,	/* 4 Extended  4.00x */
152 		125000000,	/* 5 Extended  8.00x */
153 		15625000,	/* 6 Normal    1.00x  filler */
154 		15625000,	/* 7 Normal    1.00x  filler */
155 	};
156 
157 	return refresh_time_ps[spd_refresh & 0x7];
158 }
159 
160 /*
161  * The purpose of this function is to compute a suitable
162  * CAS latency given the DRAM clock period.  The SPD only
163  * defines at most 3 CAS latencies.  Typically the slower in
164  * frequency the DIMM runs at, the shorter its CAS latency can be.
165  * If the DIMM is operating at a sufficiently low frequency,
166  * it may be able to run at a CAS latency shorter than the
167  * shortest SPD-defined CAS latency.
168  *
169  * If a CAS latency is not found, 0 is returned.
170  *
171  * Do this by finding in the standard speed bin table the longest
172  * tCKmin that doesn't exceed the value of mclk_ps (tCK).
173  *
174  * An assumption made is that the SDRAM device allows the
175  * CL to be programmed for a value that is lower than those
176  * advertised by the SPD.  This is not always the case,
177  * as those modes not defined in the SPD are optional.
178  *
179  * CAS latency de-rating based upon values JEDEC Standard No. 79-E
180  * Table 11.
181  *
182  * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
183  */
184 				  /*   CL2.0 CL2.5 CL3.0  */
185 unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
186 
187 unsigned int
compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)188 compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
189 {
190 	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
191 	unsigned int lowest_tCKmin_found = 0;
192 	unsigned int lowest_tCKmin_CL = 0;
193 	unsigned int i;
194 
195 	debug("mclk_ps = %u\n", mclk_ps);
196 
197 	for (i = 0; i < num_speed_bins; i++) {
198 		unsigned int x = ddr1_speed_bins[i];
199 		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
200 		      i, x, lowest_tCKmin_found);
201 		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
202 			lowest_tCKmin_found = x;
203 			lowest_tCKmin_CL = i + 1;
204 		}
205 	}
206 
207 	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
208 
209 	return lowest_tCKmin_CL;
210 }
211 
212 /*
213  * ddr_compute_dimm_parameters for DDR1 SPD
214  *
215  * Compute DIMM parameters based upon the SPD information in spd.
216  * Writes the results to the dimm_params_t structure pointed by pdimm.
217  *
218  * FIXME: use #define for the retvals
219  */
ddr_compute_dimm_parameters(const unsigned int ctrl_num,const ddr1_spd_eeprom_t * spd,dimm_params_t * pdimm,unsigned int dimm_number)220 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
221 					 const ddr1_spd_eeprom_t *spd,
222 					 dimm_params_t *pdimm,
223 					 unsigned int dimm_number)
224 {
225 	unsigned int retval;
226 
227 	if (spd->mem_type) {
228 		if (spd->mem_type != SPD_MEMTYPE_DDR) {
229 			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
230 			return 1;
231 		}
232 	} else {
233 		memset(pdimm, 0, sizeof(dimm_params_t));
234 		return 1;
235 	}
236 
237 	retval = ddr1_spd_check(spd);
238 	if (retval) {
239 		printf("DIMM %u: failed checksum\n", dimm_number);
240 		return 2;
241 	}
242 
243 	/*
244 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
245 	 * Guarantee null termination here by presetting all bytes to 0
246 	 * and copying the part name in ASCII from the SPD onto it
247 	 */
248 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
249 	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
250 
251 	/* DIMM organization parameters */
252 	pdimm->n_ranks = spd->nrows;
253 	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
254 	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
255 	pdimm->data_width = spd->dataw_lsb;
256 	pdimm->primary_sdram_width = spd->primw;
257 	pdimm->ec_sdram_width = spd->ecw;
258 
259 	/*
260 	 * FIXME: Need to determine registered_dimm status.
261 	 *     1 == register buffered
262 	 *     0 == unbuffered
263 	 */
264 	pdimm->registered_dimm = 0;	/* unbuffered */
265 
266 	/* SDRAM device parameters */
267 	pdimm->n_row_addr = spd->nrow_addr;
268 	pdimm->n_col_addr = spd->ncol_addr;
269 	pdimm->n_banks_per_sdram_device = spd->nbanks;
270 	pdimm->edc_config = spd->config;
271 	pdimm->burst_lengths_bitmask = spd->burstl;
272 
273 	/*
274 	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
275 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
276 	 * nanoseconds and represented as BCD.
277 	 */
278 	pdimm->tckmin_x_ps
279 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
280 	pdimm->tckmin_x_minus_1_ps
281 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
282 	pdimm->tckmin_x_minus_2_ps
283 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
284 
285 	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
286 
287 	/*
288 	 * Compute CAS latencies defined by SPD
289 	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
290 	 *
291 	 * If cas_lat after masking is 0, the __ilog2 function returns
292 	 * 255 into the variable.   This behavior is abused once.
293 	 */
294 	pdimm->caslat_x  = __ilog2(spd->cas_lat);
295 	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
296 					  & ~(1 << pdimm->caslat_x));
297 	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
298 					  & ~(1 << pdimm->caslat_x)
299 					  & ~(1 << pdimm->caslat_x_minus_1));
300 
301 	/* Compute CAS latencies below that defined by SPD */
302 	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
303 					get_memory_clk_period_ps(ctrl_num));
304 
305 	/* Compute timing parameters */
306 	pdimm->trcd_ps = spd->trcd * 250;
307 	pdimm->trp_ps = spd->trp * 250;
308 	pdimm->tras_ps = spd->tras * 1000;
309 
310 	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
311 	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
312 	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
313 
314 	pdimm->trrd_ps = spd->trrd * 250;
315 	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
316 
317 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
318 
319 	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
320 	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
321 	pdimm->tds_ps
322 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
323 	pdimm->tdh_ps
324 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
325 
326 	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
327 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
328 	pdimm->tqhs_ps = spd->tqhs * 10;
329 
330 	return 0;
331 }
332