xref: /openbmc/linux/drivers/mmc/host/mtk-sd.c (revision c1b17191)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27 
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35 
36 #include "cqhci.h"
37 
38 #define MAX_BD_NUM          1024
39 #define MSDC_NR_CLOCKS      3
40 
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition                                                        */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS          0x0
45 #define MSDC_BUS_4BITS          0x1
46 #define MSDC_BUS_8BITS          0x2
47 
48 #define MSDC_BURST_64B          0x6
49 
50 /*--------------------------------------------------------------------------*/
51 /* Register Offset                                                          */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_CFG         0x0
54 #define MSDC_IOCON       0x04
55 #define MSDC_PS          0x08
56 #define MSDC_INT         0x0c
57 #define MSDC_INTEN       0x10
58 #define MSDC_FIFOCS      0x14
59 #define SDC_CFG          0x30
60 #define SDC_CMD          0x34
61 #define SDC_ARG          0x38
62 #define SDC_STS          0x3c
63 #define SDC_RESP0        0x40
64 #define SDC_RESP1        0x44
65 #define SDC_RESP2        0x48
66 #define SDC_RESP3        0x4c
67 #define SDC_BLK_NUM      0x50
68 #define SDC_ADV_CFG0     0x64
69 #define EMMC_IOCON       0x7c
70 #define SDC_ACMD_RESP    0x80
71 #define DMA_SA_H4BIT     0x8c
72 #define MSDC_DMA_SA      0x90
73 #define MSDC_DMA_CTRL    0x98
74 #define MSDC_DMA_CFG     0x9c
75 #define MSDC_PATCH_BIT   0xb0
76 #define MSDC_PATCH_BIT1  0xb4
77 #define MSDC_PATCH_BIT2  0xb8
78 #define MSDC_PAD_TUNE    0xec
79 #define MSDC_PAD_TUNE0   0xf0
80 #define PAD_DS_TUNE      0x188
81 #define PAD_CMD_TUNE     0x18c
82 #define EMMC51_CFG0	 0x204
83 #define EMMC50_CFG0      0x208
84 #define EMMC50_CFG1      0x20c
85 #define EMMC50_CFG3      0x220
86 #define SDC_FIFO_CFG     0x228
87 #define CQHCI_SETTING	 0x7fc
88 
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset                                                  */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL	0x00
93 #define EMMC_TOP_CMD		0x04
94 #define EMMC50_PAD_DS_TUNE	0x0c
95 
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask                                                            */
98 /*--------------------------------------------------------------------------*/
99 
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE           BIT(0)	/* RW */
102 #define MSDC_CFG_CKPDN          BIT(1)	/* RW */
103 #define MSDC_CFG_RST            BIT(2)	/* RW */
104 #define MSDC_CFG_PIO            BIT(3)	/* RW */
105 #define MSDC_CFG_CKDRVEN        BIT(4)	/* RW */
106 #define MSDC_CFG_BV18SDT        BIT(5)	/* RW */
107 #define MSDC_CFG_BV18PSS        BIT(6)	/* R  */
108 #define MSDC_CFG_CKSTB          BIT(7)	/* R  */
109 #define MSDC_CFG_CKDIV          GENMASK(15, 8)	/* RW */
110 #define MSDC_CFG_CKMOD          GENMASK(17, 16)	/* RW */
111 #define MSDC_CFG_HS400_CK_MODE  BIT(18)	/* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)	/* RW */
113 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)	/* RW */
114 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20)	/* RW */
115 
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS    BIT(0)	/* RW */
118 #define MSDC_IOCON_RSPL         BIT(1)	/* RW */
119 #define MSDC_IOCON_DSPL         BIT(2)	/* RW */
120 #define MSDC_IOCON_DDLSEL       BIT(3)	/* RW */
121 #define MSDC_IOCON_DDR50CKD     BIT(4)	/* RW */
122 #define MSDC_IOCON_DSPLSEL      BIT(5)	/* RW */
123 #define MSDC_IOCON_W_DSPL       BIT(8)	/* RW */
124 #define MSDC_IOCON_D0SPL        BIT(16)	/* RW */
125 #define MSDC_IOCON_D1SPL        BIT(17)	/* RW */
126 #define MSDC_IOCON_D2SPL        BIT(18)	/* RW */
127 #define MSDC_IOCON_D3SPL        BIT(19)	/* RW */
128 #define MSDC_IOCON_D4SPL        BIT(20)	/* RW */
129 #define MSDC_IOCON_D5SPL        BIT(21)	/* RW */
130 #define MSDC_IOCON_D6SPL        BIT(22)	/* RW */
131 #define MSDC_IOCON_D7SPL        BIT(23)	/* RW */
132 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24)	/* RW */
133 
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN            BIT(0)	/* RW */
136 #define MSDC_PS_CDSTS           BIT(1)	/* R  */
137 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12)	/* RW */
138 #define MSDC_PS_DAT             GENMASK(23, 16)	/* R  */
139 #define MSDC_PS_DATA1           BIT(17)	/* R  */
140 #define MSDC_PS_CMD             BIT(24)	/* R  */
141 #define MSDC_PS_WP              BIT(31)	/* R  */
142 
143 /* MSDC_INT mask */
144 #define MSDC_INT_MMCIRQ         BIT(0)	/* W1C */
145 #define MSDC_INT_CDSC           BIT(1)	/* W1C */
146 #define MSDC_INT_ACMDRDY        BIT(3)	/* W1C */
147 #define MSDC_INT_ACMDTMO        BIT(4)	/* W1C */
148 #define MSDC_INT_ACMDCRCERR     BIT(5)	/* W1C */
149 #define MSDC_INT_DMAQ_EMPTY     BIT(6)	/* W1C */
150 #define MSDC_INT_SDIOIRQ        BIT(7)	/* W1C */
151 #define MSDC_INT_CMDRDY         BIT(8)	/* W1C */
152 #define MSDC_INT_CMDTMO         BIT(9)	/* W1C */
153 #define MSDC_INT_RSPCRCERR      BIT(10)	/* W1C */
154 #define MSDC_INT_CSTA           BIT(11)	/* R */
155 #define MSDC_INT_XFER_COMPL     BIT(12)	/* W1C */
156 #define MSDC_INT_DXFER_DONE     BIT(13)	/* W1C */
157 #define MSDC_INT_DATTMO         BIT(14)	/* W1C */
158 #define MSDC_INT_DATCRCERR      BIT(15)	/* W1C */
159 #define MSDC_INT_ACMD19_DONE    BIT(16)	/* W1C */
160 #define MSDC_INT_DMA_BDCSERR    BIT(17)	/* W1C */
161 #define MSDC_INT_DMA_GPDCSERR   BIT(18)	/* W1C */
162 #define MSDC_INT_DMA_PROTECT    BIT(19)	/* W1C */
163 #define MSDC_INT_CMDQ           BIT(28)	/* W1C */
164 
165 /* MSDC_INTEN mask */
166 #define MSDC_INTEN_MMCIRQ       BIT(0)	/* RW */
167 #define MSDC_INTEN_CDSC         BIT(1)	/* RW */
168 #define MSDC_INTEN_ACMDRDY      BIT(3)	/* RW */
169 #define MSDC_INTEN_ACMDTMO      BIT(4)	/* RW */
170 #define MSDC_INTEN_ACMDCRCERR   BIT(5)	/* RW */
171 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)	/* RW */
172 #define MSDC_INTEN_SDIOIRQ      BIT(7)	/* RW */
173 #define MSDC_INTEN_CMDRDY       BIT(8)	/* RW */
174 #define MSDC_INTEN_CMDTMO       BIT(9)	/* RW */
175 #define MSDC_INTEN_RSPCRCERR    BIT(10)	/* RW */
176 #define MSDC_INTEN_CSTA         BIT(11)	/* RW */
177 #define MSDC_INTEN_XFER_COMPL   BIT(12)	/* RW */
178 #define MSDC_INTEN_DXFER_DONE   BIT(13)	/* RW */
179 #define MSDC_INTEN_DATTMO       BIT(14)	/* RW */
180 #define MSDC_INTEN_DATCRCERR    BIT(15)	/* RW */
181 #define MSDC_INTEN_ACMD19_DONE  BIT(16)	/* RW */
182 #define MSDC_INTEN_DMA_BDCSERR  BIT(17)	/* RW */
183 #define MSDC_INTEN_DMA_GPDCSERR BIT(18)	/* RW */
184 #define MSDC_INTEN_DMA_PROTECT  BIT(19)	/* RW */
185 
186 /* MSDC_FIFOCS mask */
187 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)	/* R */
188 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16)	/* R */
189 #define MSDC_FIFOCS_CLR         BIT(31)	/* RW */
190 
191 /* SDC_CFG mask */
192 #define SDC_CFG_SDIOINTWKUP     BIT(0)	/* RW */
193 #define SDC_CFG_INSWKUP         BIT(1)	/* RW */
194 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
195 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16)	/* RW */
196 #define SDC_CFG_SDIO            BIT(19)	/* RW */
197 #define SDC_CFG_SDIOIDE         BIT(20)	/* RW */
198 #define SDC_CFG_INTATGAP        BIT(21)	/* RW */
199 #define SDC_CFG_DTOC            GENMASK(31, 24)	/* RW */
200 
201 /* SDC_STS mask */
202 #define SDC_STS_SDCBUSY         BIT(0)	/* RW */
203 #define SDC_STS_CMDBUSY         BIT(1)	/* RW */
204 #define SDC_STS_SWR_COMPL       BIT(31)	/* RW */
205 
206 #define SDC_DAT1_IRQ_TRIGGER	BIT(19)	/* RW */
207 /* SDC_ADV_CFG0 mask */
208 #define SDC_RX_ENHANCE_EN	BIT(20)	/* RW */
209 
210 /* DMA_SA_H4BIT mask */
211 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)	/* RW */
212 
213 /* MSDC_DMA_CTRL mask */
214 #define MSDC_DMA_CTRL_START     BIT(0)	/* W */
215 #define MSDC_DMA_CTRL_STOP      BIT(1)	/* W */
216 #define MSDC_DMA_CTRL_RESUME    BIT(2)	/* W */
217 #define MSDC_DMA_CTRL_MODE      BIT(8)	/* RW */
218 #define MSDC_DMA_CTRL_LASTBUF   BIT(10)	/* RW */
219 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12)	/* RW */
220 
221 /* MSDC_DMA_CFG mask */
222 #define MSDC_DMA_CFG_STS        BIT(0)	/* R */
223 #define MSDC_DMA_CFG_DECSEN     BIT(1)	/* RW */
224 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)	/* RW */
225 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13)	/* RW */
226 #define MSDC_DMA_CFG_CS12B16B   BIT(16)	/* RW */
227 
228 /* MSDC_PATCH_BIT mask */
229 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)	/* RW */
230 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
231 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
232 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)	/* RW */
233 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)	/* RW */
234 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)	/* RW */
235 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)	/* RW */
236 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)	/* RW */
237 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)	/* RW */
238 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)	/* RW */
239 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)	/* RW */
240 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)	/* RW */
241 
242 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
243 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
244 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
245 
246 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
247 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
248 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
249 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
250 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
251 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
252 
253 #define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */
256 #define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */
257 #define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */
258 #define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */
259 #define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */
260 #define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */
261 
262 #define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */
263 #define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */
264 #define PAD_DS_TUNE_DLY2	  GENMASK(11, 7)  /* RW */
265 #define PAD_DS_TUNE_DLY3	  GENMASK(16, 12) /* RW */
266 
267 #define PAD_CMD_TUNE_RX_DLY3	  GENMASK(5, 1)   /* RW */
268 
269 /* EMMC51_CFG0 mask */
270 #define CMDQ_RDAT_CNT		  GENMASK(21, 12) /* RW */
271 
272 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
273 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
274 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
275 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
276 
277 /* EMMC50_CFG1 mask */
278 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
279 
280 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
281 
282 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
283 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
284 
285 /* CQHCI_SETTING */
286 #define CQHCI_RD_CMD_WND_SEL	  BIT(14) /* RW */
287 #define CQHCI_WR_CMD_WND_SEL	  BIT(15) /* RW */
288 
289 /* EMMC_TOP_CONTROL mask */
290 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
291 #define DELAY_EN                BIT(1)      /* RW */
292 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
293 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
294 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
295 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
296 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
297 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
298 
299 /* EMMC_TOP_CMD mask */
300 #define PAD_CMD_RXDLY2          GENMASK(4, 0)	/* RW */
301 #define PAD_CMD_RXDLY           GENMASK(9, 5)	/* RW */
302 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)		/* RW */
303 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)		/* RW */
304 #define PAD_CMD_TX_DLY          GENMASK(16, 12)	/* RW */
305 
306 /* EMMC50_PAD_DS_TUNE mask */
307 #define PAD_DS_DLY_SEL		BIT(16)	/* RW */
308 #define PAD_DS_DLY1		GENMASK(14, 10)	/* RW */
309 #define PAD_DS_DLY3		GENMASK(4, 0)	/* RW */
310 
311 #define REQ_CMD_EIO  BIT(0)
312 #define REQ_CMD_TMO  BIT(1)
313 #define REQ_DAT_ERR  BIT(2)
314 #define REQ_STOP_EIO BIT(3)
315 #define REQ_STOP_TMO BIT(4)
316 #define REQ_CMD_BUSY BIT(5)
317 
318 #define MSDC_PREPARE_FLAG BIT(0)
319 #define MSDC_ASYNC_FLAG BIT(1)
320 #define MSDC_MMAP_FLAG BIT(2)
321 
322 #define MTK_MMC_AUTOSUSPEND_DELAY	50
323 #define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
324 #define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
325 
326 #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
327 
328 #define PAD_DELAY_MAX	32 /* PAD delay cells */
329 /*--------------------------------------------------------------------------*/
330 /* Descriptor Structure                                                     */
331 /*--------------------------------------------------------------------------*/
332 struct mt_gpdma_desc {
333 	u32 gpd_info;
334 #define GPDMA_DESC_HWO		BIT(0)
335 #define GPDMA_DESC_BDP		BIT(1)
336 #define GPDMA_DESC_CHECKSUM	GENMASK(15, 8)
337 #define GPDMA_DESC_INT		BIT(16)
338 #define GPDMA_DESC_NEXT_H4	GENMASK(27, 24)
339 #define GPDMA_DESC_PTR_H4	GENMASK(31, 28)
340 	u32 next;
341 	u32 ptr;
342 	u32 gpd_data_len;
343 #define GPDMA_DESC_BUFLEN	GENMASK(15, 0)
344 #define GPDMA_DESC_EXTLEN	GENMASK(23, 16)
345 	u32 arg;
346 	u32 blknum;
347 	u32 cmd;
348 };
349 
350 struct mt_bdma_desc {
351 	u32 bd_info;
352 #define BDMA_DESC_EOL		BIT(0)
353 #define BDMA_DESC_CHECKSUM	GENMASK(15, 8)
354 #define BDMA_DESC_BLKPAD	BIT(17)
355 #define BDMA_DESC_DWPAD		BIT(18)
356 #define BDMA_DESC_NEXT_H4	GENMASK(27, 24)
357 #define BDMA_DESC_PTR_H4	GENMASK(31, 28)
358 	u32 next;
359 	u32 ptr;
360 	u32 bd_data_len;
361 #define BDMA_DESC_BUFLEN	GENMASK(15, 0)
362 #define BDMA_DESC_BUFLEN_EXT	GENMASK(23, 0)
363 };
364 
365 struct msdc_dma {
366 	struct scatterlist *sg;	/* I/O scatter list */
367 	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
368 	struct mt_bdma_desc *bd;		/* pointer to bd array */
369 	dma_addr_t gpd_addr;	/* the physical address of gpd array */
370 	dma_addr_t bd_addr;	/* the physical address of bd array */
371 };
372 
373 struct msdc_save_para {
374 	u32 msdc_cfg;
375 	u32 iocon;
376 	u32 sdc_cfg;
377 	u32 pad_tune;
378 	u32 patch_bit0;
379 	u32 patch_bit1;
380 	u32 patch_bit2;
381 	u32 pad_ds_tune;
382 	u32 pad_cmd_tune;
383 	u32 emmc50_cfg0;
384 	u32 emmc50_cfg3;
385 	u32 sdc_fifo_cfg;
386 	u32 emmc_top_control;
387 	u32 emmc_top_cmd;
388 	u32 emmc50_pad_ds_tune;
389 };
390 
391 struct mtk_mmc_compatible {
392 	u8 clk_div_bits;
393 	bool recheck_sdio_irq;
394 	bool hs400_tune; /* only used for MT8173 */
395 	u32 pad_tune_reg;
396 	bool async_fifo;
397 	bool data_tune;
398 	bool busy_check;
399 	bool stop_clk_fix;
400 	bool enhance_rx;
401 	bool support_64g;
402 	bool use_internal_cd;
403 };
404 
405 struct msdc_tune_para {
406 	u32 iocon;
407 	u32 pad_tune;
408 	u32 pad_cmd_tune;
409 	u32 emmc_top_control;
410 	u32 emmc_top_cmd;
411 };
412 
413 struct msdc_delay_phase {
414 	u8 maxlen;
415 	u8 start;
416 	u8 final_phase;
417 };
418 
419 struct msdc_host {
420 	struct device *dev;
421 	const struct mtk_mmc_compatible *dev_comp;
422 	int cmd_rsp;
423 
424 	spinlock_t lock;
425 	struct mmc_request *mrq;
426 	struct mmc_command *cmd;
427 	struct mmc_data *data;
428 	int error;
429 
430 	void __iomem *base;		/* host base address */
431 	void __iomem *top_base;		/* host top register base address */
432 
433 	struct msdc_dma dma;	/* dma channel */
434 	u64 dma_mask;
435 
436 	u32 timeout_ns;		/* data timeout ns */
437 	u32 timeout_clks;	/* data timeout clks */
438 
439 	struct pinctrl *pinctrl;
440 	struct pinctrl_state *pins_default;
441 	struct pinctrl_state *pins_uhs;
442 	struct pinctrl_state *pins_eint;
443 	struct delayed_work req_timeout;
444 	int irq;		/* host interrupt */
445 	int eint_irq;		/* interrupt from sdio device for waking up system */
446 	struct reset_control *reset;
447 
448 	struct clk *src_clk;	/* msdc source clock */
449 	struct clk *h_clk;      /* msdc h_clk */
450 	struct clk *bus_clk;	/* bus clock which used to access register */
451 	struct clk *src_clk_cg; /* msdc source clock control gate */
452 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
453 	struct clk *crypto_clk; /* msdc crypto clock control gate */
454 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
455 	u32 mclk;		/* mmc subsystem clock frequency */
456 	u32 src_clk_freq;	/* source clock frequency */
457 	unsigned char timing;
458 	bool vqmmc_enabled;
459 	u32 latch_ck;
460 	u32 hs400_ds_delay;
461 	u32 hs400_ds_dly3;
462 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
463 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
464 	bool hs400_cmd_resp_sel_rising;
465 				 /* cmd response sample selection for HS400 */
466 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
467 	bool hs400_tuning;	/* hs400 mode online tuning */
468 	bool internal_cd;	/* Use internal card-detect logic */
469 	bool cqhci;		/* support eMMC hw cmdq */
470 	struct msdc_save_para save_para; /* used when gate HCLK */
471 	struct msdc_tune_para def_tune_para; /* default tune setting */
472 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
473 	struct cqhci_host *cq_host;
474 	u32 cq_ssc1_time;
475 };
476 
477 static const struct mtk_mmc_compatible mt2701_compat = {
478 	.clk_div_bits = 12,
479 	.recheck_sdio_irq = true,
480 	.hs400_tune = false,
481 	.pad_tune_reg = MSDC_PAD_TUNE0,
482 	.async_fifo = true,
483 	.data_tune = true,
484 	.busy_check = false,
485 	.stop_clk_fix = false,
486 	.enhance_rx = false,
487 	.support_64g = false,
488 };
489 
490 static const struct mtk_mmc_compatible mt2712_compat = {
491 	.clk_div_bits = 12,
492 	.recheck_sdio_irq = false,
493 	.hs400_tune = false,
494 	.pad_tune_reg = MSDC_PAD_TUNE0,
495 	.async_fifo = true,
496 	.data_tune = true,
497 	.busy_check = true,
498 	.stop_clk_fix = true,
499 	.enhance_rx = true,
500 	.support_64g = true,
501 };
502 
503 static const struct mtk_mmc_compatible mt6779_compat = {
504 	.clk_div_bits = 12,
505 	.recheck_sdio_irq = false,
506 	.hs400_tune = false,
507 	.pad_tune_reg = MSDC_PAD_TUNE0,
508 	.async_fifo = true,
509 	.data_tune = true,
510 	.busy_check = true,
511 	.stop_clk_fix = true,
512 	.enhance_rx = true,
513 	.support_64g = true,
514 };
515 
516 static const struct mtk_mmc_compatible mt6795_compat = {
517 	.clk_div_bits = 8,
518 	.recheck_sdio_irq = false,
519 	.hs400_tune = true,
520 	.pad_tune_reg = MSDC_PAD_TUNE,
521 	.async_fifo = false,
522 	.data_tune = false,
523 	.busy_check = false,
524 	.stop_clk_fix = false,
525 	.enhance_rx = false,
526 	.support_64g = false,
527 };
528 
529 static const struct mtk_mmc_compatible mt7620_compat = {
530 	.clk_div_bits = 8,
531 	.recheck_sdio_irq = true,
532 	.hs400_tune = false,
533 	.pad_tune_reg = MSDC_PAD_TUNE,
534 	.async_fifo = false,
535 	.data_tune = false,
536 	.busy_check = false,
537 	.stop_clk_fix = false,
538 	.enhance_rx = false,
539 	.use_internal_cd = true,
540 };
541 
542 static const struct mtk_mmc_compatible mt7622_compat = {
543 	.clk_div_bits = 12,
544 	.recheck_sdio_irq = true,
545 	.hs400_tune = false,
546 	.pad_tune_reg = MSDC_PAD_TUNE0,
547 	.async_fifo = true,
548 	.data_tune = true,
549 	.busy_check = true,
550 	.stop_clk_fix = true,
551 	.enhance_rx = true,
552 	.support_64g = false,
553 };
554 
555 static const struct mtk_mmc_compatible mt7986_compat = {
556 	.clk_div_bits = 12,
557 	.recheck_sdio_irq = true,
558 	.hs400_tune = false,
559 	.pad_tune_reg = MSDC_PAD_TUNE0,
560 	.async_fifo = true,
561 	.data_tune = true,
562 	.busy_check = true,
563 	.stop_clk_fix = true,
564 	.enhance_rx = true,
565 	.support_64g = true,
566 };
567 
568 static const struct mtk_mmc_compatible mt8135_compat = {
569 	.clk_div_bits = 8,
570 	.recheck_sdio_irq = true,
571 	.hs400_tune = false,
572 	.pad_tune_reg = MSDC_PAD_TUNE,
573 	.async_fifo = false,
574 	.data_tune = false,
575 	.busy_check = false,
576 	.stop_clk_fix = false,
577 	.enhance_rx = false,
578 	.support_64g = false,
579 };
580 
581 static const struct mtk_mmc_compatible mt8173_compat = {
582 	.clk_div_bits = 8,
583 	.recheck_sdio_irq = true,
584 	.hs400_tune = true,
585 	.pad_tune_reg = MSDC_PAD_TUNE,
586 	.async_fifo = false,
587 	.data_tune = false,
588 	.busy_check = false,
589 	.stop_clk_fix = false,
590 	.enhance_rx = false,
591 	.support_64g = false,
592 };
593 
594 static const struct mtk_mmc_compatible mt8183_compat = {
595 	.clk_div_bits = 12,
596 	.recheck_sdio_irq = false,
597 	.hs400_tune = false,
598 	.pad_tune_reg = MSDC_PAD_TUNE0,
599 	.async_fifo = true,
600 	.data_tune = true,
601 	.busy_check = true,
602 	.stop_clk_fix = true,
603 	.enhance_rx = true,
604 	.support_64g = true,
605 };
606 
607 static const struct mtk_mmc_compatible mt8516_compat = {
608 	.clk_div_bits = 12,
609 	.recheck_sdio_irq = true,
610 	.hs400_tune = false,
611 	.pad_tune_reg = MSDC_PAD_TUNE0,
612 	.async_fifo = true,
613 	.data_tune = true,
614 	.busy_check = true,
615 	.stop_clk_fix = true,
616 };
617 
618 static const struct of_device_id msdc_of_ids[] = {
619 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
620 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
621 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
622 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
623 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
624 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
625 	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
626 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
627 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
628 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
629 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
630 
631 	{}
632 };
633 MODULE_DEVICE_TABLE(of, msdc_of_ids);
634 
sdr_set_bits(void __iomem * reg,u32 bs)635 static void sdr_set_bits(void __iomem *reg, u32 bs)
636 {
637 	u32 val = readl(reg);
638 
639 	val |= bs;
640 	writel(val, reg);
641 }
642 
sdr_clr_bits(void __iomem * reg,u32 bs)643 static void sdr_clr_bits(void __iomem *reg, u32 bs)
644 {
645 	u32 val = readl(reg);
646 
647 	val &= ~bs;
648 	writel(val, reg);
649 }
650 
sdr_set_field(void __iomem * reg,u32 field,u32 val)651 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
652 {
653 	unsigned int tv = readl(reg);
654 
655 	tv &= ~field;
656 	tv |= ((val) << (ffs((unsigned int)field) - 1));
657 	writel(tv, reg);
658 }
659 
sdr_get_field(void __iomem * reg,u32 field,u32 * val)660 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
661 {
662 	unsigned int tv = readl(reg);
663 
664 	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
665 }
666 
msdc_reset_hw(struct msdc_host * host)667 static void msdc_reset_hw(struct msdc_host *host)
668 {
669 	u32 val;
670 
671 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
672 	readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
673 
674 	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
675 	readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
676 				  !(val & MSDC_FIFOCS_CLR), 0, 0);
677 
678 	val = readl(host->base + MSDC_INT);
679 	writel(val, host->base + MSDC_INT);
680 }
681 
682 static void msdc_cmd_next(struct msdc_host *host,
683 		struct mmc_request *mrq, struct mmc_command *cmd);
684 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
685 
686 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
687 			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
688 			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
689 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
690 			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
691 			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
692 
msdc_dma_calcs(u8 * buf,u32 len)693 static u8 msdc_dma_calcs(u8 *buf, u32 len)
694 {
695 	u32 i, sum = 0;
696 
697 	for (i = 0; i < len; i++)
698 		sum += buf[i];
699 	return 0xff - (u8) sum;
700 }
701 
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)702 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
703 		struct mmc_data *data)
704 {
705 	unsigned int j, dma_len;
706 	dma_addr_t dma_address;
707 	u32 dma_ctrl;
708 	struct scatterlist *sg;
709 	struct mt_gpdma_desc *gpd;
710 	struct mt_bdma_desc *bd;
711 
712 	sg = data->sg;
713 
714 	gpd = dma->gpd;
715 	bd = dma->bd;
716 
717 	/* modify gpd */
718 	gpd->gpd_info |= GPDMA_DESC_HWO;
719 	gpd->gpd_info |= GPDMA_DESC_BDP;
720 	/* need to clear first. use these bits to calc checksum */
721 	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
722 	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
723 
724 	/* modify bd */
725 	for_each_sg(data->sg, sg, data->sg_count, j) {
726 		dma_address = sg_dma_address(sg);
727 		dma_len = sg_dma_len(sg);
728 
729 		/* init bd */
730 		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
731 		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
732 		bd[j].ptr = lower_32_bits(dma_address);
733 		if (host->dev_comp->support_64g) {
734 			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
735 			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
736 					 << 28;
737 		}
738 
739 		if (host->dev_comp->support_64g) {
740 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
741 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
742 		} else {
743 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
744 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
745 		}
746 
747 		if (j == data->sg_count - 1) /* the last bd */
748 			bd[j].bd_info |= BDMA_DESC_EOL;
749 		else
750 			bd[j].bd_info &= ~BDMA_DESC_EOL;
751 
752 		/* checksum need to clear first */
753 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
754 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
755 	}
756 
757 	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
758 	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
759 	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
760 	dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
761 	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
762 	if (host->dev_comp->support_64g)
763 		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
764 			      upper_32_bits(dma->gpd_addr) & 0xf);
765 	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
766 }
767 
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)768 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
769 {
770 	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
771 		data->host_cookie |= MSDC_PREPARE_FLAG;
772 		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
773 					    mmc_get_dma_dir(data));
774 	}
775 }
776 
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)777 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
778 {
779 	if (data->host_cookie & MSDC_ASYNC_FLAG)
780 		return;
781 
782 	if (data->host_cookie & MSDC_PREPARE_FLAG) {
783 		dma_unmap_sg(host->dev, data->sg, data->sg_len,
784 			     mmc_get_dma_dir(data));
785 		data->host_cookie &= ~MSDC_PREPARE_FLAG;
786 	}
787 }
788 
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)789 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
790 {
791 	struct mmc_host *mmc = mmc_from_priv(host);
792 	u64 timeout, clk_ns;
793 	u32 mode = 0;
794 
795 	if (mmc->actual_clock == 0) {
796 		timeout = 0;
797 	} else {
798 		clk_ns  = 1000000000ULL;
799 		do_div(clk_ns, mmc->actual_clock);
800 		timeout = ns + clk_ns - 1;
801 		do_div(timeout, clk_ns);
802 		timeout += clks;
803 		/* in 1048576 sclk cycle unit */
804 		timeout = DIV_ROUND_UP(timeout, BIT(20));
805 		if (host->dev_comp->clk_div_bits == 8)
806 			sdr_get_field(host->base + MSDC_CFG,
807 				      MSDC_CFG_CKMOD, &mode);
808 		else
809 			sdr_get_field(host->base + MSDC_CFG,
810 				      MSDC_CFG_CKMOD_EXTRA, &mode);
811 		/*DDR mode will double the clk cycles for data timeout */
812 		timeout = mode >= 2 ? timeout * 2 : timeout;
813 		timeout = timeout > 1 ? timeout - 1 : 0;
814 	}
815 	return timeout;
816 }
817 
818 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)819 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
820 {
821 	u64 timeout;
822 
823 	host->timeout_ns = ns;
824 	host->timeout_clks = clks;
825 
826 	timeout = msdc_timeout_cal(host, ns, clks);
827 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
828 		      (u32)(timeout > 255 ? 255 : timeout));
829 }
830 
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)831 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
832 {
833 	u64 timeout;
834 
835 	timeout = msdc_timeout_cal(host, ns, clks);
836 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
837 		      (u32)(timeout > 8191 ? 8191 : timeout));
838 }
839 
msdc_gate_clock(struct msdc_host * host)840 static void msdc_gate_clock(struct msdc_host *host)
841 {
842 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
843 	clk_disable_unprepare(host->crypto_clk);
844 	clk_disable_unprepare(host->src_clk_cg);
845 	clk_disable_unprepare(host->src_clk);
846 	clk_disable_unprepare(host->bus_clk);
847 	clk_disable_unprepare(host->h_clk);
848 }
849 
msdc_ungate_clock(struct msdc_host * host)850 static int msdc_ungate_clock(struct msdc_host *host)
851 {
852 	u32 val;
853 	int ret;
854 
855 	clk_prepare_enable(host->h_clk);
856 	clk_prepare_enable(host->bus_clk);
857 	clk_prepare_enable(host->src_clk);
858 	clk_prepare_enable(host->src_clk_cg);
859 	clk_prepare_enable(host->crypto_clk);
860 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
861 	if (ret) {
862 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
863 		return ret;
864 	}
865 
866 	return readl_poll_timeout(host->base + MSDC_CFG, val,
867 				  (val & MSDC_CFG_CKSTB), 1, 20000);
868 }
869 
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)870 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
871 {
872 	struct mmc_host *mmc = mmc_from_priv(host);
873 	u32 mode;
874 	u32 flags;
875 	u32 div;
876 	u32 sclk;
877 	u32 tune_reg = host->dev_comp->pad_tune_reg;
878 	u32 val;
879 
880 	if (!hz) {
881 		dev_dbg(host->dev, "set mclk to 0\n");
882 		host->mclk = 0;
883 		mmc->actual_clock = 0;
884 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
885 		return;
886 	}
887 
888 	flags = readl(host->base + MSDC_INTEN);
889 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
890 	if (host->dev_comp->clk_div_bits == 8)
891 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
892 	else
893 		sdr_clr_bits(host->base + MSDC_CFG,
894 			     MSDC_CFG_HS400_CK_MODE_EXTRA);
895 	if (timing == MMC_TIMING_UHS_DDR50 ||
896 	    timing == MMC_TIMING_MMC_DDR52 ||
897 	    timing == MMC_TIMING_MMC_HS400) {
898 		if (timing == MMC_TIMING_MMC_HS400)
899 			mode = 0x3;
900 		else
901 			mode = 0x2; /* ddr mode and use divisor */
902 
903 		if (hz >= (host->src_clk_freq >> 2)) {
904 			div = 0; /* mean div = 1/4 */
905 			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
906 		} else {
907 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
908 			sclk = (host->src_clk_freq >> 2) / div;
909 			div = (div >> 1);
910 		}
911 
912 		if (timing == MMC_TIMING_MMC_HS400 &&
913 		    hz >= (host->src_clk_freq >> 1)) {
914 			if (host->dev_comp->clk_div_bits == 8)
915 				sdr_set_bits(host->base + MSDC_CFG,
916 					     MSDC_CFG_HS400_CK_MODE);
917 			else
918 				sdr_set_bits(host->base + MSDC_CFG,
919 					     MSDC_CFG_HS400_CK_MODE_EXTRA);
920 			sclk = host->src_clk_freq >> 1;
921 			div = 0; /* div is ignore when bit18 is set */
922 		}
923 	} else if (hz >= host->src_clk_freq) {
924 		mode = 0x1; /* no divisor */
925 		div = 0;
926 		sclk = host->src_clk_freq;
927 	} else {
928 		mode = 0x0; /* use divisor */
929 		if (hz >= (host->src_clk_freq >> 1)) {
930 			div = 0; /* mean div = 1/2 */
931 			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
932 		} else {
933 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
934 			sclk = (host->src_clk_freq >> 2) / div;
935 		}
936 	}
937 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
938 
939 	clk_disable_unprepare(host->src_clk_cg);
940 	if (host->dev_comp->clk_div_bits == 8)
941 		sdr_set_field(host->base + MSDC_CFG,
942 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
943 			      (mode << 8) | div);
944 	else
945 		sdr_set_field(host->base + MSDC_CFG,
946 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
947 			      (mode << 12) | div);
948 
949 	clk_prepare_enable(host->src_clk_cg);
950 	readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
951 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
952 	mmc->actual_clock = sclk;
953 	host->mclk = hz;
954 	host->timing = timing;
955 	/* need because clk changed. */
956 	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
957 	sdr_set_bits(host->base + MSDC_INTEN, flags);
958 
959 	/*
960 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
961 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
962 	 */
963 	if (mmc->actual_clock <= 52000000) {
964 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
965 		if (host->top_base) {
966 			writel(host->def_tune_para.emmc_top_control,
967 			       host->top_base + EMMC_TOP_CONTROL);
968 			writel(host->def_tune_para.emmc_top_cmd,
969 			       host->top_base + EMMC_TOP_CMD);
970 		} else {
971 			writel(host->def_tune_para.pad_tune,
972 			       host->base + tune_reg);
973 		}
974 	} else {
975 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
976 		writel(host->saved_tune_para.pad_cmd_tune,
977 		       host->base + PAD_CMD_TUNE);
978 		if (host->top_base) {
979 			writel(host->saved_tune_para.emmc_top_control,
980 			       host->top_base + EMMC_TOP_CONTROL);
981 			writel(host->saved_tune_para.emmc_top_cmd,
982 			       host->top_base + EMMC_TOP_CMD);
983 		} else {
984 			writel(host->saved_tune_para.pad_tune,
985 			       host->base + tune_reg);
986 		}
987 	}
988 
989 	if (timing == MMC_TIMING_MMC_HS400 &&
990 	    host->dev_comp->hs400_tune)
991 		sdr_set_field(host->base + tune_reg,
992 			      MSDC_PAD_TUNE_CMDRRDLY,
993 			      host->hs400_cmd_int_delay);
994 	dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
995 		timing);
996 }
997 
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)998 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
999 		struct mmc_command *cmd)
1000 {
1001 	u32 resp;
1002 
1003 	switch (mmc_resp_type(cmd)) {
1004 		/* Actually, R1, R5, R6, R7 are the same */
1005 	case MMC_RSP_R1:
1006 		resp = 0x1;
1007 		break;
1008 	case MMC_RSP_R1B:
1009 		resp = 0x7;
1010 		break;
1011 	case MMC_RSP_R2:
1012 		resp = 0x2;
1013 		break;
1014 	case MMC_RSP_R3:
1015 		resp = 0x3;
1016 		break;
1017 	case MMC_RSP_NONE:
1018 	default:
1019 		resp = 0x0;
1020 		break;
1021 	}
1022 
1023 	return resp;
1024 }
1025 
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1026 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1027 		struct mmc_request *mrq, struct mmc_command *cmd)
1028 {
1029 	struct mmc_host *mmc = mmc_from_priv(host);
1030 	/* rawcmd :
1031 	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1032 	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1033 	 */
1034 	u32 opcode = cmd->opcode;
1035 	u32 resp = msdc_cmd_find_resp(host, cmd);
1036 	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1037 
1038 	host->cmd_rsp = resp;
1039 
1040 	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1041 	    opcode == MMC_STOP_TRANSMISSION)
1042 		rawcmd |= BIT(14);
1043 	else if (opcode == SD_SWITCH_VOLTAGE)
1044 		rawcmd |= BIT(30);
1045 	else if (opcode == SD_APP_SEND_SCR ||
1046 		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1047 		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1048 		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1049 		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1050 		rawcmd |= BIT(11);
1051 
1052 	if (cmd->data) {
1053 		struct mmc_data *data = cmd->data;
1054 
1055 		if (mmc_op_multi(opcode)) {
1056 			if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1057 			    !(mrq->sbc->arg & 0xFFFF0000))
1058 				rawcmd |= BIT(29); /* AutoCMD23 */
1059 		}
1060 
1061 		rawcmd |= ((data->blksz & 0xFFF) << 16);
1062 		if (data->flags & MMC_DATA_WRITE)
1063 			rawcmd |= BIT(13);
1064 		if (data->blocks > 1)
1065 			rawcmd |= BIT(12);
1066 		else
1067 			rawcmd |= BIT(11);
1068 		/* Always use dma mode */
1069 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1070 
1071 		if (host->timeout_ns != data->timeout_ns ||
1072 		    host->timeout_clks != data->timeout_clks)
1073 			msdc_set_timeout(host, data->timeout_ns,
1074 					data->timeout_clks);
1075 
1076 		writel(data->blocks, host->base + SDC_BLK_NUM);
1077 	}
1078 	return rawcmd;
1079 }
1080 
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1081 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1082 		struct mmc_data *data)
1083 {
1084 	bool read;
1085 
1086 	WARN_ON(host->data);
1087 	host->data = data;
1088 	read = data->flags & MMC_DATA_READ;
1089 
1090 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1091 	msdc_dma_setup(host, &host->dma, data);
1092 	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1093 	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1094 	dev_dbg(host->dev, "DMA start\n");
1095 	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1096 			__func__, cmd->opcode, data->blocks, read);
1097 }
1098 
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1099 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1100 		struct mmc_command *cmd)
1101 {
1102 	u32 *rsp = cmd->resp;
1103 
1104 	rsp[0] = readl(host->base + SDC_ACMD_RESP);
1105 
1106 	if (events & MSDC_INT_ACMDRDY) {
1107 		cmd->error = 0;
1108 	} else {
1109 		msdc_reset_hw(host);
1110 		if (events & MSDC_INT_ACMDCRCERR) {
1111 			cmd->error = -EILSEQ;
1112 			host->error |= REQ_STOP_EIO;
1113 		} else if (events & MSDC_INT_ACMDTMO) {
1114 			cmd->error = -ETIMEDOUT;
1115 			host->error |= REQ_STOP_TMO;
1116 		}
1117 		dev_err(host->dev,
1118 			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1119 			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1120 	}
1121 	return cmd->error;
1122 }
1123 
1124 /*
1125  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1126  *
1127  * Host controller may lost interrupt in some special case.
1128  * Add SDIO irq recheck mechanism to make sure all interrupts
1129  * can be processed immediately
1130  */
msdc_recheck_sdio_irq(struct msdc_host * host)1131 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1132 {
1133 	struct mmc_host *mmc = mmc_from_priv(host);
1134 	u32 reg_int, reg_inten, reg_ps;
1135 
1136 	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1137 		reg_inten = readl(host->base + MSDC_INTEN);
1138 		if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1139 			reg_int = readl(host->base + MSDC_INT);
1140 			reg_ps = readl(host->base + MSDC_PS);
1141 			if (!(reg_int & MSDC_INT_SDIOIRQ ||
1142 			      reg_ps & MSDC_PS_DATA1)) {
1143 				__msdc_enable_sdio_irq(host, 0);
1144 				sdio_signal_irq(mmc);
1145 			}
1146 		}
1147 	}
1148 }
1149 
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1150 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1151 {
1152 	if (host->error)
1153 		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1154 			__func__, cmd->opcode, cmd->arg, host->error);
1155 }
1156 
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1157 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1158 {
1159 	unsigned long flags;
1160 
1161 	/*
1162 	 * No need check the return value of cancel_delayed_work, as only ONE
1163 	 * path will go here!
1164 	 */
1165 	cancel_delayed_work(&host->req_timeout);
1166 
1167 	spin_lock_irqsave(&host->lock, flags);
1168 	host->mrq = NULL;
1169 	spin_unlock_irqrestore(&host->lock, flags);
1170 
1171 	msdc_track_cmd_data(host, mrq->cmd);
1172 	if (mrq->data)
1173 		msdc_unprepare_data(host, mrq->data);
1174 	if (host->error)
1175 		msdc_reset_hw(host);
1176 	mmc_request_done(mmc_from_priv(host), mrq);
1177 	if (host->dev_comp->recheck_sdio_irq)
1178 		msdc_recheck_sdio_irq(host);
1179 }
1180 
1181 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1182 static bool msdc_cmd_done(struct msdc_host *host, int events,
1183 			  struct mmc_request *mrq, struct mmc_command *cmd)
1184 {
1185 	bool done = false;
1186 	bool sbc_error;
1187 	unsigned long flags;
1188 	u32 *rsp;
1189 
1190 	if (mrq->sbc && cmd == mrq->cmd &&
1191 	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1192 				   | MSDC_INT_ACMDTMO)))
1193 		msdc_auto_cmd_done(host, events, mrq->sbc);
1194 
1195 	sbc_error = mrq->sbc && mrq->sbc->error;
1196 
1197 	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1198 					| MSDC_INT_RSPCRCERR
1199 					| MSDC_INT_CMDTMO)))
1200 		return done;
1201 
1202 	spin_lock_irqsave(&host->lock, flags);
1203 	done = !host->cmd;
1204 	host->cmd = NULL;
1205 	spin_unlock_irqrestore(&host->lock, flags);
1206 
1207 	if (done)
1208 		return true;
1209 	rsp = cmd->resp;
1210 
1211 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1212 
1213 	if (cmd->flags & MMC_RSP_PRESENT) {
1214 		if (cmd->flags & MMC_RSP_136) {
1215 			rsp[0] = readl(host->base + SDC_RESP3);
1216 			rsp[1] = readl(host->base + SDC_RESP2);
1217 			rsp[2] = readl(host->base + SDC_RESP1);
1218 			rsp[3] = readl(host->base + SDC_RESP0);
1219 		} else {
1220 			rsp[0] = readl(host->base + SDC_RESP0);
1221 		}
1222 	}
1223 
1224 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1225 		if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1226 		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1227 			/*
1228 			 * should not clear fifo/interrupt as the tune data
1229 			 * may have already come when cmd19/cmd21 gets response
1230 			 * CRC error.
1231 			 */
1232 			msdc_reset_hw(host);
1233 		if (events & MSDC_INT_RSPCRCERR) {
1234 			cmd->error = -EILSEQ;
1235 			host->error |= REQ_CMD_EIO;
1236 		} else if (events & MSDC_INT_CMDTMO) {
1237 			cmd->error = -ETIMEDOUT;
1238 			host->error |= REQ_CMD_TMO;
1239 		}
1240 	}
1241 	if (cmd->error)
1242 		dev_dbg(host->dev,
1243 				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1244 				__func__, cmd->opcode, cmd->arg, rsp[0],
1245 				cmd->error);
1246 
1247 	msdc_cmd_next(host, mrq, cmd);
1248 	return true;
1249 }
1250 
1251 /* It is the core layer's responsibility to ensure card status
1252  * is correct before issue a request. but host design do below
1253  * checks recommended.
1254  */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1255 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1256 		struct mmc_request *mrq, struct mmc_command *cmd)
1257 {
1258 	u32 val;
1259 	int ret;
1260 
1261 	/* The max busy time we can endure is 20ms */
1262 	ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1263 					!(val & SDC_STS_CMDBUSY), 1, 20000);
1264 	if (ret) {
1265 		dev_err(host->dev, "CMD bus busy detected\n");
1266 		host->error |= REQ_CMD_BUSY;
1267 		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1268 		return false;
1269 	}
1270 
1271 	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1272 		/* R1B or with data, should check SDCBUSY */
1273 		ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1274 						!(val & SDC_STS_SDCBUSY), 1, 20000);
1275 		if (ret) {
1276 			dev_err(host->dev, "Controller busy detected\n");
1277 			host->error |= REQ_CMD_BUSY;
1278 			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1279 			return false;
1280 		}
1281 	}
1282 	return true;
1283 }
1284 
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1285 static void msdc_start_command(struct msdc_host *host,
1286 		struct mmc_request *mrq, struct mmc_command *cmd)
1287 {
1288 	u32 rawcmd;
1289 	unsigned long flags;
1290 
1291 	WARN_ON(host->cmd);
1292 	host->cmd = cmd;
1293 
1294 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1295 	if (!msdc_cmd_is_ready(host, mrq, cmd))
1296 		return;
1297 
1298 	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1299 	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1300 		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1301 		msdc_reset_hw(host);
1302 	}
1303 
1304 	cmd->error = 0;
1305 	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1306 
1307 	spin_lock_irqsave(&host->lock, flags);
1308 	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1309 	spin_unlock_irqrestore(&host->lock, flags);
1310 
1311 	writel(cmd->arg, host->base + SDC_ARG);
1312 	writel(rawcmd, host->base + SDC_CMD);
1313 }
1314 
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1315 static void msdc_cmd_next(struct msdc_host *host,
1316 		struct mmc_request *mrq, struct mmc_command *cmd)
1317 {
1318 	if ((cmd->error && !host->hs400_tuning &&
1319 	     !(cmd->error == -EILSEQ &&
1320 	     mmc_op_tuning(cmd->opcode))) ||
1321 	    (mrq->sbc && mrq->sbc->error))
1322 		msdc_request_done(host, mrq);
1323 	else if (cmd == mrq->sbc)
1324 		msdc_start_command(host, mrq, mrq->cmd);
1325 	else if (!cmd->data)
1326 		msdc_request_done(host, mrq);
1327 	else
1328 		msdc_start_data(host, cmd, cmd->data);
1329 }
1330 
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1331 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1332 {
1333 	struct msdc_host *host = mmc_priv(mmc);
1334 
1335 	host->error = 0;
1336 	WARN_ON(host->mrq);
1337 	host->mrq = mrq;
1338 
1339 	if (mrq->data)
1340 		msdc_prepare_data(host, mrq->data);
1341 
1342 	/* if SBC is required, we have HW option and SW option.
1343 	 * if HW option is enabled, and SBC does not have "special" flags,
1344 	 * use HW option,  otherwise use SW option
1345 	 */
1346 	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1347 	    (mrq->sbc->arg & 0xFFFF0000)))
1348 		msdc_start_command(host, mrq, mrq->sbc);
1349 	else
1350 		msdc_start_command(host, mrq, mrq->cmd);
1351 }
1352 
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1353 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1354 {
1355 	struct msdc_host *host = mmc_priv(mmc);
1356 	struct mmc_data *data = mrq->data;
1357 
1358 	if (!data)
1359 		return;
1360 
1361 	msdc_prepare_data(host, data);
1362 	data->host_cookie |= MSDC_ASYNC_FLAG;
1363 }
1364 
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1365 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1366 		int err)
1367 {
1368 	struct msdc_host *host = mmc_priv(mmc);
1369 	struct mmc_data *data = mrq->data;
1370 
1371 	if (!data)
1372 		return;
1373 
1374 	if (data->host_cookie) {
1375 		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1376 		msdc_unprepare_data(host, data);
1377 	}
1378 }
1379 
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1380 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1381 {
1382 	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1383 	    !mrq->sbc)
1384 		msdc_start_command(host, mrq, mrq->stop);
1385 	else
1386 		msdc_request_done(host, mrq);
1387 }
1388 
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1389 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1390 				struct mmc_request *mrq, struct mmc_data *data)
1391 {
1392 	struct mmc_command *stop;
1393 	unsigned long flags;
1394 	bool done;
1395 	unsigned int check_data = events &
1396 	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1397 	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1398 	     | MSDC_INT_DMA_PROTECT);
1399 	u32 val;
1400 	int ret;
1401 
1402 	spin_lock_irqsave(&host->lock, flags);
1403 	done = !host->data;
1404 	if (check_data)
1405 		host->data = NULL;
1406 	spin_unlock_irqrestore(&host->lock, flags);
1407 
1408 	if (done)
1409 		return;
1410 	stop = data->stop;
1411 
1412 	if (check_data || (stop && stop->error)) {
1413 		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1414 				readl(host->base + MSDC_DMA_CFG));
1415 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1416 				1);
1417 
1418 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1419 						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1420 		if (ret)
1421 			dev_dbg(host->dev, "DMA stop timed out\n");
1422 
1423 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1424 						!(val & MSDC_DMA_CFG_STS), 1, 20000);
1425 		if (ret)
1426 			dev_dbg(host->dev, "DMA inactive timed out\n");
1427 
1428 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1429 		dev_dbg(host->dev, "DMA stop\n");
1430 
1431 		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1432 			data->bytes_xfered = data->blocks * data->blksz;
1433 		} else {
1434 			dev_dbg(host->dev, "interrupt events: %x\n", events);
1435 			msdc_reset_hw(host);
1436 			host->error |= REQ_DAT_ERR;
1437 			data->bytes_xfered = 0;
1438 
1439 			if (events & MSDC_INT_DATTMO)
1440 				data->error = -ETIMEDOUT;
1441 			else if (events & MSDC_INT_DATCRCERR)
1442 				data->error = -EILSEQ;
1443 
1444 			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1445 				__func__, mrq->cmd->opcode, data->blocks);
1446 			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1447 				(int)data->error, data->bytes_xfered);
1448 		}
1449 
1450 		msdc_data_xfer_next(host, mrq);
1451 	}
1452 }
1453 
msdc_set_buswidth(struct msdc_host * host,u32 width)1454 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1455 {
1456 	u32 val = readl(host->base + SDC_CFG);
1457 
1458 	val &= ~SDC_CFG_BUSWIDTH;
1459 
1460 	switch (width) {
1461 	default:
1462 	case MMC_BUS_WIDTH_1:
1463 		val |= (MSDC_BUS_1BITS << 16);
1464 		break;
1465 	case MMC_BUS_WIDTH_4:
1466 		val |= (MSDC_BUS_4BITS << 16);
1467 		break;
1468 	case MMC_BUS_WIDTH_8:
1469 		val |= (MSDC_BUS_8BITS << 16);
1470 		break;
1471 	}
1472 
1473 	writel(val, host->base + SDC_CFG);
1474 	dev_dbg(host->dev, "Bus Width = %d", width);
1475 }
1476 
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1477 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1478 {
1479 	struct msdc_host *host = mmc_priv(mmc);
1480 	int ret;
1481 
1482 	if (!IS_ERR(mmc->supply.vqmmc)) {
1483 		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1484 		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1485 			dev_err(host->dev, "Unsupported signal voltage!\n");
1486 			return -EINVAL;
1487 		}
1488 
1489 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1490 		if (ret < 0) {
1491 			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1492 				ret, ios->signal_voltage);
1493 			return ret;
1494 		}
1495 
1496 		/* Apply different pinctrl settings for different signal voltage */
1497 		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1498 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1499 		else
1500 			pinctrl_select_state(host->pinctrl, host->pins_default);
1501 	}
1502 	return 0;
1503 }
1504 
msdc_card_busy(struct mmc_host * mmc)1505 static int msdc_card_busy(struct mmc_host *mmc)
1506 {
1507 	struct msdc_host *host = mmc_priv(mmc);
1508 	u32 status = readl(host->base + MSDC_PS);
1509 
1510 	/* only check if data0 is low */
1511 	return !(status & BIT(16));
1512 }
1513 
msdc_request_timeout(struct work_struct * work)1514 static void msdc_request_timeout(struct work_struct *work)
1515 {
1516 	struct msdc_host *host = container_of(work, struct msdc_host,
1517 			req_timeout.work);
1518 
1519 	/* simulate HW timeout status */
1520 	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1521 	if (host->mrq) {
1522 		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1523 				host->mrq, host->mrq->cmd->opcode);
1524 		if (host->cmd) {
1525 			dev_err(host->dev, "%s: aborting cmd=%d\n",
1526 					__func__, host->cmd->opcode);
1527 			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1528 					host->cmd);
1529 		} else if (host->data) {
1530 			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1531 					__func__, host->mrq->cmd->opcode,
1532 					host->data->blocks);
1533 			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1534 					host->data);
1535 		}
1536 	}
1537 }
1538 
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1539 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1540 {
1541 	if (enb) {
1542 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1543 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1544 		if (host->dev_comp->recheck_sdio_irq)
1545 			msdc_recheck_sdio_irq(host);
1546 	} else {
1547 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1548 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1549 	}
1550 }
1551 
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1552 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1553 {
1554 	struct msdc_host *host = mmc_priv(mmc);
1555 	unsigned long flags;
1556 	int ret;
1557 
1558 	spin_lock_irqsave(&host->lock, flags);
1559 	__msdc_enable_sdio_irq(host, enb);
1560 	spin_unlock_irqrestore(&host->lock, flags);
1561 
1562 	if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1563 		if (enb) {
1564 			/*
1565 			 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1566 			 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1567 			 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1568 			 * affect successfully, we change the pinstate to pins_eint firstly.
1569 			 */
1570 			pinctrl_select_state(host->pinctrl, host->pins_eint);
1571 			ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1572 
1573 			if (ret) {
1574 				dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1575 				host->pins_eint = NULL;
1576 				pm_runtime_get_noresume(host->dev);
1577 			} else {
1578 				dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1579 			}
1580 
1581 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1582 		} else {
1583 			dev_pm_clear_wake_irq(host->dev);
1584 		}
1585 	} else {
1586 		if (enb) {
1587 			/* Ensure host->pins_eint is NULL */
1588 			host->pins_eint = NULL;
1589 			pm_runtime_get_noresume(host->dev);
1590 		} else {
1591 			pm_runtime_put_noidle(host->dev);
1592 		}
1593 	}
1594 }
1595 
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1596 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1597 {
1598 	struct mmc_host *mmc = mmc_from_priv(host);
1599 	int cmd_err = 0, dat_err = 0;
1600 
1601 	if (intsts & MSDC_INT_RSPCRCERR) {
1602 		cmd_err = -EILSEQ;
1603 		dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1604 	} else if (intsts & MSDC_INT_CMDTMO) {
1605 		cmd_err = -ETIMEDOUT;
1606 		dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1607 	}
1608 
1609 	if (intsts & MSDC_INT_DATCRCERR) {
1610 		dat_err = -EILSEQ;
1611 		dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1612 	} else if (intsts & MSDC_INT_DATTMO) {
1613 		dat_err = -ETIMEDOUT;
1614 		dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1615 	}
1616 
1617 	if (cmd_err || dat_err) {
1618 		dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1619 			cmd_err, dat_err, intsts);
1620 	}
1621 
1622 	return cqhci_irq(mmc, 0, cmd_err, dat_err);
1623 }
1624 
msdc_irq(int irq,void * dev_id)1625 static irqreturn_t msdc_irq(int irq, void *dev_id)
1626 {
1627 	struct msdc_host *host = (struct msdc_host *) dev_id;
1628 	struct mmc_host *mmc = mmc_from_priv(host);
1629 
1630 	while (true) {
1631 		struct mmc_request *mrq;
1632 		struct mmc_command *cmd;
1633 		struct mmc_data *data;
1634 		u32 events, event_mask;
1635 
1636 		spin_lock(&host->lock);
1637 		events = readl(host->base + MSDC_INT);
1638 		event_mask = readl(host->base + MSDC_INTEN);
1639 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1640 			__msdc_enable_sdio_irq(host, 0);
1641 		/* clear interrupts */
1642 		writel(events & event_mask, host->base + MSDC_INT);
1643 
1644 		mrq = host->mrq;
1645 		cmd = host->cmd;
1646 		data = host->data;
1647 		spin_unlock(&host->lock);
1648 
1649 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1650 			sdio_signal_irq(mmc);
1651 
1652 		if ((events & event_mask) & MSDC_INT_CDSC) {
1653 			if (host->internal_cd)
1654 				mmc_detect_change(mmc, msecs_to_jiffies(20));
1655 			events &= ~MSDC_INT_CDSC;
1656 		}
1657 
1658 		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1659 			break;
1660 
1661 		if ((mmc->caps2 & MMC_CAP2_CQE) &&
1662 		    (events & MSDC_INT_CMDQ)) {
1663 			msdc_cmdq_irq(host, events);
1664 			/* clear interrupts */
1665 			writel(events, host->base + MSDC_INT);
1666 			return IRQ_HANDLED;
1667 		}
1668 
1669 		if (!mrq) {
1670 			dev_err(host->dev,
1671 				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1672 				__func__, events, event_mask);
1673 			WARN_ON(1);
1674 			break;
1675 		}
1676 
1677 		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1678 
1679 		if (cmd)
1680 			msdc_cmd_done(host, events, mrq, cmd);
1681 		else if (data)
1682 			msdc_data_xfer_done(host, events, mrq, data);
1683 	}
1684 
1685 	return IRQ_HANDLED;
1686 }
1687 
msdc_init_hw(struct msdc_host * host)1688 static void msdc_init_hw(struct msdc_host *host)
1689 {
1690 	u32 val;
1691 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1692 	struct mmc_host *mmc = mmc_from_priv(host);
1693 
1694 	if (host->reset) {
1695 		reset_control_assert(host->reset);
1696 		usleep_range(10, 50);
1697 		reset_control_deassert(host->reset);
1698 	}
1699 
1700 	/* Configure to MMC/SD mode, clock free running */
1701 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1702 
1703 	/* Reset */
1704 	msdc_reset_hw(host);
1705 
1706 	/* Disable and clear all interrupts */
1707 	writel(0, host->base + MSDC_INTEN);
1708 	val = readl(host->base + MSDC_INT);
1709 	writel(val, host->base + MSDC_INT);
1710 
1711 	/* Configure card detection */
1712 	if (host->internal_cd) {
1713 		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1714 			      DEFAULT_DEBOUNCE);
1715 		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1716 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1717 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1718 	} else {
1719 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1720 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1721 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1722 	}
1723 
1724 	if (host->top_base) {
1725 		writel(0, host->top_base + EMMC_TOP_CONTROL);
1726 		writel(0, host->top_base + EMMC_TOP_CMD);
1727 	} else {
1728 		writel(0, host->base + tune_reg);
1729 	}
1730 	writel(0, host->base + MSDC_IOCON);
1731 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1732 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1733 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1734 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1735 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1736 
1737 	if (host->dev_comp->stop_clk_fix) {
1738 		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1739 			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1740 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1741 			     SDC_FIFO_CFG_WRVALIDSEL);
1742 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1743 			     SDC_FIFO_CFG_RDVALIDSEL);
1744 	}
1745 
1746 	if (host->dev_comp->busy_check)
1747 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1748 
1749 	if (host->dev_comp->async_fifo) {
1750 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1751 			      MSDC_PB2_RESPWAIT, 3);
1752 		if (host->dev_comp->enhance_rx) {
1753 			if (host->top_base)
1754 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1755 					     SDC_RX_ENH_EN);
1756 			else
1757 				sdr_set_bits(host->base + SDC_ADV_CFG0,
1758 					     SDC_RX_ENHANCE_EN);
1759 		} else {
1760 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1761 				      MSDC_PB2_RESPSTSENSEL, 2);
1762 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1763 				      MSDC_PB2_CRCSTSENSEL, 2);
1764 		}
1765 		/* use async fifo, then no need tune internal delay */
1766 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1767 			     MSDC_PATCH_BIT2_CFGRESP);
1768 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1769 			     MSDC_PATCH_BIT2_CFGCRCSTS);
1770 	}
1771 
1772 	if (host->dev_comp->support_64g)
1773 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1774 			     MSDC_PB2_SUPPORT_64G);
1775 	if (host->dev_comp->data_tune) {
1776 		if (host->top_base) {
1777 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1778 				     PAD_DAT_RD_RXDLY_SEL);
1779 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1780 				     DATA_K_VALUE_SEL);
1781 			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1782 				     PAD_CMD_RD_RXDLY_SEL);
1783 		} else {
1784 			sdr_set_bits(host->base + tune_reg,
1785 				     MSDC_PAD_TUNE_RD_SEL |
1786 				     MSDC_PAD_TUNE_CMD_SEL);
1787 		}
1788 	} else {
1789 		/* choose clock tune */
1790 		if (host->top_base)
1791 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1792 				     PAD_RXDLY_SEL);
1793 		else
1794 			sdr_set_bits(host->base + tune_reg,
1795 				     MSDC_PAD_TUNE_RXDLYSEL);
1796 	}
1797 
1798 	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1799 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1800 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1801 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1802 	} else {
1803 		/* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1804 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1805 
1806 		/* Config SDIO device detect interrupt function */
1807 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1808 		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1809 	}
1810 
1811 	/* Configure to default data timeout */
1812 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1813 
1814 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1815 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1816 	if (host->top_base) {
1817 		host->def_tune_para.emmc_top_control =
1818 			readl(host->top_base + EMMC_TOP_CONTROL);
1819 		host->def_tune_para.emmc_top_cmd =
1820 			readl(host->top_base + EMMC_TOP_CMD);
1821 		host->saved_tune_para.emmc_top_control =
1822 			readl(host->top_base + EMMC_TOP_CONTROL);
1823 		host->saved_tune_para.emmc_top_cmd =
1824 			readl(host->top_base + EMMC_TOP_CMD);
1825 	} else {
1826 		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1827 		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1828 	}
1829 	dev_dbg(host->dev, "init hardware done!");
1830 }
1831 
msdc_deinit_hw(struct msdc_host * host)1832 static void msdc_deinit_hw(struct msdc_host *host)
1833 {
1834 	u32 val;
1835 
1836 	if (host->internal_cd) {
1837 		/* Disabled card-detect */
1838 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1839 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1840 	}
1841 
1842 	/* Disable and clear all interrupts */
1843 	writel(0, host->base + MSDC_INTEN);
1844 
1845 	val = readl(host->base + MSDC_INT);
1846 	writel(val, host->base + MSDC_INT);
1847 }
1848 
1849 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1850 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1851 {
1852 	struct mt_gpdma_desc *gpd = dma->gpd;
1853 	struct mt_bdma_desc *bd = dma->bd;
1854 	dma_addr_t dma_addr;
1855 	int i;
1856 
1857 	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1858 
1859 	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1860 	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1861 	/* gpd->next is must set for desc DMA
1862 	 * That's why must alloc 2 gpd structure.
1863 	 */
1864 	gpd->next = lower_32_bits(dma_addr);
1865 	if (host->dev_comp->support_64g)
1866 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1867 
1868 	dma_addr = dma->bd_addr;
1869 	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1870 	if (host->dev_comp->support_64g)
1871 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1872 
1873 	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1874 	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1875 		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1876 		bd[i].next = lower_32_bits(dma_addr);
1877 		if (host->dev_comp->support_64g)
1878 			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1879 	}
1880 }
1881 
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1882 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1883 {
1884 	struct msdc_host *host = mmc_priv(mmc);
1885 	int ret;
1886 
1887 	msdc_set_buswidth(host, ios->bus_width);
1888 
1889 	/* Suspend/Resume will do power off/on */
1890 	switch (ios->power_mode) {
1891 	case MMC_POWER_UP:
1892 		if (!IS_ERR(mmc->supply.vmmc)) {
1893 			msdc_init_hw(host);
1894 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1895 					ios->vdd);
1896 			if (ret) {
1897 				dev_err(host->dev, "Failed to set vmmc power!\n");
1898 				return;
1899 			}
1900 		}
1901 		break;
1902 	case MMC_POWER_ON:
1903 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1904 			ret = regulator_enable(mmc->supply.vqmmc);
1905 			if (ret)
1906 				dev_err(host->dev, "Failed to set vqmmc power!\n");
1907 			else
1908 				host->vqmmc_enabled = true;
1909 		}
1910 		break;
1911 	case MMC_POWER_OFF:
1912 		if (!IS_ERR(mmc->supply.vmmc))
1913 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1914 
1915 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1916 			regulator_disable(mmc->supply.vqmmc);
1917 			host->vqmmc_enabled = false;
1918 		}
1919 		break;
1920 	default:
1921 		break;
1922 	}
1923 
1924 	if (host->mclk != ios->clock || host->timing != ios->timing)
1925 		msdc_set_mclk(host, ios->timing, ios->clock);
1926 }
1927 
test_delay_bit(u32 delay,u32 bit)1928 static u32 test_delay_bit(u32 delay, u32 bit)
1929 {
1930 	bit %= PAD_DELAY_MAX;
1931 	return delay & BIT(bit);
1932 }
1933 
get_delay_len(u32 delay,u32 start_bit)1934 static int get_delay_len(u32 delay, u32 start_bit)
1935 {
1936 	int i;
1937 
1938 	for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1939 		if (test_delay_bit(delay, start_bit + i) == 0)
1940 			return i;
1941 	}
1942 	return PAD_DELAY_MAX - start_bit;
1943 }
1944 
get_best_delay(struct msdc_host * host,u32 delay)1945 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1946 {
1947 	int start = 0, len = 0;
1948 	int start_final = 0, len_final = 0;
1949 	u8 final_phase = 0xff;
1950 	struct msdc_delay_phase delay_phase = { 0, };
1951 
1952 	if (delay == 0) {
1953 		dev_err(host->dev, "phase error: [map:%x]\n", delay);
1954 		delay_phase.final_phase = final_phase;
1955 		return delay_phase;
1956 	}
1957 
1958 	while (start < PAD_DELAY_MAX) {
1959 		len = get_delay_len(delay, start);
1960 		if (len_final < len) {
1961 			start_final = start;
1962 			len_final = len;
1963 		}
1964 		start += len ? len : 1;
1965 		if (len >= 12 && start_final < 4)
1966 			break;
1967 	}
1968 
1969 	/* The rule is that to find the smallest delay cell */
1970 	if (start_final == 0)
1971 		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1972 	else
1973 		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1974 	dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1975 		delay, len_final, final_phase);
1976 
1977 	delay_phase.maxlen = len_final;
1978 	delay_phase.start = start_final;
1979 	delay_phase.final_phase = final_phase;
1980 	return delay_phase;
1981 }
1982 
msdc_set_cmd_delay(struct msdc_host * host,u32 value)1983 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1984 {
1985 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1986 
1987 	if (host->top_base)
1988 		sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1989 			      value);
1990 	else
1991 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1992 			      value);
1993 }
1994 
msdc_set_data_delay(struct msdc_host * host,u32 value)1995 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1996 {
1997 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1998 
1999 	if (host->top_base)
2000 		sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2001 			      PAD_DAT_RD_RXDLY, value);
2002 	else
2003 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2004 			      value);
2005 }
2006 
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2007 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2008 {
2009 	struct msdc_host *host = mmc_priv(mmc);
2010 	u32 rise_delay = 0, fall_delay = 0;
2011 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2012 	struct msdc_delay_phase internal_delay_phase;
2013 	u8 final_delay, final_maxlen;
2014 	u32 internal_delay = 0;
2015 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2016 	int cmd_err;
2017 	int i, j;
2018 
2019 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2020 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2021 		sdr_set_field(host->base + tune_reg,
2022 			      MSDC_PAD_TUNE_CMDRRDLY,
2023 			      host->hs200_cmd_int_delay);
2024 
2025 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2026 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2027 		msdc_set_cmd_delay(host, i);
2028 		/*
2029 		 * Using the same parameters, it may sometimes pass the test,
2030 		 * but sometimes it may fail. To make sure the parameters are
2031 		 * more stable, we test each set of parameters 3 times.
2032 		 */
2033 		for (j = 0; j < 3; j++) {
2034 			mmc_send_tuning(mmc, opcode, &cmd_err);
2035 			if (!cmd_err) {
2036 				rise_delay |= BIT(i);
2037 			} else {
2038 				rise_delay &= ~BIT(i);
2039 				break;
2040 			}
2041 		}
2042 	}
2043 	final_rise_delay = get_best_delay(host, rise_delay);
2044 	/* if rising edge has enough margin, then do not scan falling edge */
2045 	if (final_rise_delay.maxlen >= 12 ||
2046 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2047 		goto skip_fall;
2048 
2049 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2050 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2051 		msdc_set_cmd_delay(host, i);
2052 		/*
2053 		 * Using the same parameters, it may sometimes pass the test,
2054 		 * but sometimes it may fail. To make sure the parameters are
2055 		 * more stable, we test each set of parameters 3 times.
2056 		 */
2057 		for (j = 0; j < 3; j++) {
2058 			mmc_send_tuning(mmc, opcode, &cmd_err);
2059 			if (!cmd_err) {
2060 				fall_delay |= BIT(i);
2061 			} else {
2062 				fall_delay &= ~BIT(i);
2063 				break;
2064 			}
2065 		}
2066 	}
2067 	final_fall_delay = get_best_delay(host, fall_delay);
2068 
2069 skip_fall:
2070 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2071 	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2072 		final_maxlen = final_fall_delay.maxlen;
2073 	if (final_maxlen == final_rise_delay.maxlen) {
2074 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2075 		final_delay = final_rise_delay.final_phase;
2076 	} else {
2077 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2078 		final_delay = final_fall_delay.final_phase;
2079 	}
2080 	msdc_set_cmd_delay(host, final_delay);
2081 
2082 	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2083 		goto skip_internal;
2084 
2085 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2086 		sdr_set_field(host->base + tune_reg,
2087 			      MSDC_PAD_TUNE_CMDRRDLY, i);
2088 		mmc_send_tuning(mmc, opcode, &cmd_err);
2089 		if (!cmd_err)
2090 			internal_delay |= BIT(i);
2091 	}
2092 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2093 	internal_delay_phase = get_best_delay(host, internal_delay);
2094 	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2095 		      internal_delay_phase.final_phase);
2096 skip_internal:
2097 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2098 	return final_delay == 0xff ? -EIO : 0;
2099 }
2100 
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2101 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2102 {
2103 	struct msdc_host *host = mmc_priv(mmc);
2104 	u32 cmd_delay = 0;
2105 	struct msdc_delay_phase final_cmd_delay = { 0,};
2106 	u8 final_delay;
2107 	int cmd_err;
2108 	int i, j;
2109 
2110 	/* select EMMC50 PAD CMD tune */
2111 	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2112 	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2113 
2114 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2115 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2116 		sdr_set_field(host->base + MSDC_PAD_TUNE,
2117 			      MSDC_PAD_TUNE_CMDRRDLY,
2118 			      host->hs200_cmd_int_delay);
2119 
2120 	if (host->hs400_cmd_resp_sel_rising)
2121 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2122 	else
2123 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2124 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2125 		sdr_set_field(host->base + PAD_CMD_TUNE,
2126 			      PAD_CMD_TUNE_RX_DLY3, i);
2127 		/*
2128 		 * Using the same parameters, it may sometimes pass the test,
2129 		 * but sometimes it may fail. To make sure the parameters are
2130 		 * more stable, we test each set of parameters 3 times.
2131 		 */
2132 		for (j = 0; j < 3; j++) {
2133 			mmc_send_tuning(mmc, opcode, &cmd_err);
2134 			if (!cmd_err) {
2135 				cmd_delay |= BIT(i);
2136 			} else {
2137 				cmd_delay &= ~BIT(i);
2138 				break;
2139 			}
2140 		}
2141 	}
2142 	final_cmd_delay = get_best_delay(host, cmd_delay);
2143 	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2144 		      final_cmd_delay.final_phase);
2145 	final_delay = final_cmd_delay.final_phase;
2146 
2147 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2148 	return final_delay == 0xff ? -EIO : 0;
2149 }
2150 
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2151 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2152 {
2153 	struct msdc_host *host = mmc_priv(mmc);
2154 	u32 rise_delay = 0, fall_delay = 0;
2155 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2156 	u8 final_delay, final_maxlen;
2157 	int i, ret;
2158 
2159 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2160 		      host->latch_ck);
2161 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2162 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2163 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2164 		msdc_set_data_delay(host, i);
2165 		ret = mmc_send_tuning(mmc, opcode, NULL);
2166 		if (!ret)
2167 			rise_delay |= BIT(i);
2168 	}
2169 	final_rise_delay = get_best_delay(host, rise_delay);
2170 	/* if rising edge has enough margin, then do not scan falling edge */
2171 	if (final_rise_delay.maxlen >= 12 ||
2172 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2173 		goto skip_fall;
2174 
2175 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2176 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2177 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2178 		msdc_set_data_delay(host, i);
2179 		ret = mmc_send_tuning(mmc, opcode, NULL);
2180 		if (!ret)
2181 			fall_delay |= BIT(i);
2182 	}
2183 	final_fall_delay = get_best_delay(host, fall_delay);
2184 
2185 skip_fall:
2186 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2187 	if (final_maxlen == final_rise_delay.maxlen) {
2188 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2189 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2190 		final_delay = final_rise_delay.final_phase;
2191 	} else {
2192 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2193 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2194 		final_delay = final_fall_delay.final_phase;
2195 	}
2196 	msdc_set_data_delay(host, final_delay);
2197 
2198 	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2199 	return final_delay == 0xff ? -EIO : 0;
2200 }
2201 
2202 /*
2203  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2204  * together, which can save the tuning time.
2205  */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2206 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2207 {
2208 	struct msdc_host *host = mmc_priv(mmc);
2209 	u32 rise_delay = 0, fall_delay = 0;
2210 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2211 	u8 final_delay, final_maxlen;
2212 	int i, ret;
2213 
2214 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2215 		      host->latch_ck);
2216 
2217 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2218 	sdr_clr_bits(host->base + MSDC_IOCON,
2219 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2220 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2221 		msdc_set_cmd_delay(host, i);
2222 		msdc_set_data_delay(host, i);
2223 		ret = mmc_send_tuning(mmc, opcode, NULL);
2224 		if (!ret)
2225 			rise_delay |= BIT(i);
2226 	}
2227 	final_rise_delay = get_best_delay(host, rise_delay);
2228 	/* if rising edge has enough margin, then do not scan falling edge */
2229 	if (final_rise_delay.maxlen >= 12 ||
2230 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2231 		goto skip_fall;
2232 
2233 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2234 	sdr_set_bits(host->base + MSDC_IOCON,
2235 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2236 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2237 		msdc_set_cmd_delay(host, i);
2238 		msdc_set_data_delay(host, i);
2239 		ret = mmc_send_tuning(mmc, opcode, NULL);
2240 		if (!ret)
2241 			fall_delay |= BIT(i);
2242 	}
2243 	final_fall_delay = get_best_delay(host, fall_delay);
2244 
2245 skip_fall:
2246 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2247 	if (final_maxlen == final_rise_delay.maxlen) {
2248 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2249 		sdr_clr_bits(host->base + MSDC_IOCON,
2250 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2251 		final_delay = final_rise_delay.final_phase;
2252 	} else {
2253 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2254 		sdr_set_bits(host->base + MSDC_IOCON,
2255 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2256 		final_delay = final_fall_delay.final_phase;
2257 	}
2258 
2259 	msdc_set_cmd_delay(host, final_delay);
2260 	msdc_set_data_delay(host, final_delay);
2261 
2262 	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2263 	return final_delay == 0xff ? -EIO : 0;
2264 }
2265 
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2266 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2267 {
2268 	struct msdc_host *host = mmc_priv(mmc);
2269 	int ret;
2270 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2271 
2272 	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2273 		ret = msdc_tune_together(mmc, opcode);
2274 		if (host->hs400_mode) {
2275 			sdr_clr_bits(host->base + MSDC_IOCON,
2276 				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2277 			msdc_set_data_delay(host, 0);
2278 		}
2279 		goto tune_done;
2280 	}
2281 	if (host->hs400_mode &&
2282 	    host->dev_comp->hs400_tune)
2283 		ret = hs400_tune_response(mmc, opcode);
2284 	else
2285 		ret = msdc_tune_response(mmc, opcode);
2286 	if (ret == -EIO) {
2287 		dev_err(host->dev, "Tune response fail!\n");
2288 		return ret;
2289 	}
2290 	if (host->hs400_mode == false) {
2291 		ret = msdc_tune_data(mmc, opcode);
2292 		if (ret == -EIO)
2293 			dev_err(host->dev, "Tune data fail!\n");
2294 	}
2295 
2296 tune_done:
2297 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2298 	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2299 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2300 	if (host->top_base) {
2301 		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2302 				EMMC_TOP_CONTROL);
2303 		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2304 				EMMC_TOP_CMD);
2305 	}
2306 	return ret;
2307 }
2308 
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2309 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2310 {
2311 	struct msdc_host *host = mmc_priv(mmc);
2312 	host->hs400_mode = true;
2313 
2314 	if (host->top_base)
2315 		writel(host->hs400_ds_delay,
2316 		       host->top_base + EMMC50_PAD_DS_TUNE);
2317 	else
2318 		writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2319 	/* hs400 mode must set it to 0 */
2320 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2321 	/* to improve read performance, set outstanding to 2 */
2322 	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2323 
2324 	return 0;
2325 }
2326 
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2327 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2328 {
2329 	struct msdc_host *host = mmc_priv(mmc);
2330 	struct msdc_delay_phase dly1_delay;
2331 	u32 val, result_dly1 = 0;
2332 	u8 *ext_csd;
2333 	int i, ret;
2334 
2335 	if (host->top_base) {
2336 		sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2337 			     PAD_DS_DLY_SEL);
2338 		if (host->hs400_ds_dly3)
2339 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2340 				      PAD_DS_DLY3, host->hs400_ds_dly3);
2341 	} else {
2342 		sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2343 		if (host->hs400_ds_dly3)
2344 			sdr_set_field(host->base + PAD_DS_TUNE,
2345 				      PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2346 	}
2347 
2348 	host->hs400_tuning = true;
2349 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2350 		if (host->top_base)
2351 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2352 				      PAD_DS_DLY1, i);
2353 		else
2354 			sdr_set_field(host->base + PAD_DS_TUNE,
2355 				      PAD_DS_TUNE_DLY1, i);
2356 		ret = mmc_get_ext_csd(card, &ext_csd);
2357 		if (!ret) {
2358 			result_dly1 |= BIT(i);
2359 			kfree(ext_csd);
2360 		}
2361 	}
2362 	host->hs400_tuning = false;
2363 
2364 	dly1_delay = get_best_delay(host, result_dly1);
2365 	if (dly1_delay.maxlen == 0) {
2366 		dev_err(host->dev, "Failed to get DLY1 delay!\n");
2367 		goto fail;
2368 	}
2369 	if (host->top_base)
2370 		sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2371 			      PAD_DS_DLY1, dly1_delay.final_phase);
2372 	else
2373 		sdr_set_field(host->base + PAD_DS_TUNE,
2374 			      PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2375 
2376 	if (host->top_base)
2377 		val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2378 	else
2379 		val = readl(host->base + PAD_DS_TUNE);
2380 
2381 	dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2382 
2383 	return 0;
2384 
2385 fail:
2386 	dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2387 	return -EIO;
2388 }
2389 
msdc_hw_reset(struct mmc_host * mmc)2390 static void msdc_hw_reset(struct mmc_host *mmc)
2391 {
2392 	struct msdc_host *host = mmc_priv(mmc);
2393 
2394 	sdr_set_bits(host->base + EMMC_IOCON, 1);
2395 	udelay(10); /* 10us is enough */
2396 	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2397 }
2398 
msdc_ack_sdio_irq(struct mmc_host * mmc)2399 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2400 {
2401 	unsigned long flags;
2402 	struct msdc_host *host = mmc_priv(mmc);
2403 
2404 	spin_lock_irqsave(&host->lock, flags);
2405 	__msdc_enable_sdio_irq(host, 1);
2406 	spin_unlock_irqrestore(&host->lock, flags);
2407 }
2408 
msdc_get_cd(struct mmc_host * mmc)2409 static int msdc_get_cd(struct mmc_host *mmc)
2410 {
2411 	struct msdc_host *host = mmc_priv(mmc);
2412 	int val;
2413 
2414 	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2415 		return 1;
2416 
2417 	if (!host->internal_cd)
2418 		return mmc_gpio_get_cd(mmc);
2419 
2420 	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2421 	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2422 		return !!val;
2423 	else
2424 		return !val;
2425 }
2426 
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2427 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2428 				       struct mmc_ios *ios)
2429 {
2430 	struct msdc_host *host = mmc_priv(mmc);
2431 
2432 	if (ios->enhanced_strobe) {
2433 		msdc_prepare_hs400_tuning(mmc, ios);
2434 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2435 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2436 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2437 
2438 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2439 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2440 		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2441 	} else {
2442 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2443 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2444 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2445 
2446 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2447 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2448 		sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2449 	}
2450 }
2451 
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2452 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2453 {
2454 	struct mmc_host *mmc = mmc_from_priv(host);
2455 	struct cqhci_host *cq_host = mmc->cqe_private;
2456 	u8 itcfmul;
2457 	u64 hclk_freq, value;
2458 
2459 	/*
2460 	 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2461 	 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2462 	 * Send Status Command Idle Timer (CIT) value.
2463 	 */
2464 	hclk_freq = (u64)clk_get_rate(host->h_clk);
2465 	itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2466 	switch (itcfmul) {
2467 	case 0x0:
2468 		do_div(hclk_freq, 1000);
2469 		break;
2470 	case 0x1:
2471 		do_div(hclk_freq, 100);
2472 		break;
2473 	case 0x2:
2474 		do_div(hclk_freq, 10);
2475 		break;
2476 	case 0x3:
2477 		break;
2478 	case 0x4:
2479 		hclk_freq = hclk_freq * 10;
2480 		break;
2481 	default:
2482 		host->cq_ssc1_time = 0x40;
2483 		return;
2484 	}
2485 
2486 	value = hclk_freq * timer_ns;
2487 	do_div(value, 1000000000);
2488 	host->cq_ssc1_time = value;
2489 }
2490 
msdc_cqe_enable(struct mmc_host * mmc)2491 static void msdc_cqe_enable(struct mmc_host *mmc)
2492 {
2493 	struct msdc_host *host = mmc_priv(mmc);
2494 	struct cqhci_host *cq_host = mmc->cqe_private;
2495 
2496 	/* enable cmdq irq */
2497 	writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2498 	/* enable busy check */
2499 	sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2500 	/* default write data / busy timeout 20s */
2501 	msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2502 	/* default read data timeout 1s */
2503 	msdc_set_timeout(host, 1000000000ULL, 0);
2504 
2505 	/* Set the send status command idle timer */
2506 	cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2507 }
2508 
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2509 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2510 {
2511 	struct msdc_host *host = mmc_priv(mmc);
2512 	unsigned int val = 0;
2513 
2514 	/* disable cmdq irq */
2515 	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2516 	/* disable busy check */
2517 	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2518 
2519 	val = readl(host->base + MSDC_INT);
2520 	writel(val, host->base + MSDC_INT);
2521 
2522 	if (recovery) {
2523 		sdr_set_field(host->base + MSDC_DMA_CTRL,
2524 			      MSDC_DMA_CTRL_STOP, 1);
2525 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2526 			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2527 			return;
2528 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2529 			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
2530 			return;
2531 		msdc_reset_hw(host);
2532 	}
2533 }
2534 
msdc_cqe_pre_enable(struct mmc_host * mmc)2535 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2536 {
2537 	struct cqhci_host *cq_host = mmc->cqe_private;
2538 	u32 reg;
2539 
2540 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2541 	reg |= CQHCI_ENABLE;
2542 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2543 }
2544 
msdc_cqe_post_disable(struct mmc_host * mmc)2545 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2546 {
2547 	struct cqhci_host *cq_host = mmc->cqe_private;
2548 	u32 reg;
2549 
2550 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2551 	reg &= ~CQHCI_ENABLE;
2552 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2553 }
2554 
2555 static const struct mmc_host_ops mt_msdc_ops = {
2556 	.post_req = msdc_post_req,
2557 	.pre_req = msdc_pre_req,
2558 	.request = msdc_ops_request,
2559 	.set_ios = msdc_ops_set_ios,
2560 	.get_ro = mmc_gpio_get_ro,
2561 	.get_cd = msdc_get_cd,
2562 	.hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2563 	.enable_sdio_irq = msdc_enable_sdio_irq,
2564 	.ack_sdio_irq = msdc_ack_sdio_irq,
2565 	.start_signal_voltage_switch = msdc_ops_switch_volt,
2566 	.card_busy = msdc_card_busy,
2567 	.execute_tuning = msdc_execute_tuning,
2568 	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2569 	.execute_hs400_tuning = msdc_execute_hs400_tuning,
2570 	.card_hw_reset = msdc_hw_reset,
2571 };
2572 
2573 static const struct cqhci_host_ops msdc_cmdq_ops = {
2574 	.enable         = msdc_cqe_enable,
2575 	.disable        = msdc_cqe_disable,
2576 	.pre_enable = msdc_cqe_pre_enable,
2577 	.post_disable = msdc_cqe_post_disable,
2578 };
2579 
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2580 static void msdc_of_property_parse(struct platform_device *pdev,
2581 				   struct msdc_host *host)
2582 {
2583 	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2584 			     &host->latch_ck);
2585 
2586 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2587 			     &host->hs400_ds_delay);
2588 
2589 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2590 			     &host->hs400_ds_dly3);
2591 
2592 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2593 			     &host->hs200_cmd_int_delay);
2594 
2595 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2596 			     &host->hs400_cmd_int_delay);
2597 
2598 	if (of_property_read_bool(pdev->dev.of_node,
2599 				  "mediatek,hs400-cmd-resp-sel-rising"))
2600 		host->hs400_cmd_resp_sel_rising = true;
2601 	else
2602 		host->hs400_cmd_resp_sel_rising = false;
2603 
2604 	if (of_property_read_bool(pdev->dev.of_node,
2605 				  "supports-cqe"))
2606 		host->cqhci = true;
2607 	else
2608 		host->cqhci = false;
2609 }
2610 
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2611 static int msdc_of_clock_parse(struct platform_device *pdev,
2612 			       struct msdc_host *host)
2613 {
2614 	int ret;
2615 
2616 	host->src_clk = devm_clk_get(&pdev->dev, "source");
2617 	if (IS_ERR(host->src_clk))
2618 		return PTR_ERR(host->src_clk);
2619 
2620 	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2621 	if (IS_ERR(host->h_clk))
2622 		return PTR_ERR(host->h_clk);
2623 
2624 	host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2625 	if (IS_ERR(host->bus_clk))
2626 		host->bus_clk = NULL;
2627 
2628 	/*source clock control gate is optional clock*/
2629 	host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2630 	if (IS_ERR(host->src_clk_cg))
2631 		return PTR_ERR(host->src_clk_cg);
2632 
2633 	/*
2634 	 * Fallback for legacy device-trees: src_clk and HCLK use the same
2635 	 * bit to control gating but they are parented to a different mux,
2636 	 * hence if our intention is to gate only the source, required
2637 	 * during a clk mode switch to avoid hw hangs, we need to gate
2638 	 * its parent (specified as a different clock only on new DTs).
2639 	 */
2640 	if (!host->src_clk_cg) {
2641 		host->src_clk_cg = clk_get_parent(host->src_clk);
2642 		if (IS_ERR(host->src_clk_cg))
2643 			return PTR_ERR(host->src_clk_cg);
2644 	}
2645 
2646 	/* If present, always enable for this clock gate */
2647 	host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2648 	if (IS_ERR(host->sys_clk_cg))
2649 		host->sys_clk_cg = NULL;
2650 
2651 	host->bulk_clks[0].id = "pclk_cg";
2652 	host->bulk_clks[1].id = "axi_cg";
2653 	host->bulk_clks[2].id = "ahb_cg";
2654 	ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2655 					 host->bulk_clks);
2656 	if (ret) {
2657 		dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2658 		return ret;
2659 	}
2660 
2661 	return 0;
2662 }
2663 
msdc_drv_probe(struct platform_device * pdev)2664 static int msdc_drv_probe(struct platform_device *pdev)
2665 {
2666 	struct mmc_host *mmc;
2667 	struct msdc_host *host;
2668 	struct resource *res;
2669 	int ret;
2670 
2671 	if (!pdev->dev.of_node) {
2672 		dev_err(&pdev->dev, "No DT found\n");
2673 		return -EINVAL;
2674 	}
2675 
2676 	/* Allocate MMC host for this device */
2677 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2678 	if (!mmc)
2679 		return -ENOMEM;
2680 
2681 	host = mmc_priv(mmc);
2682 	ret = mmc_of_parse(mmc);
2683 	if (ret)
2684 		goto host_free;
2685 
2686 	host->base = devm_platform_ioremap_resource(pdev, 0);
2687 	if (IS_ERR(host->base)) {
2688 		ret = PTR_ERR(host->base);
2689 		goto host_free;
2690 	}
2691 
2692 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2693 	if (res) {
2694 		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2695 		if (IS_ERR(host->top_base))
2696 			host->top_base = NULL;
2697 	}
2698 
2699 	ret = mmc_regulator_get_supply(mmc);
2700 	if (ret)
2701 		goto host_free;
2702 
2703 	ret = msdc_of_clock_parse(pdev, host);
2704 	if (ret)
2705 		goto host_free;
2706 
2707 	host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2708 								"hrst");
2709 	if (IS_ERR(host->reset)) {
2710 		ret = PTR_ERR(host->reset);
2711 		goto host_free;
2712 	}
2713 
2714 	/* only eMMC has crypto property */
2715 	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2716 		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2717 		if (IS_ERR(host->crypto_clk))
2718 			host->crypto_clk = NULL;
2719 		else
2720 			mmc->caps2 |= MMC_CAP2_CRYPTO;
2721 	}
2722 
2723 	host->irq = platform_get_irq(pdev, 0);
2724 	if (host->irq < 0) {
2725 		ret = host->irq;
2726 		goto host_free;
2727 	}
2728 
2729 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2730 	if (IS_ERR(host->pinctrl)) {
2731 		ret = PTR_ERR(host->pinctrl);
2732 		dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2733 		goto host_free;
2734 	}
2735 
2736 	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2737 	if (IS_ERR(host->pins_default)) {
2738 		ret = PTR_ERR(host->pins_default);
2739 		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2740 		goto host_free;
2741 	}
2742 
2743 	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2744 	if (IS_ERR(host->pins_uhs)) {
2745 		ret = PTR_ERR(host->pins_uhs);
2746 		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2747 		goto host_free;
2748 	}
2749 
2750 	/* Support for SDIO eint irq ? */
2751 	if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2752 		host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2753 		if (host->eint_irq > 0) {
2754 			host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2755 			if (IS_ERR(host->pins_eint)) {
2756 				dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2757 				host->pins_eint = NULL;
2758 			} else {
2759 				device_init_wakeup(&pdev->dev, true);
2760 			}
2761 		}
2762 	}
2763 
2764 	msdc_of_property_parse(pdev, host);
2765 
2766 	host->dev = &pdev->dev;
2767 	host->dev_comp = of_device_get_match_data(&pdev->dev);
2768 	host->src_clk_freq = clk_get_rate(host->src_clk);
2769 	/* Set host parameters to mmc */
2770 	mmc->ops = &mt_msdc_ops;
2771 	if (host->dev_comp->clk_div_bits == 8)
2772 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2773 	else
2774 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2775 
2776 	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2777 	    !mmc_can_gpio_cd(mmc) &&
2778 	    host->dev_comp->use_internal_cd) {
2779 		/*
2780 		 * Is removable but no GPIO declared, so
2781 		 * use internal functionality.
2782 		 */
2783 		host->internal_cd = true;
2784 	}
2785 
2786 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2787 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2788 
2789 	mmc->caps |= MMC_CAP_CMD23;
2790 	if (host->cqhci)
2791 		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2792 	/* MMC core transfer sizes tunable parameters */
2793 	mmc->max_segs = MAX_BD_NUM;
2794 	if (host->dev_comp->support_64g)
2795 		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2796 	else
2797 		mmc->max_seg_size = BDMA_DESC_BUFLEN;
2798 	mmc->max_blk_size = 2048;
2799 	mmc->max_req_size = 512 * 1024;
2800 	mmc->max_blk_count = mmc->max_req_size / 512;
2801 	if (host->dev_comp->support_64g)
2802 		host->dma_mask = DMA_BIT_MASK(36);
2803 	else
2804 		host->dma_mask = DMA_BIT_MASK(32);
2805 	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2806 
2807 	host->timeout_clks = 3 * 1048576;
2808 	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2809 				2 * sizeof(struct mt_gpdma_desc),
2810 				&host->dma.gpd_addr, GFP_KERNEL);
2811 	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2812 				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2813 				&host->dma.bd_addr, GFP_KERNEL);
2814 	if (!host->dma.gpd || !host->dma.bd) {
2815 		ret = -ENOMEM;
2816 		goto release_mem;
2817 	}
2818 	msdc_init_gpd_bd(host, &host->dma);
2819 	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2820 	spin_lock_init(&host->lock);
2821 
2822 	platform_set_drvdata(pdev, mmc);
2823 	ret = msdc_ungate_clock(host);
2824 	if (ret) {
2825 		dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2826 		goto release_mem;
2827 	}
2828 	msdc_init_hw(host);
2829 
2830 	if (mmc->caps2 & MMC_CAP2_CQE) {
2831 		host->cq_host = devm_kzalloc(mmc->parent,
2832 					     sizeof(*host->cq_host),
2833 					     GFP_KERNEL);
2834 		if (!host->cq_host) {
2835 			ret = -ENOMEM;
2836 			goto host_free;
2837 		}
2838 		host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2839 		host->cq_host->mmio = host->base + 0x800;
2840 		host->cq_host->ops = &msdc_cmdq_ops;
2841 		ret = cqhci_init(host->cq_host, mmc, true);
2842 		if (ret)
2843 			goto host_free;
2844 		mmc->max_segs = 128;
2845 		/* cqhci 16bit length */
2846 		/* 0 size, means 65536 so we don't have to -1 here */
2847 		mmc->max_seg_size = 64 * 1024;
2848 		/* Reduce CIT to 0x40 that corresponds to 2.35us */
2849 		msdc_cqe_cit_cal(host, 2350);
2850 	}
2851 
2852 	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2853 			       IRQF_TRIGGER_NONE, pdev->name, host);
2854 	if (ret)
2855 		goto release;
2856 
2857 	pm_runtime_set_active(host->dev);
2858 	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2859 	pm_runtime_use_autosuspend(host->dev);
2860 	pm_runtime_enable(host->dev);
2861 	ret = mmc_add_host(mmc);
2862 
2863 	if (ret)
2864 		goto end;
2865 
2866 	return 0;
2867 end:
2868 	pm_runtime_disable(host->dev);
2869 release:
2870 	platform_set_drvdata(pdev, NULL);
2871 	msdc_deinit_hw(host);
2872 	msdc_gate_clock(host);
2873 release_mem:
2874 	if (host->dma.gpd)
2875 		dma_free_coherent(&pdev->dev,
2876 			2 * sizeof(struct mt_gpdma_desc),
2877 			host->dma.gpd, host->dma.gpd_addr);
2878 	if (host->dma.bd)
2879 		dma_free_coherent(&pdev->dev,
2880 			MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2881 			host->dma.bd, host->dma.bd_addr);
2882 host_free:
2883 	mmc_free_host(mmc);
2884 
2885 	return ret;
2886 }
2887 
msdc_drv_remove(struct platform_device * pdev)2888 static void msdc_drv_remove(struct platform_device *pdev)
2889 {
2890 	struct mmc_host *mmc;
2891 	struct msdc_host *host;
2892 
2893 	mmc = platform_get_drvdata(pdev);
2894 	host = mmc_priv(mmc);
2895 
2896 	pm_runtime_get_sync(host->dev);
2897 
2898 	platform_set_drvdata(pdev, NULL);
2899 	mmc_remove_host(mmc);
2900 	msdc_deinit_hw(host);
2901 	msdc_gate_clock(host);
2902 
2903 	pm_runtime_disable(host->dev);
2904 	pm_runtime_put_noidle(host->dev);
2905 	dma_free_coherent(&pdev->dev,
2906 			2 * sizeof(struct mt_gpdma_desc),
2907 			host->dma.gpd, host->dma.gpd_addr);
2908 	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2909 			host->dma.bd, host->dma.bd_addr);
2910 
2911 	mmc_free_host(mmc);
2912 }
2913 
msdc_save_reg(struct msdc_host * host)2914 static void msdc_save_reg(struct msdc_host *host)
2915 {
2916 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2917 
2918 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2919 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2920 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2921 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2922 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2923 	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2924 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2925 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2926 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2927 	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2928 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2929 	if (host->top_base) {
2930 		host->save_para.emmc_top_control =
2931 			readl(host->top_base + EMMC_TOP_CONTROL);
2932 		host->save_para.emmc_top_cmd =
2933 			readl(host->top_base + EMMC_TOP_CMD);
2934 		host->save_para.emmc50_pad_ds_tune =
2935 			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2936 	} else {
2937 		host->save_para.pad_tune = readl(host->base + tune_reg);
2938 	}
2939 }
2940 
msdc_restore_reg(struct msdc_host * host)2941 static void msdc_restore_reg(struct msdc_host *host)
2942 {
2943 	struct mmc_host *mmc = mmc_from_priv(host);
2944 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2945 
2946 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2947 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
2948 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2949 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2950 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2951 	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2952 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2953 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2954 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2955 	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2956 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2957 	if (host->top_base) {
2958 		writel(host->save_para.emmc_top_control,
2959 		       host->top_base + EMMC_TOP_CONTROL);
2960 		writel(host->save_para.emmc_top_cmd,
2961 		       host->top_base + EMMC_TOP_CMD);
2962 		writel(host->save_para.emmc50_pad_ds_tune,
2963 		       host->top_base + EMMC50_PAD_DS_TUNE);
2964 	} else {
2965 		writel(host->save_para.pad_tune, host->base + tune_reg);
2966 	}
2967 
2968 	if (sdio_irq_claimed(mmc))
2969 		__msdc_enable_sdio_irq(host, 1);
2970 }
2971 
msdc_runtime_suspend(struct device * dev)2972 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2973 {
2974 	struct mmc_host *mmc = dev_get_drvdata(dev);
2975 	struct msdc_host *host = mmc_priv(mmc);
2976 
2977 	msdc_save_reg(host);
2978 
2979 	if (sdio_irq_claimed(mmc)) {
2980 		if (host->pins_eint) {
2981 			disable_irq(host->irq);
2982 			pinctrl_select_state(host->pinctrl, host->pins_eint);
2983 		}
2984 
2985 		__msdc_enable_sdio_irq(host, 0);
2986 	}
2987 	msdc_gate_clock(host);
2988 	return 0;
2989 }
2990 
msdc_runtime_resume(struct device * dev)2991 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2992 {
2993 	struct mmc_host *mmc = dev_get_drvdata(dev);
2994 	struct msdc_host *host = mmc_priv(mmc);
2995 	int ret;
2996 
2997 	ret = msdc_ungate_clock(host);
2998 	if (ret)
2999 		return ret;
3000 
3001 	msdc_restore_reg(host);
3002 
3003 	if (sdio_irq_claimed(mmc) && host->pins_eint) {
3004 		pinctrl_select_state(host->pinctrl, host->pins_uhs);
3005 		enable_irq(host->irq);
3006 	}
3007 	return 0;
3008 }
3009 
msdc_suspend(struct device * dev)3010 static int __maybe_unused msdc_suspend(struct device *dev)
3011 {
3012 	struct mmc_host *mmc = dev_get_drvdata(dev);
3013 	struct msdc_host *host = mmc_priv(mmc);
3014 	int ret;
3015 	u32 val;
3016 
3017 	if (mmc->caps2 & MMC_CAP2_CQE) {
3018 		ret = cqhci_suspend(mmc);
3019 		if (ret)
3020 			return ret;
3021 		val = readl(host->base + MSDC_INT);
3022 		writel(val, host->base + MSDC_INT);
3023 	}
3024 
3025 	/*
3026 	 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3027 	 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3028 	 */
3029 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3030 		pm_runtime_get_noresume(dev);
3031 
3032 	return pm_runtime_force_suspend(dev);
3033 }
3034 
msdc_resume(struct device * dev)3035 static int __maybe_unused msdc_resume(struct device *dev)
3036 {
3037 	struct mmc_host *mmc = dev_get_drvdata(dev);
3038 	struct msdc_host *host = mmc_priv(mmc);
3039 
3040 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3041 		pm_runtime_put_noidle(dev);
3042 
3043 	return pm_runtime_force_resume(dev);
3044 }
3045 
3046 static const struct dev_pm_ops msdc_dev_pm_ops = {
3047 	SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3048 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3049 };
3050 
3051 static struct platform_driver mt_msdc_driver = {
3052 	.probe = msdc_drv_probe,
3053 	.remove_new = msdc_drv_remove,
3054 	.driver = {
3055 		.name = "mtk-msdc",
3056 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3057 		.of_match_table = msdc_of_ids,
3058 		.pm = &msdc_dev_pm_ops,
3059 	},
3060 };
3061 
3062 module_platform_driver(mt_msdc_driver);
3063 MODULE_LICENSE("GPL v2");
3064 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3065