1 #ifndef MIPS_CPU_H
2 #define MIPS_CPU_H
3
4 #include "cpu-qom.h"
5 #include "exec/cpu-defs.h"
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/memory.h"
8 #endif
9 #include "fpu/softfloat-types.h"
10 #include "hw/clock.h"
11 #include "mips-defs.h"
12
13 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
14
15 /* MSA Context */
16 #define MSA_WRLEN (128)
17
18 typedef union wr_t wr_t;
19 union wr_t {
20 int8_t b[MSA_WRLEN / 8];
21 int16_t h[MSA_WRLEN / 16];
22 int32_t w[MSA_WRLEN / 32];
23 int64_t d[MSA_WRLEN / 64];
24 };
25
26 typedef union fpr_t fpr_t;
27 union fpr_t {
28 float64 fd; /* ieee double precision */
29 float32 fs[2];/* ieee single precision */
30 uint64_t d; /* binary double fixed-point */
31 uint32_t w[2]; /* binary single fixed-point */
32 /* FPU/MSA register mapping is not tested on big-endian hosts. */
33 wr_t wr; /* vector data */
34 };
35 /*
36 *define FP_ENDIAN_IDX to access the same location
37 * in the fpr_t union regardless of the host endianness
38 */
39 #if HOST_BIG_ENDIAN
40 # define FP_ENDIAN_IDX 1
41 #else
42 # define FP_ENDIAN_IDX 0
43 #endif
44
45 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
46 struct CPUMIPSFPUContext {
47 /* Floating point registers */
48 fpr_t fpr[32];
49 float_status fp_status;
50 /* fpu implementation/revision register (fir) */
51 uint32_t fcr0;
52 #define FCR0_FREP 29
53 #define FCR0_UFRP 28
54 #define FCR0_HAS2008 23
55 #define FCR0_F64 22
56 #define FCR0_L 21
57 #define FCR0_W 20
58 #define FCR0_3D 19
59 #define FCR0_PS 18
60 #define FCR0_D 17
61 #define FCR0_S 16
62 #define FCR0_PRID 8
63 #define FCR0_REV 0
64 /* fcsr */
65 uint32_t fcr31_rw_bitmask;
66 uint32_t fcr31;
67 #define FCR31_FS 24
68 #define FCR31_ABS2008 19
69 #define FCR31_NAN2008 18
70 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \
71 ((num) ? (1 << ((num) + 24)) : \
72 (1 << 23)); \
73 } while (0)
74 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
75 ~((num) ? (1 << ((num) + 24)) : \
76 (1 << 23)); \
77 } while (0)
78 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
79 (((env).fcr31 >> 23) & 0x1))
80 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
81 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
82 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
83 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
84 ((v & 0x3f) << 12); \
85 } while (0)
86 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
87 ((v & 0x1f) << 7); \
88 } while (0)
89 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
90 ((v & 0x1f) << 2); \
91 } while (0)
92 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
93 #define FP_INEXACT 1
94 #define FP_UNDERFLOW 2
95 #define FP_OVERFLOW 4
96 #define FP_DIV0 8
97 #define FP_INVALID 16
98 #define FP_UNIMPLEMENTED 32
99 };
100
101 #define TARGET_INSN_START_EXTRA_WORDS 2
102
103 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
104 struct CPUMIPSMVPContext {
105 int32_t CP0_MVPControl;
106 #define CP0MVPCo_CPA 3
107 #define CP0MVPCo_STLB 2
108 #define CP0MVPCo_VPC 1
109 #define CP0MVPCo_EVP 0
110 int32_t CP0_MVPConf0;
111 #define CP0MVPC0_M 31
112 #define CP0MVPC0_TLBS 29
113 #define CP0MVPC0_GS 28
114 #define CP0MVPC0_PCP 27
115 #define CP0MVPC0_PTLBE 16
116 #define CP0MVPC0_TCA 15
117 #define CP0MVPC0_PVPE 10
118 #define CP0MVPC0_PTC 0
119 int32_t CP0_MVPConf1;
120 #define CP0MVPC1_CIM 31
121 #define CP0MVPC1_CIF 30
122 #define CP0MVPC1_PCX 20
123 #define CP0MVPC1_PCP2 10
124 #define CP0MVPC1_PCP1 0
125 };
126
127 typedef struct mips_def_t mips_def_t;
128
129 #define MIPS_SHADOW_SET_MAX 16
130 #define MIPS_TC_MAX 5
131 #define MIPS_FPU_MAX 1
132 #define MIPS_DSP_ACC 4
133 #define MIPS_KSCRATCH_NUM 6
134 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
135
136
137 /*
138 * Summary of CP0 registers
139 * ========================
140 *
141 *
142 * Register 0 Register 1 Register 2 Register 3
143 * ---------- ---------- ---------- ----------
144 *
145 * 0 Index Random EntryLo0 EntryLo1
146 * 1 MVPControl VPEControl TCStatus GlobalNumber
147 * 2 MVPConf0 VPEConf0 TCBind
148 * 3 MVPConf1 VPEConf1 TCRestart
149 * 4 VPControl YQMask TCHalt
150 * 5 VPESchedule TCContext
151 * 6 VPEScheFBack TCSchedule
152 * 7 VPEOpt TCScheFBack TCOpt
153 *
154 *
155 * Register 4 Register 5 Register 6 Register 7
156 * ---------- ---------- ---------- ----------
157 *
158 * 0 Context PageMask Wired HWREna
159 * 1 ContextConfig PageGrain SRSConf0
160 * 2 UserLocal SegCtl0 SRSConf1
161 * 3 XContextConfig SegCtl1 SRSConf2
162 * 4 DebugContextID SegCtl2 SRSConf3
163 * 5 MemoryMapID PWBase SRSConf4
164 * 6 PWField PWCtl
165 * 7 PWSize
166 *
167 *
168 * Register 8 Register 9 Register 10 Register 11
169 * ---------- ---------- ----------- -----------
170 *
171 * 0 BadVAddr Count EntryHi Compare
172 * 1 BadInstr
173 * 2 BadInstrP
174 * 3 BadInstrX
175 * 4 GuestCtl1 GuestCtl0Ext
176 * 5 GuestCtl2
177 * 6 SAARI GuestCtl3
178 * 7 SAAR
179 *
180 *
181 * Register 12 Register 13 Register 14 Register 15
182 * ----------- ----------- ----------- -----------
183 *
184 * 0 Status Cause EPC PRId
185 * 1 IntCtl EBase
186 * 2 SRSCtl NestedEPC CDMMBase
187 * 3 SRSMap CMGCRBase
188 * 4 View_IPL View_RIPL BEVVA
189 * 5 SRSMap2 NestedExc
190 * 6 GuestCtl0
191 * 7 GTOffset
192 *
193 *
194 * Register 16 Register 17 Register 18 Register 19
195 * ----------- ----------- ----------- -----------
196 *
197 * 0 Config LLAddr WatchLo0 WatchHi
198 * 1 Config1 MAAR WatchLo1 WatchHi
199 * 2 Config2 MAARI WatchLo2 WatchHi
200 * 3 Config3 WatchLo3 WatchHi
201 * 4 Config4 WatchLo4 WatchHi
202 * 5 Config5 WatchLo5 WatchHi
203 * 6 Config6 WatchLo6 WatchHi
204 * 7 Config7 WatchLo7 WatchHi
205 *
206 *
207 * Register 20 Register 21 Register 22 Register 23
208 * ----------- ----------- ----------- -----------
209 *
210 * 0 XContext Debug
211 * 1 TraceControl
212 * 2 TraceControl2
213 * 3 UserTraceData1
214 * 4 TraceIBPC
215 * 5 TraceDBPC
216 * 6 Debug2
217 * 7
218 *
219 *
220 * Register 24 Register 25 Register 26 Register 27
221 * ----------- ----------- ----------- -----------
222 *
223 * 0 DEPC PerfCnt ErrCtl CacheErr
224 * 1 PerfCnt
225 * 2 TraceControl3 PerfCnt
226 * 3 UserTraceData2 PerfCnt
227 * 4 PerfCnt
228 * 5 PerfCnt
229 * 6 PerfCnt
230 * 7 PerfCnt
231 *
232 *
233 * Register 28 Register 29 Register 30 Register 31
234 * ----------- ----------- ----------- -----------
235 *
236 * 0 DataLo DataHi ErrorEPC DESAVE
237 * 1 TagLo TagHi
238 * 2 DataLo1 DataHi1 KScratch<n>
239 * 3 TagLo1 TagHi1 KScratch<n>
240 * 4 DataLo2 DataHi2 KScratch<n>
241 * 5 TagLo2 TagHi2 KScratch<n>
242 * 6 DataLo3 DataHi3 KScratch<n>
243 * 7 TagLo3 TagHi3 KScratch<n>
244 *
245 */
246 #define CP0_REGISTER_00 0
247 #define CP0_REGISTER_01 1
248 #define CP0_REGISTER_02 2
249 #define CP0_REGISTER_03 3
250 #define CP0_REGISTER_04 4
251 #define CP0_REGISTER_05 5
252 #define CP0_REGISTER_06 6
253 #define CP0_REGISTER_07 7
254 #define CP0_REGISTER_08 8
255 #define CP0_REGISTER_09 9
256 #define CP0_REGISTER_10 10
257 #define CP0_REGISTER_11 11
258 #define CP0_REGISTER_12 12
259 #define CP0_REGISTER_13 13
260 #define CP0_REGISTER_14 14
261 #define CP0_REGISTER_15 15
262 #define CP0_REGISTER_16 16
263 #define CP0_REGISTER_17 17
264 #define CP0_REGISTER_18 18
265 #define CP0_REGISTER_19 19
266 #define CP0_REGISTER_20 20
267 #define CP0_REGISTER_21 21
268 #define CP0_REGISTER_22 22
269 #define CP0_REGISTER_23 23
270 #define CP0_REGISTER_24 24
271 #define CP0_REGISTER_25 25
272 #define CP0_REGISTER_26 26
273 #define CP0_REGISTER_27 27
274 #define CP0_REGISTER_28 28
275 #define CP0_REGISTER_29 29
276 #define CP0_REGISTER_30 30
277 #define CP0_REGISTER_31 31
278
279
280 /* CP0 Register 00 */
281 #define CP0_REG00__INDEX 0
282 #define CP0_REG00__MVPCONTROL 1
283 #define CP0_REG00__MVPCONF0 2
284 #define CP0_REG00__MVPCONF1 3
285 #define CP0_REG00__VPCONTROL 4
286 /* CP0 Register 01 */
287 #define CP0_REG01__RANDOM 0
288 #define CP0_REG01__VPECONTROL 1
289 #define CP0_REG01__VPECONF0 2
290 #define CP0_REG01__VPECONF1 3
291 #define CP0_REG01__YQMASK 4
292 #define CP0_REG01__VPESCHEDULE 5
293 #define CP0_REG01__VPESCHEFBACK 6
294 #define CP0_REG01__VPEOPT 7
295 /* CP0 Register 02 */
296 #define CP0_REG02__ENTRYLO0 0
297 #define CP0_REG02__TCSTATUS 1
298 #define CP0_REG02__TCBIND 2
299 #define CP0_REG02__TCRESTART 3
300 #define CP0_REG02__TCHALT 4
301 #define CP0_REG02__TCCONTEXT 5
302 #define CP0_REG02__TCSCHEDULE 6
303 #define CP0_REG02__TCSCHEFBACK 7
304 /* CP0 Register 03 */
305 #define CP0_REG03__ENTRYLO1 0
306 #define CP0_REG03__GLOBALNUM 1
307 #define CP0_REG03__TCOPT 7
308 /* CP0 Register 04 */
309 #define CP0_REG04__CONTEXT 0
310 #define CP0_REG04__CONTEXTCONFIG 1
311 #define CP0_REG04__USERLOCAL 2
312 #define CP0_REG04__XCONTEXTCONFIG 3
313 #define CP0_REG04__DBGCONTEXTID 4
314 #define CP0_REG04__MMID 5
315 /* CP0 Register 05 */
316 #define CP0_REG05__PAGEMASK 0
317 #define CP0_REG05__PAGEGRAIN 1
318 #define CP0_REG05__SEGCTL0 2
319 #define CP0_REG05__SEGCTL1 3
320 #define CP0_REG05__SEGCTL2 4
321 #define CP0_REG05__PWBASE 5
322 #define CP0_REG05__PWFIELD 6
323 #define CP0_REG05__PWSIZE 7
324 /* CP0 Register 06 */
325 #define CP0_REG06__WIRED 0
326 #define CP0_REG06__SRSCONF0 1
327 #define CP0_REG06__SRSCONF1 2
328 #define CP0_REG06__SRSCONF2 3
329 #define CP0_REG06__SRSCONF3 4
330 #define CP0_REG06__SRSCONF4 5
331 #define CP0_REG06__PWCTL 6
332 /* CP0 Register 07 */
333 #define CP0_REG07__HWRENA 0
334 /* CP0 Register 08 */
335 #define CP0_REG08__BADVADDR 0
336 #define CP0_REG08__BADINSTR 1
337 #define CP0_REG08__BADINSTRP 2
338 #define CP0_REG08__BADINSTRX 3
339 /* CP0 Register 09 */
340 #define CP0_REG09__COUNT 0
341 #define CP0_REG09__SAARI 6
342 #define CP0_REG09__SAAR 7
343 /* CP0 Register 10 */
344 #define CP0_REG10__ENTRYHI 0
345 #define CP0_REG10__GUESTCTL1 4
346 #define CP0_REG10__GUESTCTL2 5
347 #define CP0_REG10__GUESTCTL3 6
348 /* CP0 Register 11 */
349 #define CP0_REG11__COMPARE 0
350 #define CP0_REG11__GUESTCTL0EXT 4
351 /* CP0 Register 12 */
352 #define CP0_REG12__STATUS 0
353 #define CP0_REG12__INTCTL 1
354 #define CP0_REG12__SRSCTL 2
355 #define CP0_REG12__SRSMAP 3
356 #define CP0_REG12__VIEW_IPL 4
357 #define CP0_REG12__SRSMAP2 5
358 #define CP0_REG12__GUESTCTL0 6
359 #define CP0_REG12__GTOFFSET 7
360 /* CP0 Register 13 */
361 #define CP0_REG13__CAUSE 0
362 #define CP0_REG13__VIEW_RIPL 4
363 #define CP0_REG13__NESTEDEXC 5
364 /* CP0 Register 14 */
365 #define CP0_REG14__EPC 0
366 #define CP0_REG14__NESTEDEPC 2
367 /* CP0 Register 15 */
368 #define CP0_REG15__PRID 0
369 #define CP0_REG15__EBASE 1
370 #define CP0_REG15__CDMMBASE 2
371 #define CP0_REG15__CMGCRBASE 3
372 #define CP0_REG15__BEVVA 4
373 /* CP0 Register 16 */
374 #define CP0_REG16__CONFIG 0
375 #define CP0_REG16__CONFIG1 1
376 #define CP0_REG16__CONFIG2 2
377 #define CP0_REG16__CONFIG3 3
378 #define CP0_REG16__CONFIG4 4
379 #define CP0_REG16__CONFIG5 5
380 #define CP0_REG16__CONFIG6 6
381 #define CP0_REG16__CONFIG7 7
382 /* CP0 Register 17 */
383 #define CP0_REG17__LLADDR 0
384 #define CP0_REG17__MAAR 1
385 #define CP0_REG17__MAARI 2
386 /* CP0 Register 18 */
387 #define CP0_REG18__WATCHLO0 0
388 #define CP0_REG18__WATCHLO1 1
389 #define CP0_REG18__WATCHLO2 2
390 #define CP0_REG18__WATCHLO3 3
391 #define CP0_REG18__WATCHLO4 4
392 #define CP0_REG18__WATCHLO5 5
393 #define CP0_REG18__WATCHLO6 6
394 #define CP0_REG18__WATCHLO7 7
395 /* CP0 Register 19 */
396 #define CP0_REG19__WATCHHI0 0
397 #define CP0_REG19__WATCHHI1 1
398 #define CP0_REG19__WATCHHI2 2
399 #define CP0_REG19__WATCHHI3 3
400 #define CP0_REG19__WATCHHI4 4
401 #define CP0_REG19__WATCHHI5 5
402 #define CP0_REG19__WATCHHI6 6
403 #define CP0_REG19__WATCHHI7 7
404 /* CP0 Register 20 */
405 #define CP0_REG20__XCONTEXT 0
406 /* CP0 Register 21 */
407 /* CP0 Register 22 */
408 /* CP0 Register 23 */
409 #define CP0_REG23__DEBUG 0
410 #define CP0_REG23__TRACECONTROL 1
411 #define CP0_REG23__TRACECONTROL2 2
412 #define CP0_REG23__USERTRACEDATA1 3
413 #define CP0_REG23__TRACEIBPC 4
414 #define CP0_REG23__TRACEDBPC 5
415 #define CP0_REG23__DEBUG2 6
416 /* CP0 Register 24 */
417 #define CP0_REG24__DEPC 0
418 /* CP0 Register 25 */
419 #define CP0_REG25__PERFCTL0 0
420 #define CP0_REG25__PERFCNT0 1
421 #define CP0_REG25__PERFCTL1 2
422 #define CP0_REG25__PERFCNT1 3
423 #define CP0_REG25__PERFCTL2 4
424 #define CP0_REG25__PERFCNT2 5
425 #define CP0_REG25__PERFCTL3 6
426 #define CP0_REG25__PERFCNT3 7
427 /* CP0 Register 26 */
428 #define CP0_REG26__ERRCTL 0
429 /* CP0 Register 27 */
430 #define CP0_REG27__CACHERR 0
431 /* CP0 Register 28 */
432 #define CP0_REG28__TAGLO 0
433 #define CP0_REG28__DATALO 1
434 #define CP0_REG28__TAGLO1 2
435 #define CP0_REG28__DATALO1 3
436 #define CP0_REG28__TAGLO2 4
437 #define CP0_REG28__DATALO2 5
438 #define CP0_REG28__TAGLO3 6
439 #define CP0_REG28__DATALO3 7
440 /* CP0 Register 29 */
441 #define CP0_REG29__TAGHI 0
442 #define CP0_REG29__DATAHI 1
443 #define CP0_REG29__TAGHI1 2
444 #define CP0_REG29__DATAHI1 3
445 #define CP0_REG29__TAGHI2 4
446 #define CP0_REG29__DATAHI2 5
447 #define CP0_REG29__TAGHI3 6
448 #define CP0_REG29__DATAHI3 7
449 /* CP0 Register 30 */
450 #define CP0_REG30__ERROREPC 0
451 /* CP0 Register 31 */
452 #define CP0_REG31__DESAVE 0
453 #define CP0_REG31__KSCRATCH1 2
454 #define CP0_REG31__KSCRATCH2 3
455 #define CP0_REG31__KSCRATCH3 4
456 #define CP0_REG31__KSCRATCH4 5
457 #define CP0_REG31__KSCRATCH5 6
458 #define CP0_REG31__KSCRATCH6 7
459
460
461 typedef struct TCState TCState;
462 struct TCState {
463 target_ulong gpr[32];
464 #if defined(TARGET_MIPS64)
465 /*
466 * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
467 * and the upper halves in gpr_hi[].
468 */
469 uint64_t gpr_hi[32];
470 #endif /* TARGET_MIPS64 */
471 target_ulong PC;
472 target_ulong HI[MIPS_DSP_ACC];
473 target_ulong LO[MIPS_DSP_ACC];
474 target_ulong ACX[MIPS_DSP_ACC];
475 target_ulong DSPControl;
476 int32_t CP0_TCStatus;
477 #define CP0TCSt_TCU3 31
478 #define CP0TCSt_TCU2 30
479 #define CP0TCSt_TCU1 29
480 #define CP0TCSt_TCU0 28
481 #define CP0TCSt_TMX 27
482 #define CP0TCSt_RNST 23
483 #define CP0TCSt_TDS 21
484 #define CP0TCSt_DT 20
485 #define CP0TCSt_DA 15
486 #define CP0TCSt_A 13
487 #define CP0TCSt_TKSU 11
488 #define CP0TCSt_IXMT 10
489 #define CP0TCSt_TASID 0
490 int32_t CP0_TCBind;
491 #define CP0TCBd_CurTC 21
492 #define CP0TCBd_TBE 17
493 #define CP0TCBd_CurVPE 0
494 target_ulong CP0_TCHalt;
495 target_ulong CP0_TCContext;
496 target_ulong CP0_TCSchedule;
497 target_ulong CP0_TCScheFBack;
498 int32_t CP0_Debug_tcstatus;
499 target_ulong CP0_UserLocal;
500
501 int32_t msacsr;
502
503 #define MSACSR_FS 24
504 #define MSACSR_FS_MASK (1 << MSACSR_FS)
505 #define MSACSR_NX 18
506 #define MSACSR_NX_MASK (1 << MSACSR_NX)
507 #define MSACSR_CEF 2
508 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
509 #define MSACSR_RM 0
510 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
511 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
512 MSACSR_FS_MASK)
513
514 float_status msa_fp_status;
515
516 #define NUMBER_OF_MXU_REGISTERS 16
517 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
518 target_ulong mxu_cr;
519 #define MXU_CR_LC 31
520 #define MXU_CR_RC 30
521 #define MXU_CR_BIAS 2
522 #define MXU_CR_RD_EN 1
523 #define MXU_CR_MXU_EN 0
524
525 };
526
527 struct MIPSITUState;
528 typedef struct CPUArchState {
529 TCState active_tc;
530 CPUMIPSFPUContext active_fpu;
531
532 uint32_t current_tc;
533 uint32_t current_fpu;
534
535 uint32_t SEGBITS;
536 uint32_t PABITS;
537 #if defined(TARGET_MIPS64)
538 # define PABITS_BASE 36
539 #else
540 # define PABITS_BASE 32
541 #endif
542 target_ulong SEGMask;
543 uint64_t PAMask;
544 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
545
546 int32_t msair;
547 #define MSAIR_ProcID 8
548 #define MSAIR_Rev 0
549
550 /*
551 * CP0 Register 0
552 */
553 int32_t CP0_Index;
554 /* CP0_MVP* are per MVP registers. */
555 int32_t CP0_VPControl;
556 #define CP0VPCtl_DIS 0
557 /*
558 * CP0 Register 1
559 */
560 int32_t CP0_Random;
561 int32_t CP0_VPEControl;
562 #define CP0VPECo_YSI 21
563 #define CP0VPECo_GSI 20
564 #define CP0VPECo_EXCPT 16
565 #define CP0VPECo_TE 15
566 #define CP0VPECo_TargTC 0
567 int32_t CP0_VPEConf0;
568 #define CP0VPEC0_M 31
569 #define CP0VPEC0_XTC 21
570 #define CP0VPEC0_TCS 19
571 #define CP0VPEC0_SCS 18
572 #define CP0VPEC0_DSC 17
573 #define CP0VPEC0_ICS 16
574 #define CP0VPEC0_MVP 1
575 #define CP0VPEC0_VPA 0
576 int32_t CP0_VPEConf1;
577 #define CP0VPEC1_NCX 20
578 #define CP0VPEC1_NCP2 10
579 #define CP0VPEC1_NCP1 0
580 target_ulong CP0_YQMask;
581 target_ulong CP0_VPESchedule;
582 target_ulong CP0_VPEScheFBack;
583 int32_t CP0_VPEOpt;
584 #define CP0VPEOpt_IWX7 15
585 #define CP0VPEOpt_IWX6 14
586 #define CP0VPEOpt_IWX5 13
587 #define CP0VPEOpt_IWX4 12
588 #define CP0VPEOpt_IWX3 11
589 #define CP0VPEOpt_IWX2 10
590 #define CP0VPEOpt_IWX1 9
591 #define CP0VPEOpt_IWX0 8
592 #define CP0VPEOpt_DWX7 7
593 #define CP0VPEOpt_DWX6 6
594 #define CP0VPEOpt_DWX5 5
595 #define CP0VPEOpt_DWX4 4
596 #define CP0VPEOpt_DWX3 3
597 #define CP0VPEOpt_DWX2 2
598 #define CP0VPEOpt_DWX1 1
599 #define CP0VPEOpt_DWX0 0
600 /*
601 * CP0 Register 2
602 */
603 uint64_t CP0_EntryLo0;
604 /*
605 * CP0 Register 3
606 */
607 uint64_t CP0_EntryLo1;
608 #if defined(TARGET_MIPS64)
609 # define CP0EnLo_RI 63
610 # define CP0EnLo_XI 62
611 #else
612 # define CP0EnLo_RI 31
613 # define CP0EnLo_XI 30
614 #endif
615 int32_t CP0_GlobalNumber;
616 #define CP0GN_VPId 0
617 /*
618 * CP0 Register 4
619 */
620 target_ulong CP0_Context;
621 int32_t CP0_MemoryMapID;
622 /*
623 * CP0 Register 5
624 */
625 int32_t CP0_PageMask;
626 #define CP0PM_MASK 13
627 int32_t CP0_PageGrain_rw_bitmask;
628 int32_t CP0_PageGrain;
629 #define CP0PG_RIE 31
630 #define CP0PG_XIE 30
631 #define CP0PG_ELPA 29
632 #define CP0PG_IEC 27
633 target_ulong CP0_SegCtl0;
634 target_ulong CP0_SegCtl1;
635 target_ulong CP0_SegCtl2;
636 #define CP0SC_PA 9
637 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
638 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
639 #define CP0SC_AM 4
640 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
641 #define CP0SC_AM_UK 0ULL
642 #define CP0SC_AM_MK 1ULL
643 #define CP0SC_AM_MSK 2ULL
644 #define CP0SC_AM_MUSK 3ULL
645 #define CP0SC_AM_MUSUK 4ULL
646 #define CP0SC_AM_USK 5ULL
647 #define CP0SC_AM_UUSK 7ULL
648 #define CP0SC_EU 3
649 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
650 #define CP0SC_C 0
651 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
652 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
653 CP0SC_PA_MASK)
654 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
655 CP0SC_PA_1GMASK)
656 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
657 #define CP0SC1_XAM 59
658 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
659 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
660 #define CP0SC2_XR 56
661 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
662 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
663 target_ulong CP0_PWBase;
664 target_ulong CP0_PWField;
665 #if defined(TARGET_MIPS64)
666 #define CP0PF_BDI 32 /* 37..32 */
667 #define CP0PF_GDI 24 /* 29..24 */
668 #define CP0PF_UDI 18 /* 23..18 */
669 #define CP0PF_MDI 12 /* 17..12 */
670 #define CP0PF_PTI 6 /* 11..6 */
671 #define CP0PF_PTEI 0 /* 5..0 */
672 #else
673 #define CP0PF_GDW 24 /* 29..24 */
674 #define CP0PF_UDW 18 /* 23..18 */
675 #define CP0PF_MDW 12 /* 17..12 */
676 #define CP0PF_PTW 6 /* 11..6 */
677 #define CP0PF_PTEW 0 /* 5..0 */
678 #endif
679 target_ulong CP0_PWSize;
680 #if defined(TARGET_MIPS64)
681 #define CP0PS_BDW 32 /* 37..32 */
682 #endif
683 #define CP0PS_PS 30
684 #define CP0PS_GDW 24 /* 29..24 */
685 #define CP0PS_UDW 18 /* 23..18 */
686 #define CP0PS_MDW 12 /* 17..12 */
687 #define CP0PS_PTW 6 /* 11..6 */
688 #define CP0PS_PTEW 0 /* 5..0 */
689 /*
690 * CP0 Register 6
691 */
692 int32_t CP0_Wired;
693 int32_t CP0_PWCtl;
694 #define CP0PC_PWEN 31
695 #if defined(TARGET_MIPS64)
696 #define CP0PC_PWDIREXT 30
697 #define CP0PC_XK 28
698 #define CP0PC_XS 27
699 #define CP0PC_XU 26
700 #endif
701 #define CP0PC_DPH 7
702 #define CP0PC_HUGEPG 6
703 #define CP0PC_PSN 0 /* 5..0 */
704 int32_t CP0_SRSConf0_rw_bitmask;
705 int32_t CP0_SRSConf0;
706 #define CP0SRSC0_M 31
707 #define CP0SRSC0_SRS3 20
708 #define CP0SRSC0_SRS2 10
709 #define CP0SRSC0_SRS1 0
710 int32_t CP0_SRSConf1_rw_bitmask;
711 int32_t CP0_SRSConf1;
712 #define CP0SRSC1_M 31
713 #define CP0SRSC1_SRS6 20
714 #define CP0SRSC1_SRS5 10
715 #define CP0SRSC1_SRS4 0
716 int32_t CP0_SRSConf2_rw_bitmask;
717 int32_t CP0_SRSConf2;
718 #define CP0SRSC2_M 31
719 #define CP0SRSC2_SRS9 20
720 #define CP0SRSC2_SRS8 10
721 #define CP0SRSC2_SRS7 0
722 int32_t CP0_SRSConf3_rw_bitmask;
723 int32_t CP0_SRSConf3;
724 #define CP0SRSC3_M 31
725 #define CP0SRSC3_SRS12 20
726 #define CP0SRSC3_SRS11 10
727 #define CP0SRSC3_SRS10 0
728 int32_t CP0_SRSConf4_rw_bitmask;
729 int32_t CP0_SRSConf4;
730 #define CP0SRSC4_SRS15 20
731 #define CP0SRSC4_SRS14 10
732 #define CP0SRSC4_SRS13 0
733 /*
734 * CP0 Register 7
735 */
736 int32_t CP0_HWREna;
737 /*
738 * CP0 Register 8
739 */
740 target_ulong CP0_BadVAddr;
741 uint32_t CP0_BadInstr;
742 uint32_t CP0_BadInstrP;
743 uint32_t CP0_BadInstrX;
744 /*
745 * CP0 Register 9
746 */
747 int32_t CP0_Count;
748 #define CP0SAARI_TARGET 0 /* 5..0 */
749 #define CP0SAAR_BASE 12 /* 43..12 */
750 #define CP0SAAR_SIZE 1 /* 5..1 */
751 #define CP0SAAR_EN 0
752 /*
753 * CP0 Register 10
754 */
755 target_ulong CP0_EntryHi;
756 #define CP0EnHi_EHINV 10
757 target_ulong CP0_EntryHi_ASID_mask;
758 /*
759 * CP0 Register 11
760 */
761 int32_t CP0_Compare;
762 /*
763 * CP0 Register 12
764 */
765 int32_t CP0_Status;
766 #define CP0St_CU3 31
767 #define CP0St_CU2 30
768 #define CP0St_CU1 29
769 #define CP0St_CU0 28
770 #define CP0St_RP 27
771 #define CP0St_FR 26
772 #define CP0St_RE 25
773 #define CP0St_MX 24
774 #define CP0St_PX 23
775 #define CP0St_BEV 22
776 #define CP0St_TS 21
777 #define CP0St_SR 20
778 #define CP0St_NMI 19
779 #define CP0St_IM 8
780 #define CP0St_KX 7
781 #define CP0St_SX 6
782 #define CP0St_UX 5
783 #define CP0St_KSU 3
784 #define CP0St_ERL 2
785 #define CP0St_EXL 1
786 #define CP0St_IE 0
787 int32_t CP0_IntCtl;
788 #define CP0IntCtl_IPTI 29
789 #define CP0IntCtl_IPPCI 26
790 #define CP0IntCtl_VS 5
791 int32_t CP0_SRSCtl;
792 #define CP0SRSCtl_HSS 26
793 #define CP0SRSCtl_EICSS 18
794 #define CP0SRSCtl_ESS 12
795 #define CP0SRSCtl_PSS 6
796 #define CP0SRSCtl_CSS 0
797 int32_t CP0_SRSMap;
798 #define CP0SRSMap_SSV7 28
799 #define CP0SRSMap_SSV6 24
800 #define CP0SRSMap_SSV5 20
801 #define CP0SRSMap_SSV4 16
802 #define CP0SRSMap_SSV3 12
803 #define CP0SRSMap_SSV2 8
804 #define CP0SRSMap_SSV1 4
805 #define CP0SRSMap_SSV0 0
806 /*
807 * CP0 Register 13
808 */
809 int32_t CP0_Cause;
810 #define CP0Ca_BD 31
811 #define CP0Ca_TI 30
812 #define CP0Ca_CE 28
813 #define CP0Ca_DC 27
814 #define CP0Ca_PCI 26
815 #define CP0Ca_IV 23
816 #define CP0Ca_WP 22
817 #define CP0Ca_IP 8
818 #define CP0Ca_IP_mask 0x0000FF00
819 #define CP0Ca_EC 2
820 /*
821 * CP0 Register 14
822 */
823 target_ulong CP0_EPC;
824 /*
825 * CP0 Register 15
826 */
827 int32_t CP0_PRid;
828 target_ulong CP0_EBase;
829 target_ulong CP0_EBaseWG_rw_bitmask;
830 #define CP0EBase_WG 11
831 target_ulong CP0_CMGCRBase;
832 /*
833 * CP0 Register 16 (after Release 1)
834 */
835 int32_t CP0_Config0;
836 #define CP0C0_M 31
837 #define CP0C0_K23 28 /* 30..28 */
838 #define CP0C0_KU 25 /* 27..25 */
839 #define CP0C0_MDU 20
840 #define CP0C0_MM 18
841 #define CP0C0_BM 16
842 #define CP0C0_Impl 16 /* 24..16 */
843 #define CP0C0_BE 15
844 #define CP0C0_AT 13 /* 14..13 */
845 #define CP0C0_AR 10 /* 12..10 */
846 #define CP0C0_MT 7 /* 9..7 */
847 #define CP0C0_VI 3
848 #define CP0C0_K0 0 /* 2..0 */
849 #define CP0C0_AR_LENGTH 3
850 /*
851 * CP0 Register 16 (before Release 1)
852 */
853 #define CP0C0_Impl 16 /* 24..16 */
854 #define CP0C0_IC 9 /* 11..9 */
855 #define CP0C0_DC 6 /* 8..6 */
856 #define CP0C0_IB 5
857 #define CP0C0_DB 4
858 int32_t CP0_Config1;
859 #define CP0C1_M 31
860 #define CP0C1_MMU 25 /* 30..25 */
861 #define CP0C1_IS 22 /* 24..22 */
862 #define CP0C1_IL 19 /* 21..19 */
863 #define CP0C1_IA 16 /* 18..16 */
864 #define CP0C1_DS 13 /* 15..13 */
865 #define CP0C1_DL 10 /* 12..10 */
866 #define CP0C1_DA 7 /* 9..7 */
867 #define CP0C1_C2 6
868 #define CP0C1_MD 5
869 #define CP0C1_PC 4
870 #define CP0C1_WR 3
871 #define CP0C1_CA 2
872 #define CP0C1_EP 1
873 #define CP0C1_FP 0
874 int32_t CP0_Config2;
875 #define CP0C2_M 31
876 #define CP0C2_TU 28 /* 30..28 */
877 #define CP0C2_TS 24 /* 27..24 */
878 #define CP0C2_TL 20 /* 23..20 */
879 #define CP0C2_TA 16 /* 19..16 */
880 #define CP0C2_SU 12 /* 15..12 */
881 #define CP0C2_SS 8 /* 11..8 */
882 #define CP0C2_SL 4 /* 7..4 */
883 #define CP0C2_SA 0 /* 3..0 */
884 int32_t CP0_Config3;
885 #define CP0C3_M 31
886 #define CP0C3_BPG 30
887 #define CP0C3_CMGCR 29
888 #define CP0C3_MSAP 28
889 #define CP0C3_BP 27
890 #define CP0C3_BI 26
891 #define CP0C3_SC 25
892 #define CP0C3_PW 24
893 #define CP0C3_VZ 23
894 #define CP0C3_IPLV 21 /* 22..21 */
895 #define CP0C3_MMAR 18 /* 20..18 */
896 #define CP0C3_MCU 17
897 #define CP0C3_ISA_ON_EXC 16
898 #define CP0C3_ISA 14 /* 15..14 */
899 #define CP0C3_ULRI 13
900 #define CP0C3_RXI 12
901 #define CP0C3_DSP2P 11
902 #define CP0C3_DSPP 10
903 #define CP0C3_CTXTC 9
904 #define CP0C3_ITL 8
905 #define CP0C3_LPA 7
906 #define CP0C3_VEIC 6
907 #define CP0C3_VInt 5
908 #define CP0C3_SP 4
909 #define CP0C3_CDMM 3
910 #define CP0C3_MT 2
911 #define CP0C3_SM 1
912 #define CP0C3_TL 0
913 int32_t CP0_Config4;
914 int32_t CP0_Config4_rw_bitmask;
915 #define CP0C4_M 31
916 #define CP0C4_IE 29 /* 30..29 */
917 #define CP0C4_AE 28
918 #define CP0C4_VTLBSizeExt 24 /* 27..24 */
919 #define CP0C4_KScrExist 16
920 #define CP0C4_MMUExtDef 14
921 #define CP0C4_FTLBPageSize 8 /* 12..8 */
922 /* bit layout if MMUExtDef=1 */
923 #define CP0C4_MMUSizeExt 0 /* 7..0 */
924 /* bit layout if MMUExtDef=2 */
925 #define CP0C4_FTLBWays 4 /* 7..4 */
926 #define CP0C4_FTLBSets 0 /* 3..0 */
927 int32_t CP0_Config5;
928 int32_t CP0_Config5_rw_bitmask;
929 #define CP0C5_M 31
930 #define CP0C5_K 30
931 #define CP0C5_CV 29
932 #define CP0C5_EVA 28
933 #define CP0C5_MSAEn 27
934 #define CP0C5_PMJ 23 /* 25..23 */
935 #define CP0C5_WR2 22
936 #define CP0C5_NMS 21
937 #define CP0C5_ULS 20
938 #define CP0C5_XPA 19
939 #define CP0C5_CRCP 18
940 #define CP0C5_MI 17
941 #define CP0C5_GI 15 /* 16..15 */
942 #define CP0C5_CA2 14
943 #define CP0C5_XNP 13
944 #define CP0C5_DEC 11
945 #define CP0C5_L2C 10
946 #define CP0C5_UFE 9
947 #define CP0C5_FRE 8
948 #define CP0C5_VP 7
949 #define CP0C5_SBRI 6
950 #define CP0C5_MVH 5
951 #define CP0C5_LLB 4
952 #define CP0C5_MRP 3
953 #define CP0C5_UFR 2
954 #define CP0C5_NFExists 0
955 int32_t CP0_Config6;
956 int32_t CP0_Config6_rw_bitmask;
957 #define CP0C6_BPPASS 31
958 #define CP0C6_KPOS 24
959 #define CP0C6_KE 23
960 #define CP0C6_VTLBONLY 22
961 #define CP0C6_LASX 21
962 #define CP0C6_SSEN 20
963 #define CP0C6_DISDRTIME 19
964 #define CP0C6_PIXNUEN 18
965 #define CP0C6_SCRAND 17
966 #define CP0C6_LLEXCEN 16
967 #define CP0C6_DISVC 15
968 #define CP0C6_VCLRU 14
969 #define CP0C6_DCLRU 13
970 #define CP0C6_PIXUEN 12
971 #define CP0C6_DISBLKLYEN 11
972 #define CP0C6_UMEMUALEN 10
973 #define CP0C6_SFBEN 8
974 #define CP0C6_FLTINT 7
975 #define CP0C6_VLTINT 6
976 #define CP0C6_DISBTB 5
977 #define CP0C6_STPREFCTL 2
978 #define CP0C6_INSTPREF 1
979 #define CP0C6_DATAPREF 0
980 int32_t CP0_Config7;
981 int64_t CP0_Config7_rw_bitmask;
982 #define CP0C7_WII 31
983 #define CP0C7_NAPCGEN 2
984 #define CP0C7_UNIMUEN 1
985 #define CP0C7_VFPUCGEN 0
986 uint64_t CP0_LLAddr;
987 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
988 int32_t CP0_MAARI;
989 /* XXX: Maybe make LLAddr per-TC? */
990 /*
991 * CP0 Register 17
992 */
993 target_ulong lladdr; /* LL virtual address compared against SC */
994 target_ulong llval;
995 uint64_t llval_wp;
996 uint32_t llnewval_wp;
997 uint64_t CP0_LLAddr_rw_bitmask;
998 int CP0_LLAddr_shift;
999 /*
1000 * CP0 Register 18
1001 */
1002 target_ulong CP0_WatchLo[8];
1003 /*
1004 * CP0 Register 19
1005 */
1006 uint64_t CP0_WatchHi[8];
1007 #define CP0WH_ASID 16
1008 #define CP0WH_M 31
1009 /*
1010 * CP0 Register 20
1011 */
1012 target_ulong CP0_XContext;
1013 int32_t CP0_Framemask;
1014 /*
1015 * CP0 Register 23
1016 */
1017 int32_t CP0_Debug;
1018 #define CP0DB_DBD 31
1019 #define CP0DB_DM 30
1020 #define CP0DB_LSNM 28
1021 #define CP0DB_Doze 27
1022 #define CP0DB_Halt 26
1023 #define CP0DB_CNT 25
1024 #define CP0DB_IBEP 24
1025 #define CP0DB_DBEP 21
1026 #define CP0DB_IEXI 20
1027 #define CP0DB_VER 15
1028 #define CP0DB_DEC 10
1029 #define CP0DB_SSt 8
1030 #define CP0DB_DINT 5
1031 #define CP0DB_DIB 4
1032 #define CP0DB_DDBS 3
1033 #define CP0DB_DDBL 2
1034 #define CP0DB_DBp 1
1035 #define CP0DB_DSS 0
1036 /*
1037 * CP0 Register 24
1038 */
1039 target_ulong CP0_DEPC;
1040 /*
1041 * CP0 Register 25
1042 */
1043 int32_t CP0_Performance0;
1044 /*
1045 * CP0 Register 26
1046 */
1047 int32_t CP0_ErrCtl;
1048 #define CP0EC_WST 29
1049 #define CP0EC_SPR 28
1050 #define CP0EC_ITC 26
1051 /*
1052 * CP0 Register 28
1053 */
1054 uint64_t CP0_TagLo;
1055 int32_t CP0_DataLo;
1056 /*
1057 * CP0 Register 29
1058 */
1059 int32_t CP0_TagHi;
1060 int32_t CP0_DataHi;
1061 /*
1062 * CP0 Register 30
1063 */
1064 target_ulong CP0_ErrorEPC;
1065 /*
1066 * CP0 Register 31
1067 */
1068 int32_t CP0_DESAVE;
1069 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
1070 /*
1071 * Loongson CSR CPUCFG registers
1072 */
1073 uint32_t lcsr_cpucfg1;
1074 #define CPUCFG1_FP 0
1075 #define CPUCFG1_FPREV 1
1076 #define CPUCFG1_MMI 4
1077 #define CPUCFG1_MSA1 5
1078 #define CPUCFG1_MSA2 6
1079 #define CPUCFG1_LSLDR0 16
1080 #define CPUCFG1_LSPERF 17
1081 #define CPUCFG1_LSPERFX 18
1082 #define CPUCFG1_LSSYNCI 19
1083 #define CPUCFG1_LLEXC 20
1084 #define CPUCFG1_SCRAND 21
1085 #define CPUCFG1_MUALP 25
1086 #define CPUCFG1_KMUALEN 26
1087 #define CPUCFG1_ITLBT 27
1088 #define CPUCFG1_SFBP 29
1089 #define CPUCFG1_CDMAP 30
1090 uint32_t lcsr_cpucfg2;
1091 #define CPUCFG2_LEXT1 0
1092 #define CPUCFG2_LEXT2 1
1093 #define CPUCFG2_LEXT3 2
1094 #define CPUCFG2_LSPW 3
1095 #define CPUCFG2_LCSRP 27
1096 #define CPUCFG2_LDISBLIKELY 28
1097
1098 /* We waste some space so we can handle shadow registers like TCs. */
1099 TCState tcs[MIPS_SHADOW_SET_MAX];
1100 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
1101 /* QEMU */
1102 int error_code;
1103 #define EXCP_TLB_NOMATCH 0x1
1104 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1105 uint32_t hflags; /* CPU State */
1106 /* TMASK defines different execution modes */
1107 #define MIPS_HFLAG_TMASK 0x3F5807FF
1108 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
1109 /*
1110 * The KSU flags must be the lowest bits in hflags. The flag order
1111 * must be the same as defined for CP0 Status. This allows to use
1112 * the bits as the value of mmu_idx.
1113 */
1114 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
1115 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
1116 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
1117 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
1118 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
1119 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
1120 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
1121 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
1122 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
1123 /*
1124 * True if the MIPS IV COP1X instructions can be used. This also
1125 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1126 * and RSQRT.D.
1127 */
1128 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
1129 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
1130 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
1131 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
1132 #define MIPS_HFLAG_M16_SHIFT 10
1133 /*
1134 * If translation is interrupted between the branch instruction and
1135 * the delay slot, record what type of branch it is so that we can
1136 * resume translation properly. It might be possible to reduce
1137 * this from three bits to two.
1138 */
1139 #define MIPS_HFLAG_BMASK_BASE 0x803800
1140 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
1141 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
1142 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
1143 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
1144 /* Extra flags about the current pending branch. */
1145 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1146 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
1147 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
1148 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
1149 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
1150 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
1151 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1152 /* MIPS DSP resources access. */
1153 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
1154 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
1155 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1156 /* Extra flag about HWREna register. */
1157 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1158 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1159 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
1160 #define MIPS_HFLAG_MSA 0x1000000
1161 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
1162 #define MIPS_HFLAG_ELPA 0x4000000
1163 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
1164 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
1165 target_ulong btarget; /* Jump / branch target */
1166 target_ulong bcond; /* Branch condition (if needed) */
1167
1168 int SYNCI_Step; /* Address step size for SYNCI */
1169 int CCRes; /* Cycle count resolution/divisor */
1170 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1171 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1172 uint64_t insn_flags; /* Supported instruction set */
1173
1174 /* Fields up to this point are cleared by a CPU reset */
1175 struct {} end_reset_fields;
1176
1177 /* Fields from here on are preserved across CPU reset. */
1178 CPUMIPSMVPContext *mvp;
1179 #if !defined(CONFIG_USER_ONLY)
1180 CPUMIPSTLBContext *tlb;
1181 qemu_irq irq[8];
1182 MemoryRegion *itc_tag; /* ITC Configuration Tags */
1183
1184 /* Loongson IOCSR memory */
1185 struct {
1186 AddressSpace as;
1187 MemoryRegion mr;
1188 } iocsr;
1189 #endif
1190
1191 const mips_def_t *cpu_model;
1192 QEMUTimer *timer; /* Internal timer */
1193 Clock *count_clock; /* CP0_Count clock */
1194 target_ulong exception_base; /* ExceptionBase input to the core */
1195 } CPUMIPSState;
1196
1197 /**
1198 * MIPSCPU:
1199 * @env: #CPUMIPSState
1200 * @clock: this CPU input clock (may be connected
1201 * to an output clock from another device).
1202 *
1203 * A MIPS CPU.
1204 */
1205 struct ArchCPU {
1206 CPUState parent_obj;
1207
1208 CPUMIPSState env;
1209
1210 Clock *clock;
1211 Clock *count_div; /* Divider for CP0_Count clock */
1212 };
1213
1214 /**
1215 * MIPSCPUClass:
1216 * @parent_realize: The parent class' realize handler.
1217 * @parent_phases: The parent class' reset phase handlers.
1218 *
1219 * A MIPS CPU model.
1220 */
1221 struct MIPSCPUClass {
1222 CPUClass parent_class;
1223
1224 DeviceRealize parent_realize;
1225 ResettablePhases parent_phases;
1226 const struct mips_def_t *cpu_def;
1227
1228 /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
1229 bool no_data_aborts;
1230 };
1231
1232 void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1233 uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1234
1235 /*
1236 * MMU modes definitions. We carefully match the indices with our
1237 * hflags layout.
1238 */
1239 #define MMU_KERNEL_IDX 0
1240 #define MMU_USER_IDX 2
1241 #define MMU_ERL_IDX 3
1242
hflags_mmu_index(uint32_t hflags)1243 static inline int hflags_mmu_index(uint32_t hflags)
1244 {
1245 if (hflags & MIPS_HFLAG_ERL) {
1246 return MMU_ERL_IDX;
1247 } else {
1248 return hflags & MIPS_HFLAG_KSU;
1249 }
1250 }
1251
mips_env_mmu_index(CPUMIPSState * env)1252 static inline int mips_env_mmu_index(CPUMIPSState *env)
1253 {
1254 return hflags_mmu_index(env->hflags);
1255 }
1256
1257 #include "exec/cpu-all.h"
1258
1259 /* Exceptions */
1260 enum {
1261 EXCP_NONE = -1,
1262 EXCP_RESET = 0,
1263 EXCP_SRESET,
1264 EXCP_DSS,
1265 EXCP_DINT,
1266 EXCP_DDBL,
1267 EXCP_DDBS,
1268 EXCP_NMI,
1269 EXCP_MCHECK,
1270 EXCP_EXT_INTERRUPT, /* 8 */
1271 EXCP_DFWATCH,
1272 EXCP_DIB,
1273 EXCP_IWATCH,
1274 EXCP_AdEL,
1275 EXCP_AdES,
1276 EXCP_TLBF,
1277 EXCP_IBE,
1278 EXCP_DBp, /* 16 */
1279 EXCP_SYSCALL,
1280 EXCP_BREAK,
1281 EXCP_CpU,
1282 EXCP_RI,
1283 EXCP_OVERFLOW,
1284 EXCP_TRAP,
1285 EXCP_FPE,
1286 EXCP_DWATCH, /* 24 */
1287 EXCP_LTLBL,
1288 EXCP_TLBL,
1289 EXCP_TLBS,
1290 EXCP_DBE,
1291 EXCP_THREAD,
1292 EXCP_MDMX,
1293 EXCP_C2E,
1294 EXCP_CACHE, /* 32 */
1295 EXCP_DSPDIS,
1296 EXCP_MSADIS,
1297 EXCP_MSAFPE,
1298 EXCP_TLBXI,
1299 EXCP_TLBRI,
1300 EXCP_SEMIHOST,
1301
1302 EXCP_LAST = EXCP_SEMIHOST,
1303 };
1304
1305 /*
1306 * This is an internally generated WAKE request line.
1307 * It is driven by the CPU itself. Raised when the MT
1308 * block wants to wake a VPE from an inactive state and
1309 * cleared when VPE goes from active to inactive.
1310 */
1311 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1312
1313 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1314
1315 bool cpu_type_supports_cps_smp(const char *cpu_type);
1316 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
1317 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
1318
1319 /* Check presence of MSA implementation */
ase_msa_available(CPUMIPSState * env)1320 static inline bool ase_msa_available(CPUMIPSState *env)
1321 {
1322 return env->CP0_Config3 & (1 << CP0C3_MSAP);
1323 }
1324
1325 /* Check presence of Loongson CSR instructions */
ase_lcsr_available(CPUMIPSState * env)1326 static inline bool ase_lcsr_available(CPUMIPSState *env)
1327 {
1328 return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
1329 }
1330
1331 /* Check presence of multi-threading ASE implementation */
ase_mt_available(CPUMIPSState * env)1332 static inline bool ase_mt_available(CPUMIPSState *env)
1333 {
1334 return env->CP0_Config3 & (1 << CP0C3_MT);
1335 }
1336
cpu_type_is_64bit(const char * cpu_type)1337 static inline bool cpu_type_is_64bit(const char *cpu_type)
1338 {
1339 return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
1340 }
1341
1342 void cpu_set_exception_base(int vp_index, target_ulong address);
1343
1344 /* addr.c */
1345 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
1346 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
1347
1348 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
1349 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
1350
1351 #if !defined(CONFIG_USER_ONLY)
1352
1353 /* HW declaration specific to the MIPS target */
1354 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1355 void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
1356 void cpu_mips_clock_init(MIPSCPU *cpu);
1357
1358 #endif /* !CONFIG_USER_ONLY */
1359
1360 /* helper.c */
1361 target_ulong exception_resume_pc(CPUMIPSState *env);
1362
cpu_get_tb_cpu_state(CPUMIPSState * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)1363 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
1364 uint64_t *cs_base, uint32_t *flags)
1365 {
1366 *pc = env->active_tc.PC;
1367 *cs_base = 0;
1368 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1369 MIPS_HFLAG_HWRENA_ULR);
1370 }
1371
1372 /**
1373 * mips_cpu_create_with_clock:
1374 * @typename: a MIPS CPU type.
1375 * @cpu_refclk: this cpu input clock (an output clock of another device)
1376 *
1377 * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
1378 * then realizes the CPU.
1379 *
1380 * Returns: A #CPUState or %NULL if an error occurred.
1381 */
1382 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
1383
1384 #endif /* MIPS_CPU_H */
1385