1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
36 #include "sysemu/kvm_int.h"
37 #include "sysemu/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "xen-emu.h"
42 #include "hyperv.h"
43 #include "hyperv-proto.h"
44
45 #include "gdbstub/enums.h"
46 #include "qemu/host-utils.h"
47 #include "qemu/main-loop.h"
48 #include "qemu/ratelimit.h"
49 #include "qemu/config-file.h"
50 #include "qemu/error-report.h"
51 #include "qemu/memalign.h"
52 #include "hw/i386/x86.h"
53 #include "hw/i386/kvm/xen_evtchn.h"
54 #include "hw/i386/pc.h"
55 #include "hw/i386/apic.h"
56 #include "hw/i386/apic_internal.h"
57 #include "hw/i386/apic-msidef.h"
58 #include "hw/i386/intel_iommu.h"
59 #include "hw/i386/topology.h"
60 #include "hw/i386/x86-iommu.h"
61 #include "hw/i386/e820_memory_layout.h"
62
63 #include "hw/xen/xen.h"
64
65 #include "hw/pci/pci.h"
66 #include "hw/pci/msi.h"
67 #include "hw/pci/msix.h"
68 #include "migration/blocker.h"
69 #include "exec/memattrs.h"
70 #include "trace.h"
71
72 #include CONFIG_DEVICES
73
74 //#define DEBUG_KVM
75
76 #ifdef DEBUG_KVM
77 #define DPRINTF(fmt, ...) \
78 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define DPRINTF(fmt, ...) \
81 do { } while (0)
82 #endif
83
84 /*
85 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
86 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
87 * Since these must be part of guest physical memory, we need to allocate
88 * them, both by setting their start addresses in the kernel and by
89 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
90 * so this value allows up to 16M BIOSes.
91 */
92 #define KVM_IDENTITY_BASE 0xfeffc000
93
94 /* From arch/x86/kvm/lapic.h */
95 #define KVM_APIC_BUS_CYCLE_NS 1
96 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
97
98 #define MSR_KVM_WALL_CLOCK 0x11
99 #define MSR_KVM_SYSTEM_TIME 0x12
100
101 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
102 * 255 kvm_msr_entry structs */
103 #define MSR_BUF_SIZE 4096
104
105 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
106 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
107 typedef struct {
108 uint32_t msr;
109 QEMURDMSRHandler *rdmsr;
110 QEMUWRMSRHandler *wrmsr;
111 } KVMMSRHandlers;
112
113 static void kvm_init_msrs(X86CPU *cpu);
114 static bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
115 QEMUWRMSRHandler *wrmsr);
116
117 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
118 KVM_CAP_INFO(SET_TSS_ADDR),
119 KVM_CAP_INFO(EXT_CPUID),
120 KVM_CAP_INFO(MP_STATE),
121 KVM_CAP_INFO(SIGNAL_MSI),
122 KVM_CAP_INFO(IRQ_ROUTING),
123 KVM_CAP_INFO(DEBUGREGS),
124 KVM_CAP_INFO(XSAVE),
125 KVM_CAP_INFO(VCPU_EVENTS),
126 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
127 KVM_CAP_INFO(MCE),
128 KVM_CAP_INFO(ADJUST_CLOCK),
129 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
130 KVM_CAP_LAST_INFO
131 };
132
133 static bool has_msr_star;
134 static bool has_msr_hsave_pa;
135 static bool has_msr_tsc_aux;
136 static bool has_msr_tsc_adjust;
137 static bool has_msr_tsc_deadline;
138 static bool has_msr_feature_control;
139 static bool has_msr_misc_enable;
140 static bool has_msr_smbase;
141 static bool has_msr_bndcfgs;
142 static int lm_capable_kernel;
143 static bool has_msr_hv_hypercall;
144 static bool has_msr_hv_crash;
145 static bool has_msr_hv_reset;
146 static bool has_msr_hv_vpindex;
147 static bool hv_vpindex_settable;
148 static bool has_msr_hv_runtime;
149 static bool has_msr_hv_synic;
150 static bool has_msr_hv_stimer;
151 static bool has_msr_hv_frequencies;
152 static bool has_msr_hv_reenlightenment;
153 static bool has_msr_hv_syndbg_options;
154 static bool has_msr_xss;
155 static bool has_msr_umwait;
156 static bool has_msr_spec_ctrl;
157 static bool has_tsc_scale_msr;
158 static bool has_msr_tsx_ctrl;
159 static bool has_msr_virt_ssbd;
160 static bool has_msr_smi_count;
161 static bool has_msr_arch_capabs;
162 static bool has_msr_core_capabs;
163 static bool has_msr_vmx_vmfunc;
164 static bool has_msr_ucode_rev;
165 static bool has_msr_vmx_procbased_ctls2;
166 static bool has_msr_perf_capabs;
167 static bool has_msr_pkrs;
168 static bool has_msr_hwcr;
169
170 static uint32_t has_architectural_pmu_version;
171 static uint32_t num_architectural_pmu_gp_counters;
172 static uint32_t num_architectural_pmu_fixed_counters;
173
174 static int has_xsave2;
175 static int has_xcrs;
176 static int has_sregs2;
177 static int has_exception_payload;
178 static int has_triple_fault_event;
179
180 static bool has_msr_mcg_ext_ctl;
181
182 static struct kvm_cpuid2 *cpuid_cache;
183 static struct kvm_cpuid2 *hv_cpuid_cache;
184 static struct kvm_msr_list *kvm_feature_msrs;
185
186 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
187
188 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
189 static RateLimit bus_lock_ratelimit_ctrl;
190 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
191
192 static const char *vm_type_name[] = {
193 [KVM_X86_DEFAULT_VM] = "default",
194 [KVM_X86_SEV_VM] = "SEV",
195 [KVM_X86_SEV_ES_VM] = "SEV-ES",
196 [KVM_X86_SNP_VM] = "SEV-SNP",
197 };
198
kvm_is_vm_type_supported(int type)199 bool kvm_is_vm_type_supported(int type)
200 {
201 uint32_t machine_types;
202
203 /*
204 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
205 * is always supported
206 */
207 if (type == KVM_X86_DEFAULT_VM) {
208 return true;
209 }
210
211 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
212 KVM_CAP_VM_TYPES);
213 return !!(machine_types & BIT(type));
214 }
215
kvm_get_vm_type(MachineState * ms)216 int kvm_get_vm_type(MachineState *ms)
217 {
218 int kvm_type = KVM_X86_DEFAULT_VM;
219
220 if (ms->cgs) {
221 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
222 error_report("configuration type %s not supported for x86 guests",
223 object_get_typename(OBJECT(ms->cgs)));
224 exit(1);
225 }
226 kvm_type = x86_confidential_guest_kvm_type(
227 X86_CONFIDENTIAL_GUEST(ms->cgs));
228 }
229
230 if (!kvm_is_vm_type_supported(kvm_type)) {
231 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
232 exit(1);
233 }
234
235 return kvm_type;
236 }
237
kvm_enable_hypercall(uint64_t enable_mask)238 bool kvm_enable_hypercall(uint64_t enable_mask)
239 {
240 KVMState *s = KVM_STATE(current_accel());
241
242 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
243 }
244
kvm_has_smm(void)245 bool kvm_has_smm(void)
246 {
247 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
248 }
249
kvm_has_adjust_clock_stable(void)250 bool kvm_has_adjust_clock_stable(void)
251 {
252 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
253
254 return (ret & KVM_CLOCK_TSC_STABLE);
255 }
256
kvm_has_exception_payload(void)257 bool kvm_has_exception_payload(void)
258 {
259 return has_exception_payload;
260 }
261
kvm_x2apic_api_set_flags(uint64_t flags)262 static bool kvm_x2apic_api_set_flags(uint64_t flags)
263 {
264 KVMState *s = KVM_STATE(current_accel());
265
266 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
267 }
268
269 #define MEMORIZE(fn, _result) \
270 ({ \
271 static bool _memorized; \
272 \
273 if (_memorized) { \
274 return _result; \
275 } \
276 _memorized = true; \
277 _result = fn; \
278 })
279
280 static bool has_x2apic_api;
281
kvm_has_x2apic_api(void)282 bool kvm_has_x2apic_api(void)
283 {
284 return has_x2apic_api;
285 }
286
kvm_enable_x2apic(void)287 bool kvm_enable_x2apic(void)
288 {
289 return MEMORIZE(
290 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
291 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
292 has_x2apic_api);
293 }
294
kvm_hv_vpindex_settable(void)295 bool kvm_hv_vpindex_settable(void)
296 {
297 return hv_vpindex_settable;
298 }
299
kvm_get_tsc(CPUState * cs)300 static int kvm_get_tsc(CPUState *cs)
301 {
302 X86CPU *cpu = X86_CPU(cs);
303 CPUX86State *env = &cpu->env;
304 uint64_t value;
305 int ret;
306
307 if (env->tsc_valid) {
308 return 0;
309 }
310
311 env->tsc_valid = !runstate_is_running();
312
313 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
314 if (ret < 0) {
315 return ret;
316 }
317
318 env->tsc = value;
319 return 0;
320 }
321
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)322 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
323 {
324 kvm_get_tsc(cpu);
325 }
326
kvm_synchronize_all_tsc(void)327 void kvm_synchronize_all_tsc(void)
328 {
329 CPUState *cpu;
330
331 if (kvm_enabled()) {
332 CPU_FOREACH(cpu) {
333 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
334 }
335 }
336 }
337
try_get_cpuid(KVMState * s,int max)338 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
339 {
340 struct kvm_cpuid2 *cpuid;
341 int r, size;
342
343 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
344 cpuid = g_malloc0(size);
345 cpuid->nent = max;
346 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
347 if (r == 0 && cpuid->nent >= max) {
348 r = -E2BIG;
349 }
350 if (r < 0) {
351 if (r == -E2BIG) {
352 g_free(cpuid);
353 return NULL;
354 } else {
355 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
356 strerror(-r));
357 exit(1);
358 }
359 }
360 return cpuid;
361 }
362
363 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
364 * for all entries.
365 */
get_supported_cpuid(KVMState * s)366 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
367 {
368 struct kvm_cpuid2 *cpuid;
369 int max = 1;
370
371 if (cpuid_cache != NULL) {
372 return cpuid_cache;
373 }
374 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
375 max *= 2;
376 }
377 cpuid_cache = cpuid;
378 return cpuid;
379 }
380
host_tsx_broken(void)381 static bool host_tsx_broken(void)
382 {
383 int family, model, stepping;\
384 char vendor[CPUID_VENDOR_SZ + 1];
385
386 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
387
388 /* Check if we are running on a Haswell host known to have broken TSX */
389 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
390 (family == 6) &&
391 ((model == 63 && stepping < 4) ||
392 model == 60 || model == 69 || model == 70);
393 }
394
395 /* Returns the value for a specific register on the cpuid entry
396 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)397 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
398 {
399 uint32_t ret = 0;
400 switch (reg) {
401 case R_EAX:
402 ret = entry->eax;
403 break;
404 case R_EBX:
405 ret = entry->ebx;
406 break;
407 case R_ECX:
408 ret = entry->ecx;
409 break;
410 case R_EDX:
411 ret = entry->edx;
412 break;
413 }
414 return ret;
415 }
416
417 /* Find matching entry for function/index on kvm_cpuid2 struct
418 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)419 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
420 uint32_t function,
421 uint32_t index)
422 {
423 int i;
424 for (i = 0; i < cpuid->nent; ++i) {
425 if (cpuid->entries[i].function == function &&
426 cpuid->entries[i].index == index) {
427 return &cpuid->entries[i];
428 }
429 }
430 /* not found: */
431 return NULL;
432 }
433
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)434 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
435 uint32_t index, int reg)
436 {
437 struct kvm_cpuid2 *cpuid;
438 uint32_t ret = 0;
439 uint32_t cpuid_1_edx, unused;
440 uint64_t bitmask;
441
442 cpuid = get_supported_cpuid(s);
443
444 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
445 if (entry) {
446 ret = cpuid_entry_get_reg(entry, reg);
447 }
448
449 /* Fixups for the data returned by KVM, below */
450
451 if (function == 1 && reg == R_EDX) {
452 /* KVM before 2.6.30 misreports the following features */
453 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
454 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
455 ret |= CPUID_HT;
456 } else if (function == 1 && reg == R_ECX) {
457 /* We can set the hypervisor flag, even if KVM does not return it on
458 * GET_SUPPORTED_CPUID
459 */
460 ret |= CPUID_EXT_HYPERVISOR;
461 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
462 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
463 * and the irqchip is in the kernel.
464 */
465 if (kvm_irqchip_in_kernel() &&
466 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
467 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
468 }
469
470 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
471 * without the in-kernel irqchip
472 */
473 if (!kvm_irqchip_in_kernel()) {
474 ret &= ~CPUID_EXT_X2APIC;
475 }
476
477 if (enable_cpu_pm) {
478 int disable_exits = kvm_check_extension(s,
479 KVM_CAP_X86_DISABLE_EXITS);
480
481 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
482 ret |= CPUID_EXT_MONITOR;
483 }
484 }
485 } else if (function == 6 && reg == R_EAX) {
486 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
487 } else if (function == 7 && index == 0 && reg == R_EBX) {
488 /* Not new instructions, just an optimization. */
489 uint32_t ebx;
490 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
491 ret |= ebx & CPUID_7_0_EBX_ERMS;
492
493 if (host_tsx_broken()) {
494 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
495 }
496 } else if (function == 7 && index == 0 && reg == R_EDX) {
497 /* Not new instructions, just an optimization. */
498 uint32_t edx;
499 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
500 ret |= edx & CPUID_7_0_EDX_FSRM;
501
502 /*
503 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
504 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
505 * returned by KVM_GET_MSR_INDEX_LIST.
506 */
507 if (!has_msr_arch_capabs) {
508 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
509 }
510 } else if (function == 7 && index == 1 && reg == R_EAX) {
511 /* Not new instructions, just an optimization. */
512 uint32_t eax;
513 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
514 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
515 } else if (function == 7 && index == 2 && reg == R_EDX) {
516 uint32_t edx;
517 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
518 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
519 } else if (function == 0xd && index == 0 &&
520 (reg == R_EAX || reg == R_EDX)) {
521 /*
522 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
523 * features that still have to be enabled with the arch_prctl
524 * system call. QEMU needs the full value, which is retrieved
525 * with KVM_GET_DEVICE_ATTR.
526 */
527 struct kvm_device_attr attr = {
528 .group = 0,
529 .attr = KVM_X86_XCOMP_GUEST_SUPP,
530 .addr = (unsigned long) &bitmask
531 };
532
533 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
534 if (!sys_attr) {
535 return ret;
536 }
537
538 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
539 if (rc < 0) {
540 if (rc != -ENXIO) {
541 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
542 "error: %d", rc);
543 }
544 return ret;
545 }
546 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
547 } else if (function == 0x80000001 && reg == R_ECX) {
548 /*
549 * It's safe to enable TOPOEXT even if it's not returned by
550 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
551 * us to keep CPU models including TOPOEXT runnable on older kernels.
552 */
553 ret |= CPUID_EXT3_TOPOEXT;
554 } else if (function == 0x80000001 && reg == R_EDX) {
555 /* On Intel, kvm returns cpuid according to the Intel spec,
556 * so add missing bits according to the AMD spec:
557 */
558 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
559 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
560 } else if (function == 0x80000007 && reg == R_EBX) {
561 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
562 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
563 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
564 * be enabled without the in-kernel irqchip
565 */
566 if (!kvm_irqchip_in_kernel()) {
567 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
568 }
569 if (kvm_irqchip_is_split()) {
570 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
571 }
572 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
573 ret |= 1U << KVM_HINTS_REALTIME;
574 }
575
576 if (current_machine->cgs) {
577 ret = x86_confidential_guest_mask_cpuid_features(
578 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
579 function, index, reg, ret);
580 }
581 return ret;
582 }
583
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)584 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
585 {
586 struct {
587 struct kvm_msrs info;
588 struct kvm_msr_entry entries[1];
589 } msr_data = {};
590 uint64_t value;
591 uint32_t ret, can_be_one, must_be_one;
592
593 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
594 return 0;
595 }
596
597 /* Check if requested MSR is supported feature MSR */
598 int i;
599 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
600 if (kvm_feature_msrs->indices[i] == index) {
601 break;
602 }
603 if (i == kvm_feature_msrs->nmsrs) {
604 return 0; /* if the feature MSR is not supported, simply return 0 */
605 }
606
607 msr_data.info.nmsrs = 1;
608 msr_data.entries[0].index = index;
609
610 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
611 if (ret != 1) {
612 error_report("KVM get MSR (index=0x%x) feature failed, %s",
613 index, strerror(-ret));
614 exit(1);
615 }
616
617 value = msr_data.entries[0].data;
618 switch (index) {
619 case MSR_IA32_VMX_PROCBASED_CTLS2:
620 if (!has_msr_vmx_procbased_ctls2) {
621 /* KVM forgot to add these bits for some time, do this ourselves. */
622 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
623 CPUID_XSAVE_XSAVES) {
624 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
625 }
626 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
627 CPUID_EXT_RDRAND) {
628 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
629 }
630 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
631 CPUID_7_0_EBX_INVPCID) {
632 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
633 }
634 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
635 CPUID_7_0_EBX_RDSEED) {
636 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
637 }
638 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
639 CPUID_EXT2_RDTSCP) {
640 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
641 }
642 }
643 /* fall through */
644 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
645 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
646 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
647 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
648 /*
649 * Return true for bits that can be one, but do not have to be one.
650 * The SDM tells us which bits could have a "must be one" setting,
651 * so we can do the opposite transformation in make_vmx_msr_value.
652 */
653 must_be_one = (uint32_t)value;
654 can_be_one = (uint32_t)(value >> 32);
655 return can_be_one & ~must_be_one;
656
657 default:
658 return value;
659 }
660 }
661
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)662 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
663 int *max_banks)
664 {
665 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
666 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
667 }
668
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)669 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
670 {
671 CPUState *cs = CPU(cpu);
672 CPUX86State *env = &cpu->env;
673 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
674 MCI_STATUS_ADDRV;
675 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
676 int flags = 0;
677
678 if (!IS_AMD_CPU(env)) {
679 status |= MCI_STATUS_S | MCI_STATUS_UC;
680 if (code == BUS_MCEERR_AR) {
681 status |= MCI_STATUS_AR | 0x134;
682 mcg_status |= MCG_STATUS_EIPV;
683 } else {
684 status |= 0xc0;
685 }
686 } else {
687 if (code == BUS_MCEERR_AR) {
688 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
689 mcg_status |= MCG_STATUS_EIPV;
690 } else {
691 /* Setting the POISON bit for deferred errors indicates to the
692 * guest kernel that the address provided by the MCE is valid
693 * and usable which will ensure that the guest kernel will send
694 * a SIGBUS_AO signal to the guest process. This allows for
695 * more desirable behavior in the case that the guest process
696 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
697 * which indicates that the process would prefer to handle or
698 * shutdown due to the poisoned memory condition before the
699 * memory has been accessed.
700 *
701 * While the POISON bit would not be set in a deferred error
702 * sent from hardware, the bit is not meaningful for deferred
703 * errors and can be reused in this scenario.
704 */
705 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
706 }
707 }
708
709 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
710 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
711 * guest kernel back into env->mcg_ext_ctl.
712 */
713 cpu_synchronize_state(cs);
714 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
715 mcg_status |= MCG_STATUS_LMCE;
716 flags = 0;
717 }
718
719 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
720 (MCM_ADDR_PHYS << 6) | 0xc, flags);
721 }
722
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)723 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
724 {
725 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
726
727 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
728 &mff);
729 }
730
hardware_memory_error(void * host_addr)731 static void hardware_memory_error(void *host_addr)
732 {
733 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
734 error_report("QEMU got Hardware memory error at addr %p", host_addr);
735 exit(1);
736 }
737
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)738 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
739 {
740 X86CPU *cpu = X86_CPU(c);
741 CPUX86State *env = &cpu->env;
742 ram_addr_t ram_addr;
743 hwaddr paddr;
744
745 /* If we get an action required MCE, it has been injected by KVM
746 * while the VM was running. An action optional MCE instead should
747 * be coming from the main thread, which qemu_init_sigbus identifies
748 * as the "early kill" thread.
749 */
750 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
751
752 if ((env->mcg_cap & MCG_SER_P) && addr) {
753 ram_addr = qemu_ram_addr_from_host(addr);
754 if (ram_addr != RAM_ADDR_INVALID &&
755 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
756 kvm_hwpoison_page_add(ram_addr);
757 kvm_mce_inject(cpu, paddr, code);
758
759 /*
760 * Use different logging severity based on error type.
761 * If there is additional MCE reporting on the hypervisor, QEMU VA
762 * could be another source to identify the PA and MCE details.
763 */
764 if (code == BUS_MCEERR_AR) {
765 error_report("Guest MCE Memory Error at QEMU addr %p and "
766 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
767 addr, paddr, "BUS_MCEERR_AR");
768 } else {
769 warn_report("Guest MCE Memory Error at QEMU addr %p and "
770 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
771 addr, paddr, "BUS_MCEERR_AO");
772 }
773
774 return;
775 }
776
777 if (code == BUS_MCEERR_AO) {
778 warn_report("Hardware memory error at addr %p of type %s "
779 "for memory used by QEMU itself instead of guest system!",
780 addr, "BUS_MCEERR_AO");
781 }
782 }
783
784 if (code == BUS_MCEERR_AR) {
785 hardware_memory_error(addr);
786 }
787
788 /* Hope we are lucky for AO MCE, just notify a event */
789 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
790 }
791
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)792 static void kvm_queue_exception(CPUX86State *env,
793 int32_t exception_nr,
794 uint8_t exception_has_payload,
795 uint64_t exception_payload)
796 {
797 assert(env->exception_nr == -1);
798 assert(!env->exception_pending);
799 assert(!env->exception_injected);
800 assert(!env->exception_has_payload);
801
802 env->exception_nr = exception_nr;
803
804 if (has_exception_payload) {
805 env->exception_pending = 1;
806
807 env->exception_has_payload = exception_has_payload;
808 env->exception_payload = exception_payload;
809 } else {
810 env->exception_injected = 1;
811
812 if (exception_nr == EXCP01_DB) {
813 assert(exception_has_payload);
814 env->dr[6] = exception_payload;
815 } else if (exception_nr == EXCP0E_PAGE) {
816 assert(exception_has_payload);
817 env->cr[2] = exception_payload;
818 } else {
819 assert(!exception_has_payload);
820 }
821 }
822 }
823
cpu_update_state(void * opaque,bool running,RunState state)824 static void cpu_update_state(void *opaque, bool running, RunState state)
825 {
826 CPUX86State *env = opaque;
827
828 if (running) {
829 env->tsc_valid = false;
830 }
831 }
832
kvm_arch_vcpu_id(CPUState * cs)833 unsigned long kvm_arch_vcpu_id(CPUState *cs)
834 {
835 X86CPU *cpu = X86_CPU(cs);
836 return cpu->apic_id;
837 }
838
839 #ifndef KVM_CPUID_SIGNATURE_NEXT
840 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
841 #endif
842
hyperv_enabled(X86CPU * cpu)843 static bool hyperv_enabled(X86CPU *cpu)
844 {
845 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
846 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
847 cpu->hyperv_features || cpu->hyperv_passthrough);
848 }
849
850 /*
851 * Check whether target_freq is within conservative
852 * ntp correctable bounds (250ppm) of freq
853 */
freq_within_bounds(int freq,int target_freq)854 static inline bool freq_within_bounds(int freq, int target_freq)
855 {
856 int max_freq = freq + (freq * 250 / 1000000);
857 int min_freq = freq - (freq * 250 / 1000000);
858
859 if (target_freq >= min_freq && target_freq <= max_freq) {
860 return true;
861 }
862
863 return false;
864 }
865
kvm_arch_set_tsc_khz(CPUState * cs)866 static int kvm_arch_set_tsc_khz(CPUState *cs)
867 {
868 X86CPU *cpu = X86_CPU(cs);
869 CPUX86State *env = &cpu->env;
870 int r, cur_freq;
871 bool set_ioctl = false;
872
873 if (!env->tsc_khz) {
874 return 0;
875 }
876
877 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
878 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
879
880 /*
881 * If TSC scaling is supported, attempt to set TSC frequency.
882 */
883 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
884 set_ioctl = true;
885 }
886
887 /*
888 * If desired TSC frequency is within bounds of NTP correction,
889 * attempt to set TSC frequency.
890 */
891 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
892 set_ioctl = true;
893 }
894
895 r = set_ioctl ?
896 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
897 -ENOTSUP;
898
899 if (r < 0) {
900 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
901 * TSC frequency doesn't match the one we want.
902 */
903 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
904 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
905 -ENOTSUP;
906 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
907 warn_report("TSC frequency mismatch between "
908 "VM (%" PRId64 " kHz) and host (%d kHz), "
909 "and TSC scaling unavailable",
910 env->tsc_khz, cur_freq);
911 return r;
912 }
913 }
914
915 return 0;
916 }
917
tsc_is_stable_and_known(CPUX86State * env)918 static bool tsc_is_stable_and_known(CPUX86State *env)
919 {
920 if (!env->tsc_khz) {
921 return false;
922 }
923 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
924 || env->user_tsc_khz;
925 }
926
927 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
928
929 static struct {
930 const char *desc;
931 struct {
932 uint32_t func;
933 int reg;
934 uint32_t bits;
935 } flags[2];
936 uint64_t dependencies;
937 bool skip_passthrough;
938 } kvm_hyperv_properties[] = {
939 [HYPERV_FEAT_RELAXED] = {
940 .desc = "relaxed timing (hv-relaxed)",
941 .flags = {
942 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
943 .bits = HV_RELAXED_TIMING_RECOMMENDED}
944 }
945 },
946 [HYPERV_FEAT_VAPIC] = {
947 .desc = "virtual APIC (hv-vapic)",
948 .flags = {
949 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
950 .bits = HV_APIC_ACCESS_AVAILABLE}
951 }
952 },
953 [HYPERV_FEAT_TIME] = {
954 .desc = "clocksources (hv-time)",
955 .flags = {
956 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
957 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
958 }
959 },
960 [HYPERV_FEAT_CRASH] = {
961 .desc = "crash MSRs (hv-crash)",
962 .flags = {
963 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
964 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
965 }
966 },
967 [HYPERV_FEAT_RESET] = {
968 .desc = "reset MSR (hv-reset)",
969 .flags = {
970 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
971 .bits = HV_RESET_AVAILABLE}
972 }
973 },
974 [HYPERV_FEAT_VPINDEX] = {
975 .desc = "VP_INDEX MSR (hv-vpindex)",
976 .flags = {
977 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
978 .bits = HV_VP_INDEX_AVAILABLE}
979 }
980 },
981 [HYPERV_FEAT_RUNTIME] = {
982 .desc = "VP_RUNTIME MSR (hv-runtime)",
983 .flags = {
984 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
985 .bits = HV_VP_RUNTIME_AVAILABLE}
986 }
987 },
988 [HYPERV_FEAT_SYNIC] = {
989 .desc = "synthetic interrupt controller (hv-synic)",
990 .flags = {
991 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
992 .bits = HV_SYNIC_AVAILABLE}
993 }
994 },
995 [HYPERV_FEAT_STIMER] = {
996 .desc = "synthetic timers (hv-stimer)",
997 .flags = {
998 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
999 .bits = HV_SYNTIMERS_AVAILABLE}
1000 },
1001 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1002 },
1003 [HYPERV_FEAT_FREQUENCIES] = {
1004 .desc = "frequency MSRs (hv-frequencies)",
1005 .flags = {
1006 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1007 .bits = HV_ACCESS_FREQUENCY_MSRS},
1008 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1009 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1010 }
1011 },
1012 [HYPERV_FEAT_REENLIGHTENMENT] = {
1013 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1014 .flags = {
1015 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1016 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1017 }
1018 },
1019 [HYPERV_FEAT_TLBFLUSH] = {
1020 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1021 .flags = {
1022 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1023 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1024 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1025 },
1026 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1027 },
1028 [HYPERV_FEAT_EVMCS] = {
1029 .desc = "enlightened VMCS (hv-evmcs)",
1030 .flags = {
1031 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1032 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1033 },
1034 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1035 },
1036 [HYPERV_FEAT_IPI] = {
1037 .desc = "paravirtualized IPI (hv-ipi)",
1038 .flags = {
1039 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1040 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1041 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1042 },
1043 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1044 },
1045 [HYPERV_FEAT_STIMER_DIRECT] = {
1046 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1047 .flags = {
1048 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1049 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1050 },
1051 .dependencies = BIT(HYPERV_FEAT_STIMER)
1052 },
1053 [HYPERV_FEAT_AVIC] = {
1054 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1055 .flags = {
1056 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1057 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1058 }
1059 },
1060 [HYPERV_FEAT_SYNDBG] = {
1061 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1062 .flags = {
1063 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1064 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1065 },
1066 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1067 .skip_passthrough = true,
1068 },
1069 [HYPERV_FEAT_MSR_BITMAP] = {
1070 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1071 .flags = {
1072 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1073 .bits = HV_NESTED_MSR_BITMAP}
1074 }
1075 },
1076 [HYPERV_FEAT_XMM_INPUT] = {
1077 .desc = "XMM fast hypercall input (hv-xmm-input)",
1078 .flags = {
1079 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1080 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1081 }
1082 },
1083 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1084 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1085 .flags = {
1086 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1087 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1088 },
1089 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1090 },
1091 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1092 .desc = "direct TLB flush (hv-tlbflush-direct)",
1093 .flags = {
1094 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1095 .bits = HV_NESTED_DIRECT_FLUSH}
1096 },
1097 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1098 },
1099 };
1100
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1101 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1102 bool do_sys_ioctl)
1103 {
1104 struct kvm_cpuid2 *cpuid;
1105 int r, size;
1106
1107 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1108 cpuid = g_malloc0(size);
1109 cpuid->nent = max;
1110
1111 if (do_sys_ioctl) {
1112 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1113 } else {
1114 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1115 }
1116 if (r == 0 && cpuid->nent >= max) {
1117 r = -E2BIG;
1118 }
1119 if (r < 0) {
1120 if (r == -E2BIG) {
1121 g_free(cpuid);
1122 return NULL;
1123 } else {
1124 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1125 strerror(-r));
1126 exit(1);
1127 }
1128 }
1129 return cpuid;
1130 }
1131
1132 /*
1133 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1134 * for all entries.
1135 */
get_supported_hv_cpuid(CPUState * cs)1136 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1137 {
1138 struct kvm_cpuid2 *cpuid;
1139 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1140 int max = 11;
1141 int i;
1142 bool do_sys_ioctl;
1143
1144 do_sys_ioctl =
1145 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1146
1147 /*
1148 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1149 * unsupported, kvm_hyperv_expand_features() checks for that.
1150 */
1151 assert(do_sys_ioctl || cs->kvm_state);
1152
1153 /*
1154 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1155 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1156 * it and re-trying until we succeed.
1157 */
1158 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1159 max++;
1160 }
1161
1162 /*
1163 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1164 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1165 * information early, just check for the capability and set the bit
1166 * manually.
1167 */
1168 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1169 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1170 for (i = 0; i < cpuid->nent; i++) {
1171 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1172 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1173 }
1174 }
1175 }
1176
1177 return cpuid;
1178 }
1179
1180 /*
1181 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1182 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1183 */
get_supported_hv_cpuid_legacy(CPUState * cs)1184 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1185 {
1186 X86CPU *cpu = X86_CPU(cs);
1187 struct kvm_cpuid2 *cpuid;
1188 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1189
1190 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1191 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1192 cpuid->nent = 2;
1193
1194 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1195 entry_feat = &cpuid->entries[0];
1196 entry_feat->function = HV_CPUID_FEATURES;
1197
1198 entry_recomm = &cpuid->entries[1];
1199 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1200 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1201
1202 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1203 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1204 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1205 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1206 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1207 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1208 }
1209
1210 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1211 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1212 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1213 }
1214
1215 if (has_msr_hv_frequencies) {
1216 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1217 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1218 }
1219
1220 if (has_msr_hv_crash) {
1221 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1222 }
1223
1224 if (has_msr_hv_reenlightenment) {
1225 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1226 }
1227
1228 if (has_msr_hv_reset) {
1229 entry_feat->eax |= HV_RESET_AVAILABLE;
1230 }
1231
1232 if (has_msr_hv_vpindex) {
1233 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1234 }
1235
1236 if (has_msr_hv_runtime) {
1237 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1238 }
1239
1240 if (has_msr_hv_synic) {
1241 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1242 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1243
1244 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1245 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1246 }
1247 }
1248
1249 if (has_msr_hv_stimer) {
1250 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1251 }
1252
1253 if (has_msr_hv_syndbg_options) {
1254 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1255 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1256 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1257 }
1258
1259 if (kvm_check_extension(cs->kvm_state,
1260 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1261 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1262 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1263 }
1264
1265 if (kvm_check_extension(cs->kvm_state,
1266 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1267 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1268 }
1269
1270 if (kvm_check_extension(cs->kvm_state,
1271 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1272 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1273 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1274 }
1275
1276 return cpuid;
1277 }
1278
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1279 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1280 {
1281 struct kvm_cpuid_entry2 *entry;
1282 struct kvm_cpuid2 *cpuid;
1283
1284 if (hv_cpuid_cache) {
1285 cpuid = hv_cpuid_cache;
1286 } else {
1287 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1288 cpuid = get_supported_hv_cpuid(cs);
1289 } else {
1290 /*
1291 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1292 * before KVM context is created but this is only done when
1293 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1294 * KVM_CAP_HYPERV_CPUID.
1295 */
1296 assert(cs->kvm_state);
1297
1298 cpuid = get_supported_hv_cpuid_legacy(cs);
1299 }
1300 hv_cpuid_cache = cpuid;
1301 }
1302
1303 if (!cpuid) {
1304 return 0;
1305 }
1306
1307 entry = cpuid_find_entry(cpuid, func, 0);
1308 if (!entry) {
1309 return 0;
1310 }
1311
1312 return cpuid_entry_get_reg(entry, reg);
1313 }
1314
hyperv_feature_supported(CPUState * cs,int feature)1315 static bool hyperv_feature_supported(CPUState *cs, int feature)
1316 {
1317 uint32_t func, bits;
1318 int i, reg;
1319
1320 /*
1321 * kvm_hyperv_properties needs to define at least one CPUID flag which
1322 * must be used to detect the feature, it's hard to say whether it is
1323 * supported or not otherwise.
1324 */
1325 assert(kvm_hyperv_properties[feature].flags[0].func);
1326
1327 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1328
1329 func = kvm_hyperv_properties[feature].flags[i].func;
1330 reg = kvm_hyperv_properties[feature].flags[i].reg;
1331 bits = kvm_hyperv_properties[feature].flags[i].bits;
1332
1333 if (!func) {
1334 continue;
1335 }
1336
1337 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1338 return false;
1339 }
1340 }
1341
1342 return true;
1343 }
1344
1345 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1346 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1347 {
1348 uint64_t deps;
1349 int dep_feat;
1350
1351 deps = kvm_hyperv_properties[feature].dependencies;
1352 while (deps) {
1353 dep_feat = ctz64(deps);
1354 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1355 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1356 kvm_hyperv_properties[feature].desc,
1357 kvm_hyperv_properties[dep_feat].desc);
1358 return false;
1359 }
1360 deps &= ~(1ull << dep_feat);
1361 }
1362
1363 return true;
1364 }
1365
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1366 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1367 {
1368 X86CPU *cpu = X86_CPU(cs);
1369 uint32_t r = 0;
1370 int i, j;
1371
1372 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1373 if (!hyperv_feat_enabled(cpu, i)) {
1374 continue;
1375 }
1376
1377 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1378 if (kvm_hyperv_properties[i].flags[j].func != func) {
1379 continue;
1380 }
1381 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1382 continue;
1383 }
1384
1385 r |= kvm_hyperv_properties[i].flags[j].bits;
1386 }
1387 }
1388
1389 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1390 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1391 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1392 r |= DEFAULT_EVMCS_VERSION;
1393 }
1394 }
1395
1396 return r;
1397 }
1398
1399 /*
1400 * Expand Hyper-V CPU features. In partucular, check that all the requested
1401 * features are supported by the host and the sanity of the configuration
1402 * (that all the required dependencies are included). Also, this takes care
1403 * of 'hv_passthrough' mode and fills the environment with all supported
1404 * Hyper-V features.
1405 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1406 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1407 {
1408 CPUState *cs = CPU(cpu);
1409 Error *local_err = NULL;
1410 int feat;
1411
1412 if (!hyperv_enabled(cpu))
1413 return true;
1414
1415 /*
1416 * When kvm_hyperv_expand_features is called at CPU feature expansion
1417 * time per-CPU kvm_state is not available yet so we can only proceed
1418 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1419 */
1420 if (!cs->kvm_state &&
1421 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1422 return true;
1423
1424 if (cpu->hyperv_passthrough) {
1425 cpu->hyperv_vendor_id[0] =
1426 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1427 cpu->hyperv_vendor_id[1] =
1428 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1429 cpu->hyperv_vendor_id[2] =
1430 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1431 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1432 sizeof(cpu->hyperv_vendor_id) + 1);
1433 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1434 sizeof(cpu->hyperv_vendor_id));
1435 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1436
1437 cpu->hyperv_interface_id[0] =
1438 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1439 cpu->hyperv_interface_id[1] =
1440 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1441 cpu->hyperv_interface_id[2] =
1442 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1443 cpu->hyperv_interface_id[3] =
1444 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1445
1446 cpu->hyperv_ver_id_build =
1447 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1448 cpu->hyperv_ver_id_major =
1449 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1450 cpu->hyperv_ver_id_minor =
1451 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1452 cpu->hyperv_ver_id_sp =
1453 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1454 cpu->hyperv_ver_id_sb =
1455 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1456 cpu->hyperv_ver_id_sn =
1457 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1458
1459 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1460 R_EAX);
1461 cpu->hyperv_limits[0] =
1462 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1463 cpu->hyperv_limits[1] =
1464 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1465 cpu->hyperv_limits[2] =
1466 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1467
1468 cpu->hyperv_spinlock_attempts =
1469 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1470
1471 /*
1472 * Mark feature as enabled in 'cpu->hyperv_features' as
1473 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1474 */
1475 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1476 if (hyperv_feature_supported(cs, feat) &&
1477 !kvm_hyperv_properties[feat].skip_passthrough) {
1478 cpu->hyperv_features |= BIT(feat);
1479 }
1480 }
1481 } else {
1482 /* Check features availability and dependencies */
1483 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1484 /* If the feature was not requested skip it. */
1485 if (!hyperv_feat_enabled(cpu, feat)) {
1486 continue;
1487 }
1488
1489 /* Check if the feature is supported by KVM */
1490 if (!hyperv_feature_supported(cs, feat)) {
1491 error_setg(errp, "Hyper-V %s is not supported by kernel",
1492 kvm_hyperv_properties[feat].desc);
1493 return false;
1494 }
1495
1496 /* Check dependencies */
1497 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1498 error_propagate(errp, local_err);
1499 return false;
1500 }
1501 }
1502 }
1503
1504 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1505 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1506 !cpu->hyperv_synic_kvm_only &&
1507 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1508 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1509 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1510 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1511 return false;
1512 }
1513
1514 return true;
1515 }
1516
1517 /*
1518 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1519 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1520 static int hyperv_fill_cpuids(CPUState *cs,
1521 struct kvm_cpuid_entry2 *cpuid_ent)
1522 {
1523 X86CPU *cpu = X86_CPU(cs);
1524 struct kvm_cpuid_entry2 *c;
1525 uint32_t signature[3];
1526 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1527 uint32_t nested_eax =
1528 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1529
1530 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1531 HV_CPUID_IMPLEMENT_LIMITS;
1532
1533 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1534 max_cpuid_leaf =
1535 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1536 }
1537
1538 c = &cpuid_ent[cpuid_i++];
1539 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1540 c->eax = max_cpuid_leaf;
1541 c->ebx = cpu->hyperv_vendor_id[0];
1542 c->ecx = cpu->hyperv_vendor_id[1];
1543 c->edx = cpu->hyperv_vendor_id[2];
1544
1545 c = &cpuid_ent[cpuid_i++];
1546 c->function = HV_CPUID_INTERFACE;
1547 c->eax = cpu->hyperv_interface_id[0];
1548 c->ebx = cpu->hyperv_interface_id[1];
1549 c->ecx = cpu->hyperv_interface_id[2];
1550 c->edx = cpu->hyperv_interface_id[3];
1551
1552 c = &cpuid_ent[cpuid_i++];
1553 c->function = HV_CPUID_VERSION;
1554 c->eax = cpu->hyperv_ver_id_build;
1555 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1556 cpu->hyperv_ver_id_minor;
1557 c->ecx = cpu->hyperv_ver_id_sp;
1558 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1559 (cpu->hyperv_ver_id_sn & 0xffffff);
1560
1561 c = &cpuid_ent[cpuid_i++];
1562 c->function = HV_CPUID_FEATURES;
1563 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1564 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1565 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1566
1567 /* Unconditionally required with any Hyper-V enlightenment */
1568 c->eax |= HV_HYPERCALL_AVAILABLE;
1569
1570 /* SynIC and Vmbus devices require messages/signals hypercalls */
1571 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1572 !cpu->hyperv_synic_kvm_only) {
1573 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1574 }
1575
1576
1577 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1578 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1579
1580 c = &cpuid_ent[cpuid_i++];
1581 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1582 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1583 c->ebx = cpu->hyperv_spinlock_attempts;
1584
1585 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1586 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1587 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1588 }
1589
1590 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1591 c->eax |= HV_NO_NONARCH_CORESHARING;
1592 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1593 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1594 HV_NO_NONARCH_CORESHARING;
1595 }
1596
1597 c = &cpuid_ent[cpuid_i++];
1598 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1599 c->eax = cpu->hv_max_vps;
1600 c->ebx = cpu->hyperv_limits[0];
1601 c->ecx = cpu->hyperv_limits[1];
1602 c->edx = cpu->hyperv_limits[2];
1603
1604 if (nested_eax) {
1605 uint32_t function;
1606
1607 /* Create zeroed 0x40000006..0x40000009 leaves */
1608 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1609 function < HV_CPUID_NESTED_FEATURES; function++) {
1610 c = &cpuid_ent[cpuid_i++];
1611 c->function = function;
1612 }
1613
1614 c = &cpuid_ent[cpuid_i++];
1615 c->function = HV_CPUID_NESTED_FEATURES;
1616 c->eax = nested_eax;
1617 }
1618
1619 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1620 c = &cpuid_ent[cpuid_i++];
1621 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1622 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1623 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1624 memcpy(signature, "Microsoft VS", 12);
1625 c->eax = 0;
1626 c->ebx = signature[0];
1627 c->ecx = signature[1];
1628 c->edx = signature[2];
1629
1630 c = &cpuid_ent[cpuid_i++];
1631 c->function = HV_CPUID_SYNDBG_INTERFACE;
1632 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1633 c->eax = signature[0];
1634 c->ebx = 0;
1635 c->ecx = 0;
1636 c->edx = 0;
1637
1638 c = &cpuid_ent[cpuid_i++];
1639 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1640 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1641 c->ebx = 0;
1642 c->ecx = 0;
1643 c->edx = 0;
1644 }
1645
1646 return cpuid_i;
1647 }
1648
1649 static Error *hv_passthrough_mig_blocker;
1650 static Error *hv_no_nonarch_cs_mig_blocker;
1651
1652 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1653 static bool evmcs_version_supported(uint16_t evmcs_version,
1654 uint16_t supported_evmcs_version)
1655 {
1656 uint8_t min_version = evmcs_version & 0xff;
1657 uint8_t max_version = evmcs_version >> 8;
1658 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1659 uint8_t max_supported_version = supported_evmcs_version >> 8;
1660
1661 return (min_version >= min_supported_version) &&
1662 (max_version <= max_supported_version);
1663 }
1664
hyperv_init_vcpu(X86CPU * cpu)1665 static int hyperv_init_vcpu(X86CPU *cpu)
1666 {
1667 CPUState *cs = CPU(cpu);
1668 Error *local_err = NULL;
1669 int ret;
1670
1671 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1672 error_setg(&hv_passthrough_mig_blocker,
1673 "'hv-passthrough' CPU flag prevents migration, use explicit"
1674 " set of hv-* flags instead");
1675 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1676 if (ret < 0) {
1677 error_report_err(local_err);
1678 return ret;
1679 }
1680 }
1681
1682 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1683 hv_no_nonarch_cs_mig_blocker == NULL) {
1684 error_setg(&hv_no_nonarch_cs_mig_blocker,
1685 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1686 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1687 " make sure SMT is disabled and/or that vCPUs are properly"
1688 " pinned)");
1689 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1690 if (ret < 0) {
1691 error_report_err(local_err);
1692 return ret;
1693 }
1694 }
1695
1696 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1697 /*
1698 * the kernel doesn't support setting vp_index; assert that its value
1699 * is in sync
1700 */
1701 uint64_t value;
1702
1703 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1704 if (ret < 0) {
1705 return ret;
1706 }
1707
1708 if (value != hyperv_vp_index(CPU(cpu))) {
1709 error_report("kernel's vp_index != QEMU's vp_index");
1710 return -ENXIO;
1711 }
1712 }
1713
1714 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1715 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1716 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1717 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1718 if (ret < 0) {
1719 error_report("failed to turn on HyperV SynIC in KVM: %s",
1720 strerror(-ret));
1721 return ret;
1722 }
1723
1724 if (!cpu->hyperv_synic_kvm_only) {
1725 ret = hyperv_x86_synic_add(cpu);
1726 if (ret < 0) {
1727 error_report("failed to create HyperV SynIC: %s",
1728 strerror(-ret));
1729 return ret;
1730 }
1731 }
1732 }
1733
1734 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1735 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1736 uint16_t supported_evmcs_version;
1737
1738 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1739 (uintptr_t)&supported_evmcs_version);
1740
1741 /*
1742 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1743 * option sets. Note: we hardcode the maximum supported eVMCS version
1744 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1745 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1746 * to be added.
1747 */
1748 if (ret < 0) {
1749 error_report("Hyper-V %s is not supported by kernel",
1750 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1751 return ret;
1752 }
1753
1754 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1755 error_report("eVMCS version range [%d..%d] is not supported by "
1756 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1757 evmcs_version >> 8, supported_evmcs_version & 0xff,
1758 supported_evmcs_version >> 8);
1759 return -ENOTSUP;
1760 }
1761 }
1762
1763 if (cpu->hyperv_enforce_cpuid) {
1764 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1765 if (ret < 0) {
1766 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1767 strerror(-ret));
1768 return ret;
1769 }
1770 }
1771
1772 /* Skip SynIC and VP_INDEX since they are hard deps already */
1773 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1774 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1775 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1776 hyperv_x86_set_vmbus_recommended_features_enabled();
1777 }
1778
1779 return 0;
1780 }
1781
1782 static Error *invtsc_mig_blocker;
1783
1784 #define KVM_MAX_CPUID_ENTRIES 100
1785
kvm_init_xsave(CPUX86State * env)1786 static void kvm_init_xsave(CPUX86State *env)
1787 {
1788 if (has_xsave2) {
1789 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1790 } else {
1791 env->xsave_buf_len = sizeof(struct kvm_xsave);
1792 }
1793
1794 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1795 memset(env->xsave_buf, 0, env->xsave_buf_len);
1796 /*
1797 * The allocated storage must be large enough for all of the
1798 * possible XSAVE state components.
1799 */
1800 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1801 env->xsave_buf_len);
1802 }
1803
kvm_init_nested_state(CPUX86State * env)1804 static void kvm_init_nested_state(CPUX86State *env)
1805 {
1806 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1807 uint32_t size;
1808
1809 if (!env->nested_state) {
1810 return;
1811 }
1812
1813 size = env->nested_state->size;
1814
1815 memset(env->nested_state, 0, size);
1816 env->nested_state->size = size;
1817
1818 if (cpu_has_vmx(env)) {
1819 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1820 vmx_hdr = &env->nested_state->hdr.vmx;
1821 vmx_hdr->vmxon_pa = -1ull;
1822 vmx_hdr->vmcs12_pa = -1ull;
1823 } else if (cpu_has_svm(env)) {
1824 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1825 }
1826 }
1827
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1828 static uint32_t kvm_x86_build_cpuid(CPUX86State *env,
1829 struct kvm_cpuid_entry2 *entries,
1830 uint32_t cpuid_i)
1831 {
1832 uint32_t limit, i, j;
1833 uint32_t unused;
1834 struct kvm_cpuid_entry2 *c;
1835
1836 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1837
1838 for (i = 0; i <= limit; i++) {
1839 j = 0;
1840 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1841 goto full;
1842 }
1843 c = &entries[cpuid_i++];
1844 switch (i) {
1845 case 2: {
1846 /* Keep reading function 2 till all the input is received */
1847 int times;
1848
1849 c->function = i;
1850 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1851 times = c->eax & 0xff;
1852 if (times > 1) {
1853 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1854 KVM_CPUID_FLAG_STATE_READ_NEXT;
1855 }
1856
1857 for (j = 1; j < times; ++j) {
1858 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1859 goto full;
1860 }
1861 c = &entries[cpuid_i++];
1862 c->function = i;
1863 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1864 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1865 }
1866 break;
1867 }
1868 case 0x1f:
1869 if (!x86_has_extended_topo(env->avail_cpu_topo)) {
1870 cpuid_i--;
1871 break;
1872 }
1873 /* fallthrough */
1874 case 4:
1875 case 0xb:
1876 case 0xd:
1877 for (j = 0; ; j++) {
1878 c->function = i;
1879 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1880 c->index = j;
1881 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1882
1883 if (i == 4 && c->eax == 0) {
1884 break;
1885 }
1886 if (i == 0xb && !(c->ecx & 0xff00)) {
1887 break;
1888 }
1889 if (i == 0x1f && !(c->ecx & 0xff00)) {
1890 break;
1891 }
1892 if (i == 0xd && c->eax == 0) {
1893 if (j < 63) {
1894 continue;
1895 } else {
1896 cpuid_i--;
1897 break;
1898 }
1899 }
1900 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1901 goto full;
1902 }
1903 c = &entries[cpuid_i++];
1904 }
1905 break;
1906 case 0x12:
1907 for (j = 0; ; j++) {
1908 c->function = i;
1909 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1910 c->index = j;
1911 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1912
1913 if (j > 1 && (c->eax & 0xf) != 1) {
1914 break;
1915 }
1916
1917 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1918 goto full;
1919 }
1920 c = &entries[cpuid_i++];
1921 }
1922 break;
1923 case 0x7:
1924 case 0x14:
1925 case 0x1d:
1926 case 0x1e:
1927 case 0x24: {
1928 uint32_t times;
1929
1930 c->function = i;
1931 c->index = 0;
1932 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1933 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1934 times = c->eax;
1935
1936 for (j = 1; j <= times; ++j) {
1937 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1938 goto full;
1939 }
1940 c = &entries[cpuid_i++];
1941 c->function = i;
1942 c->index = j;
1943 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1944 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1945 }
1946 break;
1947 }
1948 default:
1949 c->function = i;
1950 c->flags = 0;
1951 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1952 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1953 /*
1954 * KVM already returns all zeroes if a CPUID entry is missing,
1955 * so we can omit it and avoid hitting KVM's 80-entry limit.
1956 */
1957 cpuid_i--;
1958 }
1959 break;
1960 }
1961 }
1962
1963 if (limit >= 0x0a) {
1964 uint32_t eax, edx;
1965
1966 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1967
1968 has_architectural_pmu_version = eax & 0xff;
1969 if (has_architectural_pmu_version > 0) {
1970 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1971
1972 /* Shouldn't be more than 32, since that's the number of bits
1973 * available in EBX to tell us _which_ counters are available.
1974 * Play it safe.
1975 */
1976 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1977 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1978 }
1979
1980 if (has_architectural_pmu_version > 1) {
1981 num_architectural_pmu_fixed_counters = edx & 0x1f;
1982
1983 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1984 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1985 }
1986 }
1987 }
1988 }
1989
1990 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1991
1992 for (i = 0x80000000; i <= limit; i++) {
1993 j = 0;
1994 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1995 goto full;
1996 }
1997 c = &entries[cpuid_i++];
1998
1999 switch (i) {
2000 case 0x8000001d:
2001 /* Query for all AMD cache information leaves */
2002 for (j = 0; ; j++) {
2003 c->function = i;
2004 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2005 c->index = j;
2006 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2007
2008 if (c->eax == 0) {
2009 break;
2010 }
2011 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2012 goto full;
2013 }
2014 c = &entries[cpuid_i++];
2015 }
2016 break;
2017 default:
2018 c->function = i;
2019 c->flags = 0;
2020 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2021 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2022 /*
2023 * KVM already returns all zeroes if a CPUID entry is missing,
2024 * so we can omit it and avoid hitting KVM's 80-entry limit.
2025 */
2026 cpuid_i--;
2027 }
2028 break;
2029 }
2030 }
2031
2032 /* Call Centaur's CPUID instructions they are supported. */
2033 if (env->cpuid_xlevel2 > 0) {
2034 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2035
2036 for (i = 0xC0000000; i <= limit; i++) {
2037 j = 0;
2038 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2039 goto full;
2040 }
2041 c = &entries[cpuid_i++];
2042
2043 c->function = i;
2044 c->flags = 0;
2045 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2046 }
2047 }
2048
2049 return cpuid_i;
2050
2051 full:
2052 fprintf(stderr, "cpuid_data is full, no space for "
2053 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2054 abort();
2055 }
2056
kvm_arch_init_vcpu(CPUState * cs)2057 int kvm_arch_init_vcpu(CPUState *cs)
2058 {
2059 struct {
2060 struct kvm_cpuid2 cpuid;
2061 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2062 } cpuid_data;
2063 /*
2064 * The kernel defines these structs with padding fields so there
2065 * should be no extra padding in our cpuid_data struct.
2066 */
2067 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2068 sizeof(struct kvm_cpuid2) +
2069 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2070
2071 X86CPU *cpu = X86_CPU(cs);
2072 CPUX86State *env = &cpu->env;
2073 uint32_t cpuid_i;
2074 struct kvm_cpuid_entry2 *c;
2075 uint32_t signature[3];
2076 int kvm_base = KVM_CPUID_SIGNATURE;
2077 int max_nested_state_len;
2078 int r;
2079 Error *local_err = NULL;
2080
2081 memset(&cpuid_data, 0, sizeof(cpuid_data));
2082
2083 cpuid_i = 0;
2084
2085 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2086
2087 r = kvm_arch_set_tsc_khz(cs);
2088 if (r < 0) {
2089 return r;
2090 }
2091
2092 /* vcpu's TSC frequency is either specified by user, or following
2093 * the value used by KVM if the former is not present. In the
2094 * latter case, we query it from KVM and record in env->tsc_khz,
2095 * so that vcpu's TSC frequency can be migrated later via this field.
2096 */
2097 if (!env->tsc_khz) {
2098 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2099 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2100 -ENOTSUP;
2101 if (r > 0) {
2102 env->tsc_khz = r;
2103 }
2104 }
2105
2106 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2107
2108 /*
2109 * kvm_hyperv_expand_features() is called here for the second time in case
2110 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2111 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2112 * check which Hyper-V enlightenments are supported and which are not, we
2113 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2114 * behavior is preserved.
2115 */
2116 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2117 error_report_err(local_err);
2118 return -ENOSYS;
2119 }
2120
2121 if (hyperv_enabled(cpu)) {
2122 r = hyperv_init_vcpu(cpu);
2123 if (r) {
2124 return r;
2125 }
2126
2127 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2128 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2129 has_msr_hv_hypercall = true;
2130 }
2131
2132 if (cs->kvm_state->xen_version) {
2133 #ifdef CONFIG_XEN_EMU
2134 struct kvm_cpuid_entry2 *xen_max_leaf;
2135
2136 memcpy(signature, "XenVMMXenVMM", 12);
2137
2138 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2139 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2140 c->eax = kvm_base + XEN_CPUID_TIME;
2141 c->ebx = signature[0];
2142 c->ecx = signature[1];
2143 c->edx = signature[2];
2144
2145 c = &cpuid_data.entries[cpuid_i++];
2146 c->function = kvm_base + XEN_CPUID_VENDOR;
2147 c->eax = cs->kvm_state->xen_version;
2148 c->ebx = 0;
2149 c->ecx = 0;
2150 c->edx = 0;
2151
2152 c = &cpuid_data.entries[cpuid_i++];
2153 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2154 /* Number of hypercall-transfer pages */
2155 c->eax = 1;
2156 /* Hypercall MSR base address */
2157 if (hyperv_enabled(cpu)) {
2158 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2159 kvm_xen_init(cs->kvm_state, c->ebx);
2160 } else {
2161 c->ebx = XEN_HYPERCALL_MSR;
2162 }
2163 c->ecx = 0;
2164 c->edx = 0;
2165
2166 c = &cpuid_data.entries[cpuid_i++];
2167 c->function = kvm_base + XEN_CPUID_TIME;
2168 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2169 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2170 /* default=0 (emulate if necessary) */
2171 c->ebx = 0;
2172 /* guest tsc frequency */
2173 c->ecx = env->user_tsc_khz;
2174 /* guest tsc incarnation (migration count) */
2175 c->edx = 0;
2176
2177 c = &cpuid_data.entries[cpuid_i++];
2178 c->function = kvm_base + XEN_CPUID_HVM;
2179 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2180 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2181 c->function = kvm_base + XEN_CPUID_HVM;
2182
2183 if (cpu->xen_vapic) {
2184 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2185 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2186 }
2187
2188 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2189
2190 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2191 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2192 c->ebx = cs->cpu_index;
2193 }
2194
2195 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2196 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2197 }
2198 }
2199
2200 r = kvm_xen_init_vcpu(cs);
2201 if (r) {
2202 return r;
2203 }
2204
2205 kvm_base += 0x100;
2206 #else /* CONFIG_XEN_EMU */
2207 /* This should never happen as kvm_arch_init() would have died first. */
2208 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2209 abort();
2210 #endif
2211 } else if (cpu->expose_kvm) {
2212 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2213 c = &cpuid_data.entries[cpuid_i++];
2214 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2215 c->eax = KVM_CPUID_FEATURES | kvm_base;
2216 c->ebx = signature[0];
2217 c->ecx = signature[1];
2218 c->edx = signature[2];
2219
2220 c = &cpuid_data.entries[cpuid_i++];
2221 c->function = KVM_CPUID_FEATURES | kvm_base;
2222 c->eax = env->features[FEAT_KVM];
2223 c->edx = env->features[FEAT_KVM_HINTS];
2224 }
2225
2226 if (cpu->kvm_pv_enforce_cpuid) {
2227 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2228 if (r < 0) {
2229 fprintf(stderr,
2230 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2231 strerror(-r));
2232 abort();
2233 }
2234 }
2235
2236 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2237 cpuid_data.cpuid.nent = cpuid_i;
2238
2239 if (((env->cpuid_version >> 8)&0xF) >= 6
2240 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2241 (CPUID_MCE | CPUID_MCA)) {
2242 uint64_t mcg_cap, unsupported_caps;
2243 int banks;
2244 int ret;
2245
2246 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2247 if (ret < 0) {
2248 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2249 return ret;
2250 }
2251
2252 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2253 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2254 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2255 return -ENOTSUP;
2256 }
2257
2258 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2259 if (unsupported_caps) {
2260 if (unsupported_caps & MCG_LMCE_P) {
2261 error_report("kvm: LMCE not supported");
2262 return -ENOTSUP;
2263 }
2264 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2265 unsupported_caps);
2266 }
2267
2268 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2269 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2270 if (ret < 0) {
2271 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2272 return ret;
2273 }
2274 }
2275
2276 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2277
2278 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2279 if (c) {
2280 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2281 !!(c->ecx & CPUID_EXT_SMX);
2282 }
2283
2284 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2285 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2286 has_msr_feature_control = true;
2287 }
2288
2289 if (env->mcg_cap & MCG_LMCE_P) {
2290 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2291 }
2292
2293 if (!env->user_tsc_khz) {
2294 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2295 invtsc_mig_blocker == NULL) {
2296 error_setg(&invtsc_mig_blocker,
2297 "State blocked by non-migratable CPU device"
2298 " (invtsc flag)");
2299 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2300 if (r < 0) {
2301 error_report_err(local_err);
2302 return r;
2303 }
2304 }
2305 }
2306
2307 if (cpu->vmware_cpuid_freq
2308 /* Guests depend on 0x40000000 to detect this feature, so only expose
2309 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2310 && cpu->expose_kvm
2311 && kvm_base == KVM_CPUID_SIGNATURE
2312 /* TSC clock must be stable and known for this feature. */
2313 && tsc_is_stable_and_known(env)) {
2314
2315 c = &cpuid_data.entries[cpuid_i++];
2316 c->function = KVM_CPUID_SIGNATURE | 0x10;
2317 c->eax = env->tsc_khz;
2318 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2319 c->ecx = c->edx = 0;
2320
2321 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2322 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2323 }
2324
2325 cpuid_data.cpuid.nent = cpuid_i;
2326
2327 cpuid_data.cpuid.padding = 0;
2328 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2329 if (r) {
2330 goto fail;
2331 }
2332 kvm_init_xsave(env);
2333
2334 max_nested_state_len = kvm_max_nested_state_length();
2335 if (max_nested_state_len > 0) {
2336 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2337
2338 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2339 env->nested_state = g_malloc0(max_nested_state_len);
2340 env->nested_state->size = max_nested_state_len;
2341
2342 kvm_init_nested_state(env);
2343 }
2344 }
2345
2346 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2347
2348 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2349 has_msr_tsc_aux = false;
2350 }
2351
2352 kvm_init_msrs(cpu);
2353
2354 return 0;
2355
2356 fail:
2357 migrate_del_blocker(&invtsc_mig_blocker);
2358
2359 return r;
2360 }
2361
kvm_arch_destroy_vcpu(CPUState * cs)2362 int kvm_arch_destroy_vcpu(CPUState *cs)
2363 {
2364 X86CPU *cpu = X86_CPU(cs);
2365 CPUX86State *env = &cpu->env;
2366
2367 g_free(env->xsave_buf);
2368
2369 g_free(cpu->kvm_msr_buf);
2370 cpu->kvm_msr_buf = NULL;
2371
2372 g_free(env->nested_state);
2373 env->nested_state = NULL;
2374
2375 qemu_del_vm_change_state_handler(cpu->vmsentry);
2376
2377 return 0;
2378 }
2379
kvm_arch_reset_vcpu(X86CPU * cpu)2380 void kvm_arch_reset_vcpu(X86CPU *cpu)
2381 {
2382 CPUX86State *env = &cpu->env;
2383
2384 env->xcr0 = 1;
2385 if (kvm_irqchip_in_kernel()) {
2386 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2387 KVM_MP_STATE_UNINITIALIZED;
2388 } else {
2389 env->mp_state = KVM_MP_STATE_RUNNABLE;
2390 }
2391
2392 /* enabled by default */
2393 env->poll_control_msr = 1;
2394
2395 kvm_init_nested_state(env);
2396
2397 sev_es_set_reset_vector(CPU(cpu));
2398 }
2399
kvm_arch_after_reset_vcpu(X86CPU * cpu)2400 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2401 {
2402 CPUX86State *env = &cpu->env;
2403 int i;
2404
2405 /*
2406 * Reset SynIC after all other devices have been reset to let them remove
2407 * their SINT routes first.
2408 */
2409 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2410 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2411 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2412 }
2413
2414 hyperv_x86_synic_reset(cpu);
2415 }
2416 }
2417
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2418 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2419 {
2420 g_autofree struct kvm_msrs *msrs = NULL;
2421
2422 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2423 msrs->entries[0].index = MSR_IA32_TSC;
2424 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2425 msrs->nmsrs++;
2426
2427 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2428 warn_report("parked vCPU %lu TSC reset failed: %d",
2429 vcpu_id, errno);
2430 }
2431 }
2432
kvm_arch_do_init_vcpu(X86CPU * cpu)2433 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2434 {
2435 CPUX86State *env = &cpu->env;
2436
2437 /* APs get directly into wait-for-SIPI state. */
2438 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2439 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2440 }
2441 }
2442
kvm_get_supported_feature_msrs(KVMState * s)2443 static int kvm_get_supported_feature_msrs(KVMState *s)
2444 {
2445 int ret = 0;
2446
2447 if (kvm_feature_msrs != NULL) {
2448 return 0;
2449 }
2450
2451 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2452 return 0;
2453 }
2454
2455 struct kvm_msr_list msr_list;
2456
2457 msr_list.nmsrs = 0;
2458 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2459 if (ret < 0 && ret != -E2BIG) {
2460 error_report("Fetch KVM feature MSR list failed: %s",
2461 strerror(-ret));
2462 return ret;
2463 }
2464
2465 assert(msr_list.nmsrs > 0);
2466 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2467 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2468
2469 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2470 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2471
2472 if (ret < 0) {
2473 error_report("Fetch KVM feature MSR list failed: %s",
2474 strerror(-ret));
2475 g_free(kvm_feature_msrs);
2476 kvm_feature_msrs = NULL;
2477 return ret;
2478 }
2479
2480 return 0;
2481 }
2482
kvm_get_supported_msrs(KVMState * s)2483 static int kvm_get_supported_msrs(KVMState *s)
2484 {
2485 int ret = 0;
2486 struct kvm_msr_list msr_list, *kvm_msr_list;
2487
2488 /*
2489 * Obtain MSR list from KVM. These are the MSRs that we must
2490 * save/restore.
2491 */
2492 msr_list.nmsrs = 0;
2493 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2494 if (ret < 0 && ret != -E2BIG) {
2495 return ret;
2496 }
2497 /*
2498 * Old kernel modules had a bug and could write beyond the provided
2499 * memory. Allocate at least a safe amount of 1K.
2500 */
2501 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2502 msr_list.nmsrs *
2503 sizeof(msr_list.indices[0])));
2504
2505 kvm_msr_list->nmsrs = msr_list.nmsrs;
2506 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2507 if (ret >= 0) {
2508 int i;
2509
2510 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2511 switch (kvm_msr_list->indices[i]) {
2512 case MSR_STAR:
2513 has_msr_star = true;
2514 break;
2515 case MSR_VM_HSAVE_PA:
2516 has_msr_hsave_pa = true;
2517 break;
2518 case MSR_TSC_AUX:
2519 has_msr_tsc_aux = true;
2520 break;
2521 case MSR_TSC_ADJUST:
2522 has_msr_tsc_adjust = true;
2523 break;
2524 case MSR_IA32_TSCDEADLINE:
2525 has_msr_tsc_deadline = true;
2526 break;
2527 case MSR_IA32_SMBASE:
2528 has_msr_smbase = true;
2529 break;
2530 case MSR_SMI_COUNT:
2531 has_msr_smi_count = true;
2532 break;
2533 case MSR_IA32_MISC_ENABLE:
2534 has_msr_misc_enable = true;
2535 break;
2536 case MSR_IA32_BNDCFGS:
2537 has_msr_bndcfgs = true;
2538 break;
2539 case MSR_IA32_XSS:
2540 has_msr_xss = true;
2541 break;
2542 case MSR_IA32_UMWAIT_CONTROL:
2543 has_msr_umwait = true;
2544 break;
2545 case HV_X64_MSR_CRASH_CTL:
2546 has_msr_hv_crash = true;
2547 break;
2548 case HV_X64_MSR_RESET:
2549 has_msr_hv_reset = true;
2550 break;
2551 case HV_X64_MSR_VP_INDEX:
2552 has_msr_hv_vpindex = true;
2553 break;
2554 case HV_X64_MSR_VP_RUNTIME:
2555 has_msr_hv_runtime = true;
2556 break;
2557 case HV_X64_MSR_SCONTROL:
2558 has_msr_hv_synic = true;
2559 break;
2560 case HV_X64_MSR_STIMER0_CONFIG:
2561 has_msr_hv_stimer = true;
2562 break;
2563 case HV_X64_MSR_TSC_FREQUENCY:
2564 has_msr_hv_frequencies = true;
2565 break;
2566 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2567 has_msr_hv_reenlightenment = true;
2568 break;
2569 case HV_X64_MSR_SYNDBG_OPTIONS:
2570 has_msr_hv_syndbg_options = true;
2571 break;
2572 case MSR_IA32_SPEC_CTRL:
2573 has_msr_spec_ctrl = true;
2574 break;
2575 case MSR_AMD64_TSC_RATIO:
2576 has_tsc_scale_msr = true;
2577 break;
2578 case MSR_IA32_TSX_CTRL:
2579 has_msr_tsx_ctrl = true;
2580 break;
2581 case MSR_VIRT_SSBD:
2582 has_msr_virt_ssbd = true;
2583 break;
2584 case MSR_IA32_ARCH_CAPABILITIES:
2585 has_msr_arch_capabs = true;
2586 break;
2587 case MSR_IA32_CORE_CAPABILITY:
2588 has_msr_core_capabs = true;
2589 break;
2590 case MSR_IA32_PERF_CAPABILITIES:
2591 has_msr_perf_capabs = true;
2592 break;
2593 case MSR_IA32_VMX_VMFUNC:
2594 has_msr_vmx_vmfunc = true;
2595 break;
2596 case MSR_IA32_UCODE_REV:
2597 has_msr_ucode_rev = true;
2598 break;
2599 case MSR_IA32_VMX_PROCBASED_CTLS2:
2600 has_msr_vmx_procbased_ctls2 = true;
2601 break;
2602 case MSR_IA32_PKRS:
2603 has_msr_pkrs = true;
2604 break;
2605 case MSR_K7_HWCR:
2606 has_msr_hwcr = true;
2607 }
2608 }
2609 }
2610
2611 g_free(kvm_msr_list);
2612
2613 return ret;
2614 }
2615
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2616 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2617 uint32_t msr,
2618 uint64_t *val)
2619 {
2620 CPUState *cs = CPU(cpu);
2621
2622 *val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
2623 *val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
2624
2625 return true;
2626 }
2627
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2628 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2629 uint32_t msr,
2630 uint64_t *val)
2631 {
2632
2633 CPUState *cs = CPU(cpu);
2634
2635 *val = cs->kvm_state->msr_energy.msr_unit;
2636
2637 return true;
2638 }
2639
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2640 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2641 uint32_t msr,
2642 uint64_t *val)
2643 {
2644
2645 CPUState *cs = CPU(cpu);
2646
2647 *val = cs->kvm_state->msr_energy.msr_limit;
2648
2649 return true;
2650 }
2651
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2652 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2653 uint32_t msr,
2654 uint64_t *val)
2655 {
2656
2657 CPUState *cs = CPU(cpu);
2658
2659 *val = cs->kvm_state->msr_energy.msr_info;
2660
2661 return true;
2662 }
2663
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2664 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2665 uint32_t msr,
2666 uint64_t *val)
2667 {
2668
2669 CPUState *cs = CPU(cpu);
2670 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2671
2672 return true;
2673 }
2674
2675 static Notifier smram_machine_done;
2676 static KVMMemoryListener smram_listener;
2677 static AddressSpace smram_address_space;
2678 static MemoryRegion smram_as_root;
2679 static MemoryRegion smram_as_mem;
2680
register_smram_listener(Notifier * n,void * unused)2681 static void register_smram_listener(Notifier *n, void *unused)
2682 {
2683 MemoryRegion *smram =
2684 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2685
2686 /* Outer container... */
2687 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2688 memory_region_set_enabled(&smram_as_root, true);
2689
2690 /* ... with two regions inside: normal system memory with low
2691 * priority, and...
2692 */
2693 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2694 get_system_memory(), 0, ~0ull);
2695 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2696 memory_region_set_enabled(&smram_as_mem, true);
2697
2698 if (smram) {
2699 /* ... SMRAM with higher priority */
2700 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2701 memory_region_set_enabled(smram, true);
2702 }
2703
2704 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2705 kvm_memory_listener_register(kvm_state, &smram_listener,
2706 &smram_address_space, 1, "kvm-smram");
2707 }
2708
kvm_msr_energy_thread(void * data)2709 static void *kvm_msr_energy_thread(void *data)
2710 {
2711 KVMState *s = data;
2712 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2713
2714 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2715 g_autofree vmsr_thread_stat *thd_stat = NULL;
2716 g_autofree CPUState *cpu = NULL;
2717 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2718 unsigned int num_threads = 0;
2719
2720 X86CPUTopoIDs topo_ids;
2721
2722 rcu_register_thread();
2723
2724 /* Allocate memory for each package energy status */
2725 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2726
2727 /* Allocate memory for thread stats */
2728 thd_stat = g_new0(vmsr_thread_stat, 1);
2729
2730 /* Allocate memory for holding virtual package energy counter */
2731 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2732
2733 /* Populate the max tick of each packages */
2734 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2735 /*
2736 * Max numbers of ticks per package
2737 * Time in second * Number of ticks/second * Number of cores/package
2738 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2739 */
2740 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2741 * sysconf(_SC_CLK_TCK)
2742 * vmsr->host_topo.pkg_cpu_count[i];
2743 }
2744
2745 while (true) {
2746 /* Get all qemu threads id */
2747 g_autofree pid_t *thread_ids
2748 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2749
2750 if (thread_ids == NULL) {
2751 goto clean;
2752 }
2753
2754 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2755 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2756 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2757
2758 /* Populate all the thread stats */
2759 for (int i = 0; i < num_threads; i++) {
2760 thd_stat[i].utime = g_new0(unsigned long long, 2);
2761 thd_stat[i].stime = g_new0(unsigned long long, 2);
2762 thd_stat[i].thread_id = thread_ids[i];
2763 vmsr_read_thread_stat(vmsr->pid,
2764 thd_stat[i].thread_id,
2765 &thd_stat[i].utime[0],
2766 &thd_stat[i].stime[0],
2767 &thd_stat[i].cpu_id);
2768 thd_stat[i].pkg_id =
2769 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2770 }
2771
2772 /* Retrieve all packages power plane energy counter */
2773 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2774 for (int j = 0; j < num_threads; j++) {
2775 /*
2776 * Use the first thread we found that ran on the CPU
2777 * of the package to read the packages energy counter
2778 */
2779 if (thd_stat[j].pkg_id == i) {
2780 pkg_stat[i].e_start =
2781 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2782 thd_stat[j].cpu_id,
2783 thd_stat[j].thread_id,
2784 s->msr_energy.sioc);
2785 break;
2786 }
2787 }
2788 }
2789
2790 /* Sleep a short period while the other threads are working */
2791 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2792
2793 /*
2794 * Retrieve all packages power plane energy counter
2795 * Calculate the delta of all packages
2796 */
2797 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2798 for (int j = 0; j < num_threads; j++) {
2799 /*
2800 * Use the first thread we found that ran on the CPU
2801 * of the package to read the packages energy counter
2802 */
2803 if (thd_stat[j].pkg_id == i) {
2804 pkg_stat[i].e_end =
2805 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2806 thd_stat[j].cpu_id,
2807 thd_stat[j].thread_id,
2808 s->msr_energy.sioc);
2809 /*
2810 * Prevent the case we have migrate the VM
2811 * during the sleep period or any other cases
2812 * were energy counter might be lower after
2813 * the sleep period.
2814 */
2815 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2816 pkg_stat[i].e_delta =
2817 pkg_stat[i].e_end - pkg_stat[i].e_start;
2818 } else {
2819 pkg_stat[i].e_delta = 0;
2820 }
2821 break;
2822 }
2823 }
2824 }
2825
2826 /* Delta of ticks spend by each thread between the sample */
2827 for (int i = 0; i < num_threads; i++) {
2828 vmsr_read_thread_stat(vmsr->pid,
2829 thd_stat[i].thread_id,
2830 &thd_stat[i].utime[1],
2831 &thd_stat[i].stime[1],
2832 &thd_stat[i].cpu_id);
2833
2834 if (vmsr->pid < 0) {
2835 /*
2836 * We don't count the dead thread
2837 * i.e threads that existed before the sleep
2838 * and not anymore
2839 */
2840 thd_stat[i].delta_ticks = 0;
2841 } else {
2842 vmsr_delta_ticks(thd_stat, i);
2843 }
2844 }
2845
2846 /*
2847 * Identify the vcpu threads
2848 * Calculate the number of vcpu per package
2849 */
2850 CPU_FOREACH(cpu) {
2851 for (int i = 0; i < num_threads; i++) {
2852 if (cpu->thread_id == thd_stat[i].thread_id) {
2853 thd_stat[i].is_vcpu = true;
2854 thd_stat[i].vcpu_id = cpu->cpu_index;
2855 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2856 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2857 break;
2858 }
2859 }
2860 }
2861
2862 /* Retrieve the virtual package number of each vCPU */
2863 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2864 for (int j = 0; j < num_threads; j++) {
2865 if ((thd_stat[j].acpi_id ==
2866 vmsr->guest_cpu_list->cpus[i].arch_id)
2867 && (thd_stat[j].is_vcpu == true)) {
2868 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2869 &vmsr->guest_topo_info, &topo_ids);
2870 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2871 }
2872 }
2873 }
2874
2875 /* Calculate the total energy of all non-vCPU thread */
2876 for (int i = 0; i < num_threads; i++) {
2877 if ((thd_stat[i].is_vcpu != true) &&
2878 (thd_stat[i].delta_ticks > 0)) {
2879 double temp;
2880 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2881 thd_stat[i].delta_ticks,
2882 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2883 pkg_stat[thd_stat[i].pkg_id].e_ratio
2884 += (uint64_t)lround(temp);
2885 }
2886 }
2887
2888 /* Calculate the ratio per non-vCPU thread of each package */
2889 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2890 if (pkg_stat[i].nb_vcpu > 0) {
2891 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2892 }
2893 }
2894
2895 /*
2896 * Calculate the energy for each Package:
2897 * Energy Package = sum of each vCPU energy that belongs to the package
2898 */
2899 for (int i = 0; i < num_threads; i++) {
2900 if ((thd_stat[i].is_vcpu == true) && \
2901 (thd_stat[i].delta_ticks > 0)) {
2902 double temp;
2903 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2904 thd_stat[i].delta_ticks,
2905 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2906 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2907 (uint64_t)lround(temp);
2908 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2909 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2910 }
2911 }
2912
2913 /*
2914 * Finally populate the vmsr register of each vCPU with the total
2915 * package value to emulate the real hardware where each CPU return the
2916 * value of the package it belongs.
2917 */
2918 for (int i = 0; i < num_threads; i++) {
2919 if ((thd_stat[i].is_vcpu == true) && \
2920 (thd_stat[i].delta_ticks > 0)) {
2921 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2922 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2923 }
2924 }
2925
2926 /* Freeing memory before zeroing the pointer */
2927 for (int i = 0; i < num_threads; i++) {
2928 g_free(thd_stat[i].utime);
2929 g_free(thd_stat[i].stime);
2930 }
2931 }
2932
2933 clean:
2934 rcu_unregister_thread();
2935 return NULL;
2936 }
2937
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2938 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2939 {
2940 MachineClass *mc = MACHINE_GET_CLASS(ms);
2941 struct KVMMsrEnergy *r = &s->msr_energy;
2942 int ret = 0;
2943
2944 /*
2945 * Sanity check
2946 * 1. Host cpu must be Intel cpu
2947 * 2. RAPL must be enabled on the Host
2948 */
2949 if (!is_host_cpu_intel()) {
2950 error_report("The RAPL feature can only be enabled on hosts "
2951 "with Intel CPU models");
2952 ret = 1;
2953 goto out;
2954 }
2955
2956 if (!is_rapl_enabled()) {
2957 ret = 1;
2958 goto out;
2959 }
2960
2961 /* Retrieve the virtual topology */
2962 vmsr_init_topo_info(&r->guest_topo_info, ms);
2963
2964 /* Retrieve the number of vcpu */
2965 r->guest_vcpus = ms->smp.cpus;
2966
2967 /* Retrieve the number of virtual sockets */
2968 r->guest_vsockets = ms->smp.sockets;
2969
2970 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
2971 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
2972
2973 /* Retrieve the CPUArchIDlist */
2974 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
2975
2976 /* Max number of cpus on the Host */
2977 r->host_topo.maxcpus = vmsr_get_maxcpus();
2978 if (r->host_topo.maxcpus == 0) {
2979 error_report("host max cpus = 0");
2980 ret = 1;
2981 goto out;
2982 }
2983
2984 /* Max number of packages on the host */
2985 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
2986 if (r->host_topo.maxpkgs == 0) {
2987 error_report("host max pkgs = 0");
2988 ret = 1;
2989 goto out;
2990 }
2991
2992 /* Allocate memory for each package on the host */
2993 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
2994 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
2995
2996 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
2997 r->host_topo.maxpkgs);
2998 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
2999 if (r->host_topo.pkg_cpu_count[i] == 0) {
3000 error_report("cpu per packages = 0 on package_%d", i);
3001 ret = 1;
3002 goto out;
3003 }
3004 }
3005
3006 /* Get QEMU PID*/
3007 r->pid = getpid();
3008
3009 /* Compute the socket path if necessary */
3010 if (s->msr_energy.socket_path == NULL) {
3011 s->msr_energy.socket_path = vmsr_compute_default_paths();
3012 }
3013
3014 /* Open socket with vmsr helper */
3015 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3016
3017 if (s->msr_energy.sioc == NULL) {
3018 error_report("vmsr socket opening failed");
3019 ret = 1;
3020 goto out;
3021 }
3022
3023 /* Those MSR values should not change */
3024 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3025 s->msr_energy.sioc);
3026 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3027 s->msr_energy.sioc);
3028 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3029 s->msr_energy.sioc);
3030 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3031 error_report("can't read any virtual msr");
3032 ret = 1;
3033 goto out;
3034 }
3035
3036 qemu_thread_create(&r->msr_thr, "kvm-msr",
3037 kvm_msr_energy_thread,
3038 s, QEMU_THREAD_JOINABLE);
3039 out:
3040 return ret;
3041 }
3042
kvm_arch_get_default_type(MachineState * ms)3043 int kvm_arch_get_default_type(MachineState *ms)
3044 {
3045 return 0;
3046 }
3047
kvm_vm_enable_exception_payload(KVMState * s)3048 static int kvm_vm_enable_exception_payload(KVMState *s)
3049 {
3050 int ret = 0;
3051 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3052 if (has_exception_payload) {
3053 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3054 if (ret < 0) {
3055 error_report("kvm: Failed to enable exception payload cap: %s",
3056 strerror(-ret));
3057 }
3058 }
3059
3060 return ret;
3061 }
3062
kvm_vm_enable_triple_fault_event(KVMState * s)3063 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3064 {
3065 int ret = 0;
3066 has_triple_fault_event = \
3067 kvm_check_extension(s,
3068 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3069 if (has_triple_fault_event) {
3070 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3071 if (ret < 0) {
3072 error_report("kvm: Failed to enable triple fault event cap: %s",
3073 strerror(-ret));
3074 }
3075 }
3076 return ret;
3077 }
3078
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3079 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3080 {
3081 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3082 }
3083
kvm_vm_set_nr_mmu_pages(KVMState * s)3084 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3085 {
3086 uint64_t shadow_mem;
3087 int ret = 0;
3088 shadow_mem = object_property_get_int(OBJECT(s),
3089 "kvm-shadow-mem",
3090 &error_abort);
3091 if (shadow_mem != -1) {
3092 shadow_mem /= 4096;
3093 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3094 }
3095 return ret;
3096 }
3097
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3098 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3099 {
3100 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3101 }
3102
kvm_vm_enable_disable_exits(KVMState * s)3103 static int kvm_vm_enable_disable_exits(KVMState *s)
3104 {
3105 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3106 /* Work around for kernel header with a typo. TODO: fix header and drop. */
3107 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
3108 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
3109 #endif
3110 if (disable_exits) {
3111 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3112 KVM_X86_DISABLE_EXITS_HLT |
3113 KVM_X86_DISABLE_EXITS_PAUSE |
3114 KVM_X86_DISABLE_EXITS_CSTATE);
3115 }
3116
3117 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3118 disable_exits);
3119 }
3120
kvm_vm_enable_bus_lock_exit(KVMState * s)3121 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3122 {
3123 int ret = 0;
3124 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3125 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3126 error_report("kvm: bus lock detection unsupported");
3127 return -ENOTSUP;
3128 }
3129 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3130 KVM_BUS_LOCK_DETECTION_EXIT);
3131 if (ret < 0) {
3132 error_report("kvm: Failed to enable bus lock detection cap: %s",
3133 strerror(-ret));
3134 }
3135
3136 return ret;
3137 }
3138
kvm_vm_enable_notify_vmexit(KVMState * s)3139 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3140 {
3141 int ret = 0;
3142 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3143 uint64_t notify_window_flags =
3144 ((uint64_t)s->notify_window << 32) |
3145 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3146 KVM_X86_NOTIFY_VMEXIT_USER;
3147 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3148 notify_window_flags);
3149 if (ret < 0) {
3150 error_report("kvm: Failed to enable notify vmexit cap: %s",
3151 strerror(-ret));
3152 }
3153 }
3154 return ret;
3155 }
3156
kvm_vm_enable_userspace_msr(KVMState * s)3157 static int kvm_vm_enable_userspace_msr(KVMState *s)
3158 {
3159 int ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3160 KVM_MSR_EXIT_REASON_FILTER);
3161 if (ret < 0) {
3162 error_report("Could not enable user space MSRs: %s",
3163 strerror(-ret));
3164 exit(1);
3165 }
3166
3167 if (!kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3168 kvm_rdmsr_core_thread_count, NULL)) {
3169 error_report("Could not install MSR_CORE_THREAD_COUNT handler!");
3170 exit(1);
3171 }
3172
3173 return 0;
3174 }
3175
kvm_vm_enable_energy_msrs(KVMState * s)3176 static void kvm_vm_enable_energy_msrs(KVMState *s)
3177 {
3178 bool r;
3179 if (s->msr_energy.enable == true) {
3180 r = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3181 kvm_rdmsr_rapl_power_unit, NULL);
3182 if (!r) {
3183 error_report("Could not install MSR_RAPL_POWER_UNIT \
3184 handler");
3185 exit(1);
3186 }
3187
3188 r = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3189 kvm_rdmsr_pkg_power_limit, NULL);
3190 if (!r) {
3191 error_report("Could not install MSR_PKG_POWER_LIMIT \
3192 handler");
3193 exit(1);
3194 }
3195
3196 r = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3197 kvm_rdmsr_pkg_power_info, NULL);
3198 if (!r) {
3199 error_report("Could not install MSR_PKG_POWER_INFO \
3200 handler");
3201 exit(1);
3202 }
3203 r = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3204 kvm_rdmsr_pkg_energy_status, NULL);
3205 if (!r) {
3206 error_report("Could not install MSR_PKG_ENERGY_STATUS \
3207 handler");
3208 exit(1);
3209 }
3210 }
3211 return;
3212 }
3213
kvm_arch_init(MachineState * ms,KVMState * s)3214 int kvm_arch_init(MachineState *ms, KVMState *s)
3215 {
3216 int ret;
3217 struct utsname utsname;
3218 Error *local_err = NULL;
3219
3220 /*
3221 * Initialize SEV context, if required
3222 *
3223 * If no memory encryption is requested (ms->cgs == NULL) this is
3224 * a no-op.
3225 *
3226 * It's also a no-op if a non-SEV confidential guest support
3227 * mechanism is selected. SEV is the only mechanism available to
3228 * select on x86 at present, so this doesn't arise, but if new
3229 * mechanisms are supported in future (e.g. TDX), they'll need
3230 * their own initialization either here or elsewhere.
3231 */
3232 if (ms->cgs) {
3233 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3234 if (ret < 0) {
3235 error_report_err(local_err);
3236 return ret;
3237 }
3238 }
3239
3240 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3241 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3242
3243 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3244
3245 ret = kvm_vm_enable_exception_payload(s);
3246 if (ret < 0) {
3247 return ret;
3248 }
3249
3250 ret = kvm_vm_enable_triple_fault_event(s);
3251 if (ret < 0) {
3252 return ret;
3253 }
3254
3255 if (s->xen_version) {
3256 #ifdef CONFIG_XEN_EMU
3257 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3258 error_report("kvm: Xen support only available in PC machine");
3259 return -ENOTSUP;
3260 }
3261 /* hyperv_enabled() doesn't work yet. */
3262 uint32_t msr = XEN_HYPERCALL_MSR;
3263 ret = kvm_xen_init(s, msr);
3264 if (ret < 0) {
3265 return ret;
3266 }
3267 #else
3268 error_report("kvm: Xen support not enabled in qemu");
3269 return -ENOTSUP;
3270 #endif
3271 }
3272
3273 ret = kvm_get_supported_msrs(s);
3274 if (ret < 0) {
3275 return ret;
3276 }
3277
3278 kvm_get_supported_feature_msrs(s);
3279
3280 uname(&utsname);
3281 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3282
3283 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3284 if (ret < 0) {
3285 return ret;
3286 }
3287
3288 /* Set TSS base one page after EPT identity map. */
3289 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3290 if (ret < 0) {
3291 return ret;
3292 }
3293
3294 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3295 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3296
3297 ret = kvm_vm_set_nr_mmu_pages(s);
3298 if (ret < 0) {
3299 return ret;
3300 }
3301
3302 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3303 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3304 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3305 smram_machine_done.notify = register_smram_listener;
3306 qemu_add_machine_init_done_notifier(&smram_machine_done);
3307 }
3308
3309 if (enable_cpu_pm) {
3310 ret = kvm_vm_enable_disable_exits(s);
3311 if (ret < 0) {
3312 error_report("kvm: guest stopping CPU not supported: %s",
3313 strerror(-ret));
3314 }
3315 }
3316
3317 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3318 X86MachineState *x86ms = X86_MACHINE(ms);
3319
3320 if (x86ms->bus_lock_ratelimit > 0) {
3321 ret = kvm_vm_enable_bus_lock_exit(s);
3322 if (ret < 0) {
3323 return ret;
3324 }
3325 ratelimit_init(&bus_lock_ratelimit_ctrl);
3326 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3327 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3328 }
3329 }
3330
3331 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3332 ret = kvm_vm_enable_notify_vmexit(s);
3333 if (ret < 0) {
3334 return ret;
3335 }
3336 }
3337
3338 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3339 ret = kvm_vm_enable_userspace_msr(s);
3340 if (ret < 0) {
3341 return ret;
3342 }
3343
3344 if (s->msr_energy.enable == true) {
3345 kvm_vm_enable_energy_msrs(s);
3346 if (kvm_msr_energy_thread_init(s, ms)) {
3347 error_report("kvm : error RAPL feature requirement not met");
3348 exit(1);
3349 }
3350 }
3351 }
3352
3353 return 0;
3354 }
3355
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3356 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3357 {
3358 lhs->selector = rhs->selector;
3359 lhs->base = rhs->base;
3360 lhs->limit = rhs->limit;
3361 lhs->type = 3;
3362 lhs->present = 1;
3363 lhs->dpl = 3;
3364 lhs->db = 0;
3365 lhs->s = 1;
3366 lhs->l = 0;
3367 lhs->g = 0;
3368 lhs->avl = 0;
3369 lhs->unusable = 0;
3370 }
3371
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3372 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3373 {
3374 unsigned flags = rhs->flags;
3375 lhs->selector = rhs->selector;
3376 lhs->base = rhs->base;
3377 lhs->limit = rhs->limit;
3378 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3379 lhs->present = (flags & DESC_P_MASK) != 0;
3380 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3381 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3382 lhs->s = (flags & DESC_S_MASK) != 0;
3383 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3384 lhs->g = (flags & DESC_G_MASK) != 0;
3385 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3386 lhs->unusable = !lhs->present;
3387 lhs->padding = 0;
3388 }
3389
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3390 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3391 {
3392 lhs->selector = rhs->selector;
3393 lhs->base = rhs->base;
3394 lhs->limit = rhs->limit;
3395 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3396 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3397 (rhs->dpl << DESC_DPL_SHIFT) |
3398 (rhs->db << DESC_B_SHIFT) |
3399 (rhs->s * DESC_S_MASK) |
3400 (rhs->l << DESC_L_SHIFT) |
3401 (rhs->g * DESC_G_MASK) |
3402 (rhs->avl * DESC_AVL_MASK);
3403 }
3404
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3405 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3406 {
3407 if (set) {
3408 *kvm_reg = *qemu_reg;
3409 } else {
3410 *qemu_reg = *kvm_reg;
3411 }
3412 }
3413
kvm_getput_regs(X86CPU * cpu,int set)3414 static int kvm_getput_regs(X86CPU *cpu, int set)
3415 {
3416 CPUX86State *env = &cpu->env;
3417 struct kvm_regs regs;
3418 int ret = 0;
3419
3420 if (!set) {
3421 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3422 if (ret < 0) {
3423 return ret;
3424 }
3425 }
3426
3427 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3428 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3429 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3430 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3431 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3432 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3433 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3434 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3435 #ifdef TARGET_X86_64
3436 kvm_getput_reg(®s.r8, &env->regs[8], set);
3437 kvm_getput_reg(®s.r9, &env->regs[9], set);
3438 kvm_getput_reg(®s.r10, &env->regs[10], set);
3439 kvm_getput_reg(®s.r11, &env->regs[11], set);
3440 kvm_getput_reg(®s.r12, &env->regs[12], set);
3441 kvm_getput_reg(®s.r13, &env->regs[13], set);
3442 kvm_getput_reg(®s.r14, &env->regs[14], set);
3443 kvm_getput_reg(®s.r15, &env->regs[15], set);
3444 #endif
3445
3446 kvm_getput_reg(®s.rflags, &env->eflags, set);
3447 kvm_getput_reg(®s.rip, &env->eip, set);
3448
3449 if (set) {
3450 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3451 }
3452
3453 return ret;
3454 }
3455
kvm_put_xsave(X86CPU * cpu)3456 static int kvm_put_xsave(X86CPU *cpu)
3457 {
3458 CPUX86State *env = &cpu->env;
3459 void *xsave = env->xsave_buf;
3460
3461 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3462
3463 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3464 }
3465
kvm_put_xcrs(X86CPU * cpu)3466 static int kvm_put_xcrs(X86CPU *cpu)
3467 {
3468 CPUX86State *env = &cpu->env;
3469 struct kvm_xcrs xcrs = {};
3470
3471 if (!has_xcrs) {
3472 return 0;
3473 }
3474
3475 xcrs.nr_xcrs = 1;
3476 xcrs.flags = 0;
3477 xcrs.xcrs[0].xcr = 0;
3478 xcrs.xcrs[0].value = env->xcr0;
3479 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3480 }
3481
kvm_put_sregs(X86CPU * cpu)3482 static int kvm_put_sregs(X86CPU *cpu)
3483 {
3484 CPUX86State *env = &cpu->env;
3485 struct kvm_sregs sregs;
3486
3487 /*
3488 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3489 * always followed by KVM_SET_VCPU_EVENTS.
3490 */
3491 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3492
3493 if ((env->eflags & VM_MASK)) {
3494 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3495 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3496 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3497 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3498 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3499 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3500 } else {
3501 set_seg(&sregs.cs, &env->segs[R_CS]);
3502 set_seg(&sregs.ds, &env->segs[R_DS]);
3503 set_seg(&sregs.es, &env->segs[R_ES]);
3504 set_seg(&sregs.fs, &env->segs[R_FS]);
3505 set_seg(&sregs.gs, &env->segs[R_GS]);
3506 set_seg(&sregs.ss, &env->segs[R_SS]);
3507 }
3508
3509 set_seg(&sregs.tr, &env->tr);
3510 set_seg(&sregs.ldt, &env->ldt);
3511
3512 sregs.idt.limit = env->idt.limit;
3513 sregs.idt.base = env->idt.base;
3514 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3515 sregs.gdt.limit = env->gdt.limit;
3516 sregs.gdt.base = env->gdt.base;
3517 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3518
3519 sregs.cr0 = env->cr[0];
3520 sregs.cr2 = env->cr[2];
3521 sregs.cr3 = env->cr[3];
3522 sregs.cr4 = env->cr[4];
3523
3524 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3525 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3526
3527 sregs.efer = env->efer;
3528
3529 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3530 }
3531
kvm_put_sregs2(X86CPU * cpu)3532 static int kvm_put_sregs2(X86CPU *cpu)
3533 {
3534 CPUX86State *env = &cpu->env;
3535 struct kvm_sregs2 sregs;
3536 int i;
3537
3538 sregs.flags = 0;
3539
3540 if ((env->eflags & VM_MASK)) {
3541 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3542 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3543 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3544 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3545 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3546 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3547 } else {
3548 set_seg(&sregs.cs, &env->segs[R_CS]);
3549 set_seg(&sregs.ds, &env->segs[R_DS]);
3550 set_seg(&sregs.es, &env->segs[R_ES]);
3551 set_seg(&sregs.fs, &env->segs[R_FS]);
3552 set_seg(&sregs.gs, &env->segs[R_GS]);
3553 set_seg(&sregs.ss, &env->segs[R_SS]);
3554 }
3555
3556 set_seg(&sregs.tr, &env->tr);
3557 set_seg(&sregs.ldt, &env->ldt);
3558
3559 sregs.idt.limit = env->idt.limit;
3560 sregs.idt.base = env->idt.base;
3561 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3562 sregs.gdt.limit = env->gdt.limit;
3563 sregs.gdt.base = env->gdt.base;
3564 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3565
3566 sregs.cr0 = env->cr[0];
3567 sregs.cr2 = env->cr[2];
3568 sregs.cr3 = env->cr[3];
3569 sregs.cr4 = env->cr[4];
3570
3571 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3572 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3573
3574 sregs.efer = env->efer;
3575
3576 if (env->pdptrs_valid) {
3577 for (i = 0; i < 4; i++) {
3578 sregs.pdptrs[i] = env->pdptrs[i];
3579 }
3580 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3581 }
3582
3583 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3584 }
3585
3586
kvm_msr_buf_reset(X86CPU * cpu)3587 static void kvm_msr_buf_reset(X86CPU *cpu)
3588 {
3589 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3590 }
3591
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3592 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3593 {
3594 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3595 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3596 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3597
3598 assert((void *)(entry + 1) <= limit);
3599
3600 entry->index = index;
3601 entry->reserved = 0;
3602 entry->data = value;
3603 msrs->nmsrs++;
3604 }
3605
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3606 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3607 {
3608 kvm_msr_buf_reset(cpu);
3609 kvm_msr_entry_add(cpu, index, value);
3610
3611 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3612 }
3613
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3614 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3615 {
3616 int ret;
3617 struct {
3618 struct kvm_msrs info;
3619 struct kvm_msr_entry entries[1];
3620 } msr_data = {
3621 .info.nmsrs = 1,
3622 .entries[0].index = index,
3623 };
3624
3625 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3626 if (ret < 0) {
3627 return ret;
3628 }
3629 assert(ret == 1);
3630 *value = msr_data.entries[0].data;
3631 return ret;
3632 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3633 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3634 {
3635 int ret;
3636
3637 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3638 assert(ret == 1);
3639 }
3640
kvm_put_tscdeadline_msr(X86CPU * cpu)3641 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3642 {
3643 CPUX86State *env = &cpu->env;
3644 int ret;
3645
3646 if (!has_msr_tsc_deadline) {
3647 return 0;
3648 }
3649
3650 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3651 if (ret < 0) {
3652 return ret;
3653 }
3654
3655 assert(ret == 1);
3656 return 0;
3657 }
3658
3659 /*
3660 * Provide a separate write service for the feature control MSR in order to
3661 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3662 * before writing any other state because forcibly leaving nested mode
3663 * invalidates the VCPU state.
3664 */
kvm_put_msr_feature_control(X86CPU * cpu)3665 static int kvm_put_msr_feature_control(X86CPU *cpu)
3666 {
3667 int ret;
3668
3669 if (!has_msr_feature_control) {
3670 return 0;
3671 }
3672
3673 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3674 cpu->env.msr_ia32_feature_control);
3675 if (ret < 0) {
3676 return ret;
3677 }
3678
3679 assert(ret == 1);
3680 return 0;
3681 }
3682
make_vmx_msr_value(uint32_t index,uint32_t features)3683 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3684 {
3685 uint32_t default1, can_be_one, can_be_zero;
3686 uint32_t must_be_one;
3687
3688 switch (index) {
3689 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3690 default1 = 0x00000016;
3691 break;
3692 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3693 default1 = 0x0401e172;
3694 break;
3695 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3696 default1 = 0x000011ff;
3697 break;
3698 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3699 default1 = 0x00036dff;
3700 break;
3701 case MSR_IA32_VMX_PROCBASED_CTLS2:
3702 default1 = 0;
3703 break;
3704 default:
3705 abort();
3706 }
3707
3708 /* If a feature bit is set, the control can be either set or clear.
3709 * Otherwise the value is limited to either 0 or 1 by default1.
3710 */
3711 can_be_one = features | default1;
3712 can_be_zero = features | ~default1;
3713 must_be_one = ~can_be_zero;
3714
3715 /*
3716 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3717 * Bit 32:63 -> 1 if the control bit can be one.
3718 */
3719 return must_be_one | (((uint64_t)can_be_one) << 32);
3720 }
3721
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3722 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3723 {
3724 uint64_t kvm_vmx_basic =
3725 kvm_arch_get_supported_msr_feature(kvm_state,
3726 MSR_IA32_VMX_BASIC);
3727
3728 if (!kvm_vmx_basic) {
3729 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3730 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3731 */
3732 return;
3733 }
3734
3735 uint64_t kvm_vmx_misc =
3736 kvm_arch_get_supported_msr_feature(kvm_state,
3737 MSR_IA32_VMX_MISC);
3738 uint64_t kvm_vmx_ept_vpid =
3739 kvm_arch_get_supported_msr_feature(kvm_state,
3740 MSR_IA32_VMX_EPT_VPID_CAP);
3741
3742 /*
3743 * If the guest is 64-bit, a value of 1 is allowed for the host address
3744 * space size vmexit control.
3745 */
3746 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3747 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3748
3749 /*
3750 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3751 * not change them for backwards compatibility.
3752 */
3753 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3754 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3755 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3756 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3757
3758 /*
3759 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3760 * change in the future but are always zero for now, clear them to be
3761 * future proof. Bits 32-63 in theory could change, though KVM does
3762 * not support dual-monitor treatment and probably never will; mask
3763 * them out as well.
3764 */
3765 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3766 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3767 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3768
3769 /*
3770 * EPT memory types should not change either, so we do not bother
3771 * adding features for them.
3772 */
3773 uint64_t fixed_vmx_ept_mask =
3774 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3775 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3776 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3777
3778 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3779 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3780 f[FEAT_VMX_PROCBASED_CTLS]));
3781 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3782 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3783 f[FEAT_VMX_PINBASED_CTLS]));
3784 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3785 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3786 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3787 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3788 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3789 f[FEAT_VMX_ENTRY_CTLS]));
3790 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3791 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3792 f[FEAT_VMX_SECONDARY_CTLS]));
3793 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3794 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3795 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3796 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3797 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3798 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3799 if (has_msr_vmx_vmfunc) {
3800 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3801 }
3802
3803 /*
3804 * Just to be safe, write these with constant values. The CRn_FIXED1
3805 * MSRs are generated by KVM based on the vCPU's CPUID.
3806 */
3807 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3808 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3809 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3810 CR4_VMXE_MASK);
3811
3812 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3813 /* FRED injected-event data (0x2052). */
3814 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3815 } else if (f[FEAT_VMX_EXIT_CTLS] &
3816 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3817 /* Secondary VM-exit controls (0x2044). */
3818 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3819 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3820 /* TSC multiplier (0x2032). */
3821 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3822 } else {
3823 /* Preemption timer (0x482E). */
3824 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3825 }
3826 }
3827
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3828 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3829 {
3830 uint64_t kvm_perf_cap =
3831 kvm_arch_get_supported_msr_feature(kvm_state,
3832 MSR_IA32_PERF_CAPABILITIES);
3833
3834 if (kvm_perf_cap) {
3835 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3836 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3837 }
3838 }
3839
kvm_buf_set_msrs(X86CPU * cpu)3840 static int kvm_buf_set_msrs(X86CPU *cpu)
3841 {
3842 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3843 if (ret < 0) {
3844 return ret;
3845 }
3846
3847 if (ret < cpu->kvm_msr_buf->nmsrs) {
3848 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3849 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3850 (uint32_t)e->index, (uint64_t)e->data);
3851 }
3852
3853 assert(ret == cpu->kvm_msr_buf->nmsrs);
3854 return 0;
3855 }
3856
kvm_init_msrs(X86CPU * cpu)3857 static void kvm_init_msrs(X86CPU *cpu)
3858 {
3859 CPUX86State *env = &cpu->env;
3860
3861 kvm_msr_buf_reset(cpu);
3862 if (has_msr_arch_capabs) {
3863 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3864 env->features[FEAT_ARCH_CAPABILITIES]);
3865 }
3866
3867 if (has_msr_core_capabs) {
3868 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3869 env->features[FEAT_CORE_CAPABILITY]);
3870 }
3871
3872 if (has_msr_perf_capabs && cpu->enable_pmu) {
3873 kvm_msr_entry_add_perf(cpu, env->features);
3874 }
3875
3876 if (has_msr_ucode_rev) {
3877 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3878 }
3879
3880 /*
3881 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3882 * all kernels with MSR features should have them.
3883 */
3884 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3885 kvm_msr_entry_add_vmx(cpu, env->features);
3886 }
3887
3888 assert(kvm_buf_set_msrs(cpu) == 0);
3889 }
3890
kvm_put_msrs(X86CPU * cpu,int level)3891 static int kvm_put_msrs(X86CPU *cpu, int level)
3892 {
3893 CPUX86State *env = &cpu->env;
3894 int i;
3895
3896 kvm_msr_buf_reset(cpu);
3897
3898 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3899 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3900 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3901 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3902 if (has_msr_star) {
3903 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3904 }
3905 if (has_msr_hsave_pa) {
3906 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3907 }
3908 if (has_msr_tsc_aux) {
3909 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3910 }
3911 if (has_msr_tsc_adjust) {
3912 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3913 }
3914 if (has_msr_misc_enable) {
3915 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3916 env->msr_ia32_misc_enable);
3917 }
3918 if (has_msr_smbase) {
3919 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3920 }
3921 if (has_msr_smi_count) {
3922 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3923 }
3924 if (has_msr_pkrs) {
3925 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3926 }
3927 if (has_msr_bndcfgs) {
3928 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3929 }
3930 if (has_msr_xss) {
3931 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3932 }
3933 if (has_msr_umwait) {
3934 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3935 }
3936 if (has_msr_spec_ctrl) {
3937 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3938 }
3939 if (has_tsc_scale_msr) {
3940 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3941 }
3942
3943 if (has_msr_tsx_ctrl) {
3944 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3945 }
3946 if (has_msr_virt_ssbd) {
3947 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3948 }
3949 if (has_msr_hwcr) {
3950 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3951 }
3952
3953 #ifdef TARGET_X86_64
3954 if (lm_capable_kernel) {
3955 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3956 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3957 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3958 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3959 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3960 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3961 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3962 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
3963 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
3964 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
3965 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
3966 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
3967 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
3968 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
3969 }
3970 }
3971 #endif
3972
3973 /*
3974 * The following MSRs have side effects on the guest or are too heavy
3975 * for normal writeback. Limit them to reset or full state updates.
3976 */
3977 if (level >= KVM_PUT_RESET_STATE) {
3978 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3979 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3980 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
3981 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3982 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3983 }
3984 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3985 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
3986 }
3987 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3988 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
3989 }
3990 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3991 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
3992 }
3993
3994 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3995 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3996 }
3997
3998 if (has_architectural_pmu_version > 0) {
3999 if (has_architectural_pmu_version > 1) {
4000 /* Stop the counter. */
4001 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4002 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4003 }
4004
4005 /* Set the counter values. */
4006 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4007 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4008 env->msr_fixed_counters[i]);
4009 }
4010 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4011 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4012 env->msr_gp_counters[i]);
4013 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4014 env->msr_gp_evtsel[i]);
4015 }
4016 if (has_architectural_pmu_version > 1) {
4017 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4018 env->msr_global_status);
4019 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4020 env->msr_global_ovf_ctrl);
4021
4022 /* Now start the PMU. */
4023 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4024 env->msr_fixed_ctr_ctrl);
4025 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4026 env->msr_global_ctrl);
4027 }
4028 }
4029 /*
4030 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4031 * only sync them to KVM on the first cpu
4032 */
4033 if (current_cpu == first_cpu) {
4034 if (has_msr_hv_hypercall) {
4035 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4036 env->msr_hv_guest_os_id);
4037 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4038 env->msr_hv_hypercall);
4039 }
4040 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4041 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4042 env->msr_hv_tsc);
4043 }
4044 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4045 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4046 env->msr_hv_reenlightenment_control);
4047 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4048 env->msr_hv_tsc_emulation_control);
4049 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4050 env->msr_hv_tsc_emulation_status);
4051 }
4052 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4053 has_msr_hv_syndbg_options) {
4054 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4055 hyperv_syndbg_query_options());
4056 }
4057 }
4058 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4059 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4060 env->msr_hv_vapic);
4061 }
4062 if (has_msr_hv_crash) {
4063 int j;
4064
4065 for (j = 0; j < HV_CRASH_PARAMS; j++)
4066 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4067 env->msr_hv_crash_params[j]);
4068
4069 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4070 }
4071 if (has_msr_hv_runtime) {
4072 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4073 }
4074 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4075 && hv_vpindex_settable) {
4076 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4077 hyperv_vp_index(CPU(cpu)));
4078 }
4079 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4080 int j;
4081
4082 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4083
4084 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4085 env->msr_hv_synic_control);
4086 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4087 env->msr_hv_synic_evt_page);
4088 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4089 env->msr_hv_synic_msg_page);
4090
4091 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4092 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4093 env->msr_hv_synic_sint[j]);
4094 }
4095 }
4096 if (has_msr_hv_stimer) {
4097 int j;
4098
4099 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4100 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4101 env->msr_hv_stimer_config[j]);
4102 }
4103
4104 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4105 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4106 env->msr_hv_stimer_count[j]);
4107 }
4108 }
4109 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4110 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4111
4112 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4113 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4114 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4115 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4116 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4117 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4124 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4125 /* The CPU GPs if we write to a bit above the physical limit of
4126 * the host CPU (and KVM emulates that)
4127 */
4128 uint64_t mask = env->mtrr_var[i].mask;
4129 mask &= phys_mask;
4130
4131 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4132 env->mtrr_var[i].base);
4133 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4134 }
4135 }
4136 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4137 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4138 0x14, 1, R_EAX) & 0x7;
4139
4140 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4141 env->msr_rtit_ctrl);
4142 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4143 env->msr_rtit_status);
4144 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4145 env->msr_rtit_output_base);
4146 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4147 env->msr_rtit_output_mask);
4148 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4149 env->msr_rtit_cr3_match);
4150 for (i = 0; i < addr_num; i++) {
4151 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4152 env->msr_rtit_addrs[i]);
4153 }
4154 }
4155
4156 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4157 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4158 env->msr_ia32_sgxlepubkeyhash[0]);
4159 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4160 env->msr_ia32_sgxlepubkeyhash[1]);
4161 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4162 env->msr_ia32_sgxlepubkeyhash[2]);
4163 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4164 env->msr_ia32_sgxlepubkeyhash[3]);
4165 }
4166
4167 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4168 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4169 env->msr_xfd);
4170 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4171 env->msr_xfd_err);
4172 }
4173
4174 if (kvm_enabled() && cpu->enable_pmu &&
4175 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4176 uint64_t depth;
4177 int ret;
4178
4179 /*
4180 * Only migrate Arch LBR states when the host Arch LBR depth
4181 * equals that of source guest's, this is to avoid mismatch
4182 * of guest/host config for the msr hence avoid unexpected
4183 * misbehavior.
4184 */
4185 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4186
4187 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4188 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4189 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4190
4191 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4192 if (!env->lbr_records[i].from) {
4193 continue;
4194 }
4195 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4196 env->lbr_records[i].from);
4197 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4198 env->lbr_records[i].to);
4199 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4200 env->lbr_records[i].info);
4201 }
4202 }
4203 }
4204
4205 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4206 * kvm_put_msr_feature_control. */
4207 }
4208
4209 if (env->mcg_cap) {
4210 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4211 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4212 if (has_msr_mcg_ext_ctl) {
4213 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4214 }
4215 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4216 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4217 }
4218 }
4219
4220 return kvm_buf_set_msrs(cpu);
4221 }
4222
4223
kvm_get_xsave(X86CPU * cpu)4224 static int kvm_get_xsave(X86CPU *cpu)
4225 {
4226 CPUX86State *env = &cpu->env;
4227 void *xsave = env->xsave_buf;
4228 unsigned long type;
4229 int ret;
4230
4231 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4232 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4233 if (ret < 0) {
4234 return ret;
4235 }
4236 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4237
4238 return 0;
4239 }
4240
kvm_get_xcrs(X86CPU * cpu)4241 static int kvm_get_xcrs(X86CPU *cpu)
4242 {
4243 CPUX86State *env = &cpu->env;
4244 int i, ret;
4245 struct kvm_xcrs xcrs;
4246
4247 if (!has_xcrs) {
4248 return 0;
4249 }
4250
4251 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4252 if (ret < 0) {
4253 return ret;
4254 }
4255
4256 for (i = 0; i < xcrs.nr_xcrs; i++) {
4257 /* Only support xcr0 now */
4258 if (xcrs.xcrs[i].xcr == 0) {
4259 env->xcr0 = xcrs.xcrs[i].value;
4260 break;
4261 }
4262 }
4263 return 0;
4264 }
4265
kvm_get_sregs(X86CPU * cpu)4266 static int kvm_get_sregs(X86CPU *cpu)
4267 {
4268 CPUX86State *env = &cpu->env;
4269 struct kvm_sregs sregs;
4270 int ret;
4271
4272 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4273 if (ret < 0) {
4274 return ret;
4275 }
4276
4277 /*
4278 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4279 * always preceded by KVM_GET_VCPU_EVENTS.
4280 */
4281
4282 get_seg(&env->segs[R_CS], &sregs.cs);
4283 get_seg(&env->segs[R_DS], &sregs.ds);
4284 get_seg(&env->segs[R_ES], &sregs.es);
4285 get_seg(&env->segs[R_FS], &sregs.fs);
4286 get_seg(&env->segs[R_GS], &sregs.gs);
4287 get_seg(&env->segs[R_SS], &sregs.ss);
4288
4289 get_seg(&env->tr, &sregs.tr);
4290 get_seg(&env->ldt, &sregs.ldt);
4291
4292 env->idt.limit = sregs.idt.limit;
4293 env->idt.base = sregs.idt.base;
4294 env->gdt.limit = sregs.gdt.limit;
4295 env->gdt.base = sregs.gdt.base;
4296
4297 env->cr[0] = sregs.cr0;
4298 env->cr[2] = sregs.cr2;
4299 env->cr[3] = sregs.cr3;
4300 env->cr[4] = sregs.cr4;
4301
4302 env->efer = sregs.efer;
4303 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4304 env->cr[0] & CR0_PG_MASK) {
4305 env->efer |= MSR_EFER_LMA;
4306 }
4307
4308 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4309 x86_update_hflags(env);
4310
4311 return 0;
4312 }
4313
kvm_get_sregs2(X86CPU * cpu)4314 static int kvm_get_sregs2(X86CPU *cpu)
4315 {
4316 CPUX86State *env = &cpu->env;
4317 struct kvm_sregs2 sregs;
4318 int i, ret;
4319
4320 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4321 if (ret < 0) {
4322 return ret;
4323 }
4324
4325 get_seg(&env->segs[R_CS], &sregs.cs);
4326 get_seg(&env->segs[R_DS], &sregs.ds);
4327 get_seg(&env->segs[R_ES], &sregs.es);
4328 get_seg(&env->segs[R_FS], &sregs.fs);
4329 get_seg(&env->segs[R_GS], &sregs.gs);
4330 get_seg(&env->segs[R_SS], &sregs.ss);
4331
4332 get_seg(&env->tr, &sregs.tr);
4333 get_seg(&env->ldt, &sregs.ldt);
4334
4335 env->idt.limit = sregs.idt.limit;
4336 env->idt.base = sregs.idt.base;
4337 env->gdt.limit = sregs.gdt.limit;
4338 env->gdt.base = sregs.gdt.base;
4339
4340 env->cr[0] = sregs.cr0;
4341 env->cr[2] = sregs.cr2;
4342 env->cr[3] = sregs.cr3;
4343 env->cr[4] = sregs.cr4;
4344
4345 env->efer = sregs.efer;
4346 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4347 env->cr[0] & CR0_PG_MASK) {
4348 env->efer |= MSR_EFER_LMA;
4349 }
4350
4351 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4352
4353 if (env->pdptrs_valid) {
4354 for (i = 0; i < 4; i++) {
4355 env->pdptrs[i] = sregs.pdptrs[i];
4356 }
4357 }
4358
4359 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4360 x86_update_hflags(env);
4361
4362 return 0;
4363 }
4364
kvm_get_msrs(X86CPU * cpu)4365 static int kvm_get_msrs(X86CPU *cpu)
4366 {
4367 CPUX86State *env = &cpu->env;
4368 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4369 int ret, i;
4370 uint64_t mtrr_top_bits;
4371
4372 kvm_msr_buf_reset(cpu);
4373
4374 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4375 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4376 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4377 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4378 if (has_msr_star) {
4379 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4380 }
4381 if (has_msr_hsave_pa) {
4382 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4383 }
4384 if (has_msr_tsc_aux) {
4385 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4386 }
4387 if (has_msr_tsc_adjust) {
4388 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4389 }
4390 if (has_msr_tsc_deadline) {
4391 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4392 }
4393 if (has_msr_misc_enable) {
4394 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4395 }
4396 if (has_msr_smbase) {
4397 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4398 }
4399 if (has_msr_smi_count) {
4400 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4401 }
4402 if (has_msr_feature_control) {
4403 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4404 }
4405 if (has_msr_pkrs) {
4406 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4407 }
4408 if (has_msr_bndcfgs) {
4409 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4410 }
4411 if (has_msr_xss) {
4412 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4413 }
4414 if (has_msr_umwait) {
4415 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4416 }
4417 if (has_msr_spec_ctrl) {
4418 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4419 }
4420 if (has_tsc_scale_msr) {
4421 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4422 }
4423
4424 if (has_msr_tsx_ctrl) {
4425 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4426 }
4427 if (has_msr_virt_ssbd) {
4428 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4429 }
4430 if (!env->tsc_valid) {
4431 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4432 env->tsc_valid = !runstate_is_running();
4433 }
4434 if (has_msr_hwcr) {
4435 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4436 }
4437
4438 #ifdef TARGET_X86_64
4439 if (lm_capable_kernel) {
4440 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4441 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4442 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4443 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4444 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4445 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4446 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4447 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4448 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4449 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4450 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4451 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4452 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4453 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4454 }
4455 }
4456 #endif
4457 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4458 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4459 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
4460 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4461 }
4462 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
4463 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4464 }
4465 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
4466 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4467 }
4468 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
4469 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4470 }
4471 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
4472 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4473 }
4474 if (has_architectural_pmu_version > 0) {
4475 if (has_architectural_pmu_version > 1) {
4476 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4477 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4478 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4479 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4480 }
4481 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4482 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4483 }
4484 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4485 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4486 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4487 }
4488 }
4489
4490 if (env->mcg_cap) {
4491 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4492 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4493 if (has_msr_mcg_ext_ctl) {
4494 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4495 }
4496 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4497 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4498 }
4499 }
4500
4501 if (has_msr_hv_hypercall) {
4502 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4503 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4504 }
4505 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4506 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4507 }
4508 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4509 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4510 }
4511 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4512 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4513 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4514 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4515 }
4516 if (has_msr_hv_syndbg_options) {
4517 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4518 }
4519 if (has_msr_hv_crash) {
4520 int j;
4521
4522 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4523 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4524 }
4525 }
4526 if (has_msr_hv_runtime) {
4527 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4528 }
4529 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4530 uint32_t msr;
4531
4532 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4533 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4534 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4535 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4536 kvm_msr_entry_add(cpu, msr, 0);
4537 }
4538 }
4539 if (has_msr_hv_stimer) {
4540 uint32_t msr;
4541
4542 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4543 msr++) {
4544 kvm_msr_entry_add(cpu, msr, 0);
4545 }
4546 }
4547 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4548 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4549 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4550 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4551 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4552 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4553 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4554 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4555 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4556 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4557 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4558 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4559 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4560 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4561 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4562 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4563 }
4564 }
4565
4566 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4567 int addr_num =
4568 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4569
4570 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4571 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4572 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4573 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4574 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4575 for (i = 0; i < addr_num; i++) {
4576 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4577 }
4578 }
4579
4580 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4581 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4582 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4583 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4584 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4585 }
4586
4587 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4588 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4589 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4590 }
4591
4592 if (kvm_enabled() && cpu->enable_pmu &&
4593 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4594 uint64_t depth;
4595
4596 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4597 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4598 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4599 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4600
4601 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4602 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4603 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4604 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4605 }
4606 }
4607 }
4608
4609 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4610 if (ret < 0) {
4611 return ret;
4612 }
4613
4614 if (ret < cpu->kvm_msr_buf->nmsrs) {
4615 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4616 error_report("error: failed to get MSR 0x%" PRIx32,
4617 (uint32_t)e->index);
4618 }
4619
4620 assert(ret == cpu->kvm_msr_buf->nmsrs);
4621 /*
4622 * MTRR masks: Each mask consists of 5 parts
4623 * a 10..0: must be zero
4624 * b 11 : valid bit
4625 * c n-1.12: actual mask bits
4626 * d 51..n: reserved must be zero
4627 * e 63.52: reserved must be zero
4628 *
4629 * 'n' is the number of physical bits supported by the CPU and is
4630 * apparently always <= 52. We know our 'n' but don't know what
4631 * the destinations 'n' is; it might be smaller, in which case
4632 * it masks (c) on loading. It might be larger, in which case
4633 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4634 * we're migrating to.
4635 */
4636
4637 if (cpu->fill_mtrr_mask) {
4638 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4639 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4640 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4641 } else {
4642 mtrr_top_bits = 0;
4643 }
4644
4645 for (i = 0; i < ret; i++) {
4646 uint32_t index = msrs[i].index;
4647 switch (index) {
4648 case MSR_IA32_SYSENTER_CS:
4649 env->sysenter_cs = msrs[i].data;
4650 break;
4651 case MSR_IA32_SYSENTER_ESP:
4652 env->sysenter_esp = msrs[i].data;
4653 break;
4654 case MSR_IA32_SYSENTER_EIP:
4655 env->sysenter_eip = msrs[i].data;
4656 break;
4657 case MSR_PAT:
4658 env->pat = msrs[i].data;
4659 break;
4660 case MSR_STAR:
4661 env->star = msrs[i].data;
4662 break;
4663 #ifdef TARGET_X86_64
4664 case MSR_CSTAR:
4665 env->cstar = msrs[i].data;
4666 break;
4667 case MSR_KERNELGSBASE:
4668 env->kernelgsbase = msrs[i].data;
4669 break;
4670 case MSR_FMASK:
4671 env->fmask = msrs[i].data;
4672 break;
4673 case MSR_LSTAR:
4674 env->lstar = msrs[i].data;
4675 break;
4676 case MSR_IA32_FRED_RSP0:
4677 env->fred_rsp0 = msrs[i].data;
4678 break;
4679 case MSR_IA32_FRED_RSP1:
4680 env->fred_rsp1 = msrs[i].data;
4681 break;
4682 case MSR_IA32_FRED_RSP2:
4683 env->fred_rsp2 = msrs[i].data;
4684 break;
4685 case MSR_IA32_FRED_RSP3:
4686 env->fred_rsp3 = msrs[i].data;
4687 break;
4688 case MSR_IA32_FRED_STKLVLS:
4689 env->fred_stklvls = msrs[i].data;
4690 break;
4691 case MSR_IA32_FRED_SSP1:
4692 env->fred_ssp1 = msrs[i].data;
4693 break;
4694 case MSR_IA32_FRED_SSP2:
4695 env->fred_ssp2 = msrs[i].data;
4696 break;
4697 case MSR_IA32_FRED_SSP3:
4698 env->fred_ssp3 = msrs[i].data;
4699 break;
4700 case MSR_IA32_FRED_CONFIG:
4701 env->fred_config = msrs[i].data;
4702 break;
4703 #endif
4704 case MSR_IA32_TSC:
4705 env->tsc = msrs[i].data;
4706 break;
4707 case MSR_TSC_AUX:
4708 env->tsc_aux = msrs[i].data;
4709 break;
4710 case MSR_TSC_ADJUST:
4711 env->tsc_adjust = msrs[i].data;
4712 break;
4713 case MSR_IA32_TSCDEADLINE:
4714 env->tsc_deadline = msrs[i].data;
4715 break;
4716 case MSR_VM_HSAVE_PA:
4717 env->vm_hsave = msrs[i].data;
4718 break;
4719 case MSR_KVM_SYSTEM_TIME:
4720 env->system_time_msr = msrs[i].data;
4721 break;
4722 case MSR_KVM_WALL_CLOCK:
4723 env->wall_clock_msr = msrs[i].data;
4724 break;
4725 case MSR_MCG_STATUS:
4726 env->mcg_status = msrs[i].data;
4727 break;
4728 case MSR_MCG_CTL:
4729 env->mcg_ctl = msrs[i].data;
4730 break;
4731 case MSR_MCG_EXT_CTL:
4732 env->mcg_ext_ctl = msrs[i].data;
4733 break;
4734 case MSR_IA32_MISC_ENABLE:
4735 env->msr_ia32_misc_enable = msrs[i].data;
4736 break;
4737 case MSR_IA32_SMBASE:
4738 env->smbase = msrs[i].data;
4739 break;
4740 case MSR_SMI_COUNT:
4741 env->msr_smi_count = msrs[i].data;
4742 break;
4743 case MSR_IA32_FEATURE_CONTROL:
4744 env->msr_ia32_feature_control = msrs[i].data;
4745 break;
4746 case MSR_IA32_BNDCFGS:
4747 env->msr_bndcfgs = msrs[i].data;
4748 break;
4749 case MSR_IA32_XSS:
4750 env->xss = msrs[i].data;
4751 break;
4752 case MSR_IA32_UMWAIT_CONTROL:
4753 env->umwait = msrs[i].data;
4754 break;
4755 case MSR_IA32_PKRS:
4756 env->pkrs = msrs[i].data;
4757 break;
4758 default:
4759 if (msrs[i].index >= MSR_MC0_CTL &&
4760 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4761 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4762 }
4763 break;
4764 case MSR_KVM_ASYNC_PF_EN:
4765 env->async_pf_en_msr = msrs[i].data;
4766 break;
4767 case MSR_KVM_ASYNC_PF_INT:
4768 env->async_pf_int_msr = msrs[i].data;
4769 break;
4770 case MSR_KVM_PV_EOI_EN:
4771 env->pv_eoi_en_msr = msrs[i].data;
4772 break;
4773 case MSR_KVM_STEAL_TIME:
4774 env->steal_time_msr = msrs[i].data;
4775 break;
4776 case MSR_KVM_POLL_CONTROL: {
4777 env->poll_control_msr = msrs[i].data;
4778 break;
4779 }
4780 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4781 env->msr_fixed_ctr_ctrl = msrs[i].data;
4782 break;
4783 case MSR_CORE_PERF_GLOBAL_CTRL:
4784 env->msr_global_ctrl = msrs[i].data;
4785 break;
4786 case MSR_CORE_PERF_GLOBAL_STATUS:
4787 env->msr_global_status = msrs[i].data;
4788 break;
4789 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4790 env->msr_global_ovf_ctrl = msrs[i].data;
4791 break;
4792 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4793 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4794 break;
4795 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4796 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4797 break;
4798 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4799 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4800 break;
4801 case HV_X64_MSR_HYPERCALL:
4802 env->msr_hv_hypercall = msrs[i].data;
4803 break;
4804 case HV_X64_MSR_GUEST_OS_ID:
4805 env->msr_hv_guest_os_id = msrs[i].data;
4806 break;
4807 case HV_X64_MSR_APIC_ASSIST_PAGE:
4808 env->msr_hv_vapic = msrs[i].data;
4809 break;
4810 case HV_X64_MSR_REFERENCE_TSC:
4811 env->msr_hv_tsc = msrs[i].data;
4812 break;
4813 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4814 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4815 break;
4816 case HV_X64_MSR_VP_RUNTIME:
4817 env->msr_hv_runtime = msrs[i].data;
4818 break;
4819 case HV_X64_MSR_SCONTROL:
4820 env->msr_hv_synic_control = msrs[i].data;
4821 break;
4822 case HV_X64_MSR_SIEFP:
4823 env->msr_hv_synic_evt_page = msrs[i].data;
4824 break;
4825 case HV_X64_MSR_SIMP:
4826 env->msr_hv_synic_msg_page = msrs[i].data;
4827 break;
4828 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4829 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4830 break;
4831 case HV_X64_MSR_STIMER0_CONFIG:
4832 case HV_X64_MSR_STIMER1_CONFIG:
4833 case HV_X64_MSR_STIMER2_CONFIG:
4834 case HV_X64_MSR_STIMER3_CONFIG:
4835 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4836 msrs[i].data;
4837 break;
4838 case HV_X64_MSR_STIMER0_COUNT:
4839 case HV_X64_MSR_STIMER1_COUNT:
4840 case HV_X64_MSR_STIMER2_COUNT:
4841 case HV_X64_MSR_STIMER3_COUNT:
4842 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4843 msrs[i].data;
4844 break;
4845 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4846 env->msr_hv_reenlightenment_control = msrs[i].data;
4847 break;
4848 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4849 env->msr_hv_tsc_emulation_control = msrs[i].data;
4850 break;
4851 case HV_X64_MSR_TSC_EMULATION_STATUS:
4852 env->msr_hv_tsc_emulation_status = msrs[i].data;
4853 break;
4854 case HV_X64_MSR_SYNDBG_OPTIONS:
4855 env->msr_hv_syndbg_options = msrs[i].data;
4856 break;
4857 case MSR_MTRRdefType:
4858 env->mtrr_deftype = msrs[i].data;
4859 break;
4860 case MSR_MTRRfix64K_00000:
4861 env->mtrr_fixed[0] = msrs[i].data;
4862 break;
4863 case MSR_MTRRfix16K_80000:
4864 env->mtrr_fixed[1] = msrs[i].data;
4865 break;
4866 case MSR_MTRRfix16K_A0000:
4867 env->mtrr_fixed[2] = msrs[i].data;
4868 break;
4869 case MSR_MTRRfix4K_C0000:
4870 env->mtrr_fixed[3] = msrs[i].data;
4871 break;
4872 case MSR_MTRRfix4K_C8000:
4873 env->mtrr_fixed[4] = msrs[i].data;
4874 break;
4875 case MSR_MTRRfix4K_D0000:
4876 env->mtrr_fixed[5] = msrs[i].data;
4877 break;
4878 case MSR_MTRRfix4K_D8000:
4879 env->mtrr_fixed[6] = msrs[i].data;
4880 break;
4881 case MSR_MTRRfix4K_E0000:
4882 env->mtrr_fixed[7] = msrs[i].data;
4883 break;
4884 case MSR_MTRRfix4K_E8000:
4885 env->mtrr_fixed[8] = msrs[i].data;
4886 break;
4887 case MSR_MTRRfix4K_F0000:
4888 env->mtrr_fixed[9] = msrs[i].data;
4889 break;
4890 case MSR_MTRRfix4K_F8000:
4891 env->mtrr_fixed[10] = msrs[i].data;
4892 break;
4893 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4894 if (index & 1) {
4895 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4896 mtrr_top_bits;
4897 } else {
4898 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4899 }
4900 break;
4901 case MSR_IA32_SPEC_CTRL:
4902 env->spec_ctrl = msrs[i].data;
4903 break;
4904 case MSR_AMD64_TSC_RATIO:
4905 env->amd_tsc_scale_msr = msrs[i].data;
4906 break;
4907 case MSR_IA32_TSX_CTRL:
4908 env->tsx_ctrl = msrs[i].data;
4909 break;
4910 case MSR_VIRT_SSBD:
4911 env->virt_ssbd = msrs[i].data;
4912 break;
4913 case MSR_IA32_RTIT_CTL:
4914 env->msr_rtit_ctrl = msrs[i].data;
4915 break;
4916 case MSR_IA32_RTIT_STATUS:
4917 env->msr_rtit_status = msrs[i].data;
4918 break;
4919 case MSR_IA32_RTIT_OUTPUT_BASE:
4920 env->msr_rtit_output_base = msrs[i].data;
4921 break;
4922 case MSR_IA32_RTIT_OUTPUT_MASK:
4923 env->msr_rtit_output_mask = msrs[i].data;
4924 break;
4925 case MSR_IA32_RTIT_CR3_MATCH:
4926 env->msr_rtit_cr3_match = msrs[i].data;
4927 break;
4928 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4929 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4930 break;
4931 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4932 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4933 msrs[i].data;
4934 break;
4935 case MSR_IA32_XFD:
4936 env->msr_xfd = msrs[i].data;
4937 break;
4938 case MSR_IA32_XFD_ERR:
4939 env->msr_xfd_err = msrs[i].data;
4940 break;
4941 case MSR_ARCH_LBR_CTL:
4942 env->msr_lbr_ctl = msrs[i].data;
4943 break;
4944 case MSR_ARCH_LBR_DEPTH:
4945 env->msr_lbr_depth = msrs[i].data;
4946 break;
4947 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4948 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4949 break;
4950 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4951 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4952 break;
4953 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4954 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4955 break;
4956 case MSR_K7_HWCR:
4957 env->msr_hwcr = msrs[i].data;
4958 break;
4959 }
4960 }
4961
4962 return 0;
4963 }
4964
kvm_put_mp_state(X86CPU * cpu)4965 static int kvm_put_mp_state(X86CPU *cpu)
4966 {
4967 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4968
4969 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4970 }
4971
kvm_get_mp_state(X86CPU * cpu)4972 static int kvm_get_mp_state(X86CPU *cpu)
4973 {
4974 CPUState *cs = CPU(cpu);
4975 CPUX86State *env = &cpu->env;
4976 struct kvm_mp_state mp_state;
4977 int ret;
4978
4979 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
4980 if (ret < 0) {
4981 return ret;
4982 }
4983 env->mp_state = mp_state.mp_state;
4984 if (kvm_irqchip_in_kernel()) {
4985 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
4986 }
4987 return 0;
4988 }
4989
kvm_get_apic(X86CPU * cpu)4990 static int kvm_get_apic(X86CPU *cpu)
4991 {
4992 DeviceState *apic = cpu->apic_state;
4993 struct kvm_lapic_state kapic;
4994 int ret;
4995
4996 if (apic && kvm_irqchip_in_kernel()) {
4997 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
4998 if (ret < 0) {
4999 return ret;
5000 }
5001
5002 kvm_get_apic_state(apic, &kapic);
5003 }
5004 return 0;
5005 }
5006
kvm_put_vcpu_events(X86CPU * cpu,int level)5007 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5008 {
5009 CPUState *cs = CPU(cpu);
5010 CPUX86State *env = &cpu->env;
5011 struct kvm_vcpu_events events = {};
5012
5013 events.flags = 0;
5014
5015 if (has_exception_payload) {
5016 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5017 events.exception.pending = env->exception_pending;
5018 events.exception_has_payload = env->exception_has_payload;
5019 events.exception_payload = env->exception_payload;
5020 }
5021 events.exception.nr = env->exception_nr;
5022 events.exception.injected = env->exception_injected;
5023 events.exception.has_error_code = env->has_error_code;
5024 events.exception.error_code = env->error_code;
5025
5026 events.interrupt.injected = (env->interrupt_injected >= 0);
5027 events.interrupt.nr = env->interrupt_injected;
5028 events.interrupt.soft = env->soft_interrupt;
5029
5030 events.nmi.injected = env->nmi_injected;
5031 events.nmi.pending = env->nmi_pending;
5032 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5033
5034 events.sipi_vector = env->sipi_vector;
5035
5036 if (has_msr_smbase) {
5037 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5038 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5039 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5040 if (kvm_irqchip_in_kernel()) {
5041 /* As soon as these are moved to the kernel, remove them
5042 * from cs->interrupt_request.
5043 */
5044 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5045 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5046 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5047 } else {
5048 /* Keep these in cs->interrupt_request. */
5049 events.smi.pending = 0;
5050 events.smi.latched_init = 0;
5051 }
5052 }
5053
5054 if (level >= KVM_PUT_RESET_STATE) {
5055 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5056 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5057 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5058 }
5059 }
5060
5061 if (has_triple_fault_event) {
5062 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5063 events.triple_fault.pending = env->triple_fault_pending;
5064 }
5065
5066 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5067 }
5068
kvm_get_vcpu_events(X86CPU * cpu)5069 static int kvm_get_vcpu_events(X86CPU *cpu)
5070 {
5071 CPUX86State *env = &cpu->env;
5072 struct kvm_vcpu_events events;
5073 int ret;
5074
5075 memset(&events, 0, sizeof(events));
5076 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5077 if (ret < 0) {
5078 return ret;
5079 }
5080
5081 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5082 env->exception_pending = events.exception.pending;
5083 env->exception_has_payload = events.exception_has_payload;
5084 env->exception_payload = events.exception_payload;
5085 } else {
5086 env->exception_pending = 0;
5087 env->exception_has_payload = false;
5088 }
5089 env->exception_injected = events.exception.injected;
5090 env->exception_nr =
5091 (env->exception_pending || env->exception_injected) ?
5092 events.exception.nr : -1;
5093 env->has_error_code = events.exception.has_error_code;
5094 env->error_code = events.exception.error_code;
5095
5096 env->interrupt_injected =
5097 events.interrupt.injected ? events.interrupt.nr : -1;
5098 env->soft_interrupt = events.interrupt.soft;
5099
5100 env->nmi_injected = events.nmi.injected;
5101 env->nmi_pending = events.nmi.pending;
5102 if (events.nmi.masked) {
5103 env->hflags2 |= HF2_NMI_MASK;
5104 } else {
5105 env->hflags2 &= ~HF2_NMI_MASK;
5106 }
5107
5108 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5109 if (events.smi.smm) {
5110 env->hflags |= HF_SMM_MASK;
5111 } else {
5112 env->hflags &= ~HF_SMM_MASK;
5113 }
5114 if (events.smi.pending) {
5115 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5116 } else {
5117 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5118 }
5119 if (events.smi.smm_inside_nmi) {
5120 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5121 } else {
5122 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5123 }
5124 if (events.smi.latched_init) {
5125 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5126 } else {
5127 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5128 }
5129 }
5130
5131 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5132 env->triple_fault_pending = events.triple_fault.pending;
5133 }
5134
5135 env->sipi_vector = events.sipi_vector;
5136
5137 return 0;
5138 }
5139
kvm_put_debugregs(X86CPU * cpu)5140 static int kvm_put_debugregs(X86CPU *cpu)
5141 {
5142 CPUX86State *env = &cpu->env;
5143 struct kvm_debugregs dbgregs;
5144 int i;
5145
5146 memset(&dbgregs, 0, sizeof(dbgregs));
5147 for (i = 0; i < 4; i++) {
5148 dbgregs.db[i] = env->dr[i];
5149 }
5150 dbgregs.dr6 = env->dr[6];
5151 dbgregs.dr7 = env->dr[7];
5152 dbgregs.flags = 0;
5153
5154 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5155 }
5156
kvm_get_debugregs(X86CPU * cpu)5157 static int kvm_get_debugregs(X86CPU *cpu)
5158 {
5159 CPUX86State *env = &cpu->env;
5160 struct kvm_debugregs dbgregs;
5161 int i, ret;
5162
5163 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5164 if (ret < 0) {
5165 return ret;
5166 }
5167 for (i = 0; i < 4; i++) {
5168 env->dr[i] = dbgregs.db[i];
5169 }
5170 env->dr[4] = env->dr[6] = dbgregs.dr6;
5171 env->dr[5] = env->dr[7] = dbgregs.dr7;
5172
5173 return 0;
5174 }
5175
kvm_put_nested_state(X86CPU * cpu)5176 static int kvm_put_nested_state(X86CPU *cpu)
5177 {
5178 CPUX86State *env = &cpu->env;
5179 int max_nested_state_len = kvm_max_nested_state_length();
5180
5181 if (!env->nested_state) {
5182 return 0;
5183 }
5184
5185 /*
5186 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5187 */
5188 if (env->hflags & HF_GUEST_MASK) {
5189 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5190 } else {
5191 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5192 }
5193
5194 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5195 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5196 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5197 } else {
5198 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5199 }
5200
5201 assert(env->nested_state->size <= max_nested_state_len);
5202 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5203 }
5204
kvm_get_nested_state(X86CPU * cpu)5205 static int kvm_get_nested_state(X86CPU *cpu)
5206 {
5207 CPUX86State *env = &cpu->env;
5208 int max_nested_state_len = kvm_max_nested_state_length();
5209 int ret;
5210
5211 if (!env->nested_state) {
5212 return 0;
5213 }
5214
5215 /*
5216 * It is possible that migration restored a smaller size into
5217 * nested_state->hdr.size than what our kernel support.
5218 * We preserve migration origin nested_state->hdr.size for
5219 * call to KVM_SET_NESTED_STATE but wish that our next call
5220 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5221 */
5222 env->nested_state->size = max_nested_state_len;
5223
5224 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5225 if (ret < 0) {
5226 return ret;
5227 }
5228
5229 /*
5230 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5231 */
5232 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5233 env->hflags |= HF_GUEST_MASK;
5234 } else {
5235 env->hflags &= ~HF_GUEST_MASK;
5236 }
5237
5238 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5239 if (cpu_has_svm(env)) {
5240 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5241 env->hflags2 |= HF2_GIF_MASK;
5242 } else {
5243 env->hflags2 &= ~HF2_GIF_MASK;
5244 }
5245 }
5246
5247 return ret;
5248 }
5249
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5250 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5251 {
5252 X86CPU *x86_cpu = X86_CPU(cpu);
5253 int ret;
5254
5255 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5256
5257 /*
5258 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5259 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5260 * precede kvm_put_nested_state() when 'real' nested state is set.
5261 */
5262 if (level >= KVM_PUT_RESET_STATE) {
5263 ret = kvm_put_msr_feature_control(x86_cpu);
5264 if (ret < 0) {
5265 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5266 return ret;
5267 }
5268 }
5269
5270 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5271 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5272 if (ret < 0) {
5273 error_setg_errno(errp, -ret, "Failed to set special registers");
5274 return ret;
5275 }
5276
5277 if (level >= KVM_PUT_RESET_STATE) {
5278 ret = kvm_put_nested_state(x86_cpu);
5279 if (ret < 0) {
5280 error_setg_errno(errp, -ret, "Failed to set nested state");
5281 return ret;
5282 }
5283 }
5284
5285 if (level == KVM_PUT_FULL_STATE) {
5286 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5287 * because TSC frequency mismatch shouldn't abort migration,
5288 * unless the user explicitly asked for a more strict TSC
5289 * setting (e.g. using an explicit "tsc-freq" option).
5290 */
5291 kvm_arch_set_tsc_khz(cpu);
5292 }
5293
5294 #ifdef CONFIG_XEN_EMU
5295 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5296 ret = kvm_put_xen_state(cpu);
5297 if (ret < 0) {
5298 error_setg_errno(errp, -ret, "Failed to set Xen state");
5299 return ret;
5300 }
5301 }
5302 #endif
5303
5304 ret = kvm_getput_regs(x86_cpu, 1);
5305 if (ret < 0) {
5306 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5307 return ret;
5308 }
5309 ret = kvm_put_xsave(x86_cpu);
5310 if (ret < 0) {
5311 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5312 return ret;
5313 }
5314 ret = kvm_put_xcrs(x86_cpu);
5315 if (ret < 0) {
5316 error_setg_errno(errp, -ret, "Failed to set XCRs");
5317 return ret;
5318 }
5319 ret = kvm_put_msrs(x86_cpu, level);
5320 if (ret < 0) {
5321 error_setg_errno(errp, -ret, "Failed to set MSRs");
5322 return ret;
5323 }
5324 ret = kvm_put_vcpu_events(x86_cpu, level);
5325 if (ret < 0) {
5326 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5327 return ret;
5328 }
5329 if (level >= KVM_PUT_RESET_STATE) {
5330 ret = kvm_put_mp_state(x86_cpu);
5331 if (ret < 0) {
5332 error_setg_errno(errp, -ret, "Failed to set MP state");
5333 return ret;
5334 }
5335 }
5336
5337 ret = kvm_put_tscdeadline_msr(x86_cpu);
5338 if (ret < 0) {
5339 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5340 return ret;
5341 }
5342 ret = kvm_put_debugregs(x86_cpu);
5343 if (ret < 0) {
5344 error_setg_errno(errp, -ret, "Failed to set debug registers");
5345 return ret;
5346 }
5347 return 0;
5348 }
5349
kvm_arch_get_registers(CPUState * cs,Error ** errp)5350 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5351 {
5352 X86CPU *cpu = X86_CPU(cs);
5353 int ret;
5354
5355 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5356
5357 ret = kvm_get_vcpu_events(cpu);
5358 if (ret < 0) {
5359 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5360 goto out;
5361 }
5362 /*
5363 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5364 * KVM_GET_REGS and KVM_GET_SREGS.
5365 */
5366 ret = kvm_get_mp_state(cpu);
5367 if (ret < 0) {
5368 error_setg_errno(errp, -ret, "Failed to get MP state");
5369 goto out;
5370 }
5371 ret = kvm_getput_regs(cpu, 0);
5372 if (ret < 0) {
5373 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5374 goto out;
5375 }
5376 ret = kvm_get_xsave(cpu);
5377 if (ret < 0) {
5378 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5379 goto out;
5380 }
5381 ret = kvm_get_xcrs(cpu);
5382 if (ret < 0) {
5383 error_setg_errno(errp, -ret, "Failed to get XCRs");
5384 goto out;
5385 }
5386 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5387 if (ret < 0) {
5388 error_setg_errno(errp, -ret, "Failed to get special registers");
5389 goto out;
5390 }
5391 ret = kvm_get_msrs(cpu);
5392 if (ret < 0) {
5393 error_setg_errno(errp, -ret, "Failed to get MSRs");
5394 goto out;
5395 }
5396 ret = kvm_get_apic(cpu);
5397 if (ret < 0) {
5398 error_setg_errno(errp, -ret, "Failed to get APIC");
5399 goto out;
5400 }
5401 ret = kvm_get_debugregs(cpu);
5402 if (ret < 0) {
5403 error_setg_errno(errp, -ret, "Failed to get debug registers");
5404 goto out;
5405 }
5406 ret = kvm_get_nested_state(cpu);
5407 if (ret < 0) {
5408 error_setg_errno(errp, -ret, "Failed to get nested state");
5409 goto out;
5410 }
5411 #ifdef CONFIG_XEN_EMU
5412 if (xen_mode == XEN_EMULATE) {
5413 ret = kvm_get_xen_state(cs);
5414 if (ret < 0) {
5415 error_setg_errno(errp, -ret, "Failed to get Xen state");
5416 goto out;
5417 }
5418 }
5419 #endif
5420 ret = 0;
5421 out:
5422 cpu_sync_bndcs_hflags(&cpu->env);
5423 return ret;
5424 }
5425
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5426 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5427 {
5428 X86CPU *x86_cpu = X86_CPU(cpu);
5429 CPUX86State *env = &x86_cpu->env;
5430 int ret;
5431
5432 /* Inject NMI */
5433 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5434 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5435 bql_lock();
5436 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5437 bql_unlock();
5438 DPRINTF("injected NMI\n");
5439 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5440 if (ret < 0) {
5441 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5442 strerror(-ret));
5443 }
5444 }
5445 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5446 bql_lock();
5447 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5448 bql_unlock();
5449 DPRINTF("injected SMI\n");
5450 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5451 if (ret < 0) {
5452 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5453 strerror(-ret));
5454 }
5455 }
5456 }
5457
5458 if (!kvm_pic_in_kernel()) {
5459 bql_lock();
5460 }
5461
5462 /* Force the VCPU out of its inner loop to process any INIT requests
5463 * or (for userspace APIC, but it is cheap to combine the checks here)
5464 * pending TPR access reports.
5465 */
5466 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5467 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5468 !(env->hflags & HF_SMM_MASK)) {
5469 cpu->exit_request = 1;
5470 }
5471 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5472 cpu->exit_request = 1;
5473 }
5474 }
5475
5476 if (!kvm_pic_in_kernel()) {
5477 /* Try to inject an interrupt if the guest can accept it */
5478 if (run->ready_for_interrupt_injection &&
5479 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5480 (env->eflags & IF_MASK)) {
5481 int irq;
5482
5483 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5484 irq = cpu_get_pic_interrupt(env);
5485 if (irq >= 0) {
5486 struct kvm_interrupt intr;
5487
5488 intr.irq = irq;
5489 DPRINTF("injected interrupt %d\n", irq);
5490 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5491 if (ret < 0) {
5492 fprintf(stderr,
5493 "KVM: injection failed, interrupt lost (%s)\n",
5494 strerror(-ret));
5495 }
5496 }
5497 }
5498
5499 /* If we have an interrupt but the guest is not ready to receive an
5500 * interrupt, request an interrupt window exit. This will
5501 * cause a return to userspace as soon as the guest is ready to
5502 * receive interrupts. */
5503 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5504 run->request_interrupt_window = 1;
5505 } else {
5506 run->request_interrupt_window = 0;
5507 }
5508
5509 DPRINTF("setting tpr\n");
5510 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5511
5512 bql_unlock();
5513 }
5514 }
5515
kvm_rate_limit_on_bus_lock(void)5516 static void kvm_rate_limit_on_bus_lock(void)
5517 {
5518 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5519
5520 if (delay_ns) {
5521 g_usleep(delay_ns / SCALE_US);
5522 }
5523 }
5524
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5525 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5526 {
5527 X86CPU *x86_cpu = X86_CPU(cpu);
5528 CPUX86State *env = &x86_cpu->env;
5529
5530 if (run->flags & KVM_RUN_X86_SMM) {
5531 env->hflags |= HF_SMM_MASK;
5532 } else {
5533 env->hflags &= ~HF_SMM_MASK;
5534 }
5535 if (run->if_flag) {
5536 env->eflags |= IF_MASK;
5537 } else {
5538 env->eflags &= ~IF_MASK;
5539 }
5540 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5541 kvm_rate_limit_on_bus_lock();
5542 }
5543
5544 #ifdef CONFIG_XEN_EMU
5545 /*
5546 * If the callback is asserted as a GSI (or PCI INTx) then check if
5547 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5548 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5549 * EOI and only resample then, exactly how the VFIO eventfd pairs
5550 * are designed to work for level triggered interrupts.
5551 */
5552 if (x86_cpu->env.xen_callback_asserted) {
5553 kvm_xen_maybe_deassert_callback(cpu);
5554 }
5555 #endif
5556
5557 /* We need to protect the apic state against concurrent accesses from
5558 * different threads in case the userspace irqchip is used. */
5559 if (!kvm_irqchip_in_kernel()) {
5560 bql_lock();
5561 }
5562 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5563 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5564 if (!kvm_irqchip_in_kernel()) {
5565 bql_unlock();
5566 }
5567 return cpu_get_mem_attrs(env);
5568 }
5569
kvm_arch_process_async_events(CPUState * cs)5570 int kvm_arch_process_async_events(CPUState *cs)
5571 {
5572 X86CPU *cpu = X86_CPU(cs);
5573 CPUX86State *env = &cpu->env;
5574
5575 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5576 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5577 assert(env->mcg_cap);
5578
5579 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5580
5581 kvm_cpu_synchronize_state(cs);
5582
5583 if (env->exception_nr == EXCP08_DBLE) {
5584 /* this means triple fault */
5585 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5586 cs->exit_request = 1;
5587 return 0;
5588 }
5589 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5590 env->has_error_code = 0;
5591
5592 cs->halted = 0;
5593 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5594 env->mp_state = KVM_MP_STATE_RUNNABLE;
5595 }
5596 }
5597
5598 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5599 !(env->hflags & HF_SMM_MASK)) {
5600 kvm_cpu_synchronize_state(cs);
5601 do_cpu_init(cpu);
5602 }
5603
5604 if (kvm_irqchip_in_kernel()) {
5605 return 0;
5606 }
5607
5608 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5609 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5610 apic_poll_irq(cpu->apic_state);
5611 }
5612 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5613 (env->eflags & IF_MASK)) ||
5614 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5615 cs->halted = 0;
5616 }
5617 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5618 kvm_cpu_synchronize_state(cs);
5619 do_cpu_sipi(cpu);
5620 }
5621 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5622 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5623 kvm_cpu_synchronize_state(cs);
5624 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5625 env->tpr_access_type);
5626 }
5627
5628 return cs->halted;
5629 }
5630
kvm_handle_halt(X86CPU * cpu)5631 static int kvm_handle_halt(X86CPU *cpu)
5632 {
5633 CPUState *cs = CPU(cpu);
5634 CPUX86State *env = &cpu->env;
5635
5636 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5637 (env->eflags & IF_MASK)) &&
5638 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5639 cs->halted = 1;
5640 return EXCP_HLT;
5641 }
5642
5643 return 0;
5644 }
5645
kvm_handle_tpr_access(X86CPU * cpu)5646 static int kvm_handle_tpr_access(X86CPU *cpu)
5647 {
5648 CPUState *cs = CPU(cpu);
5649 struct kvm_run *run = cs->kvm_run;
5650
5651 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5652 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5653 : TPR_ACCESS_READ);
5654 return 1;
5655 }
5656
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5657 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5658 {
5659 static const uint8_t int3 = 0xcc;
5660
5661 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5662 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5663 return -EINVAL;
5664 }
5665 return 0;
5666 }
5667
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5668 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5669 {
5670 uint8_t int3;
5671
5672 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5673 return -EINVAL;
5674 }
5675 if (int3 != 0xcc) {
5676 return 0;
5677 }
5678 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5679 return -EINVAL;
5680 }
5681 return 0;
5682 }
5683
5684 static struct {
5685 target_ulong addr;
5686 int len;
5687 int type;
5688 } hw_breakpoint[4];
5689
5690 static int nb_hw_breakpoint;
5691
find_hw_breakpoint(target_ulong addr,int len,int type)5692 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5693 {
5694 int n;
5695
5696 for (n = 0; n < nb_hw_breakpoint; n++) {
5697 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5698 (hw_breakpoint[n].len == len || len == -1)) {
5699 return n;
5700 }
5701 }
5702 return -1;
5703 }
5704
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5705 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5706 {
5707 switch (type) {
5708 case GDB_BREAKPOINT_HW:
5709 len = 1;
5710 break;
5711 case GDB_WATCHPOINT_WRITE:
5712 case GDB_WATCHPOINT_ACCESS:
5713 switch (len) {
5714 case 1:
5715 break;
5716 case 2:
5717 case 4:
5718 case 8:
5719 if (addr & (len - 1)) {
5720 return -EINVAL;
5721 }
5722 break;
5723 default:
5724 return -EINVAL;
5725 }
5726 break;
5727 default:
5728 return -ENOSYS;
5729 }
5730
5731 if (nb_hw_breakpoint == 4) {
5732 return -ENOBUFS;
5733 }
5734 if (find_hw_breakpoint(addr, len, type) >= 0) {
5735 return -EEXIST;
5736 }
5737 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5738 hw_breakpoint[nb_hw_breakpoint].len = len;
5739 hw_breakpoint[nb_hw_breakpoint].type = type;
5740 nb_hw_breakpoint++;
5741
5742 return 0;
5743 }
5744
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5745 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5746 {
5747 int n;
5748
5749 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5750 if (n < 0) {
5751 return -ENOENT;
5752 }
5753 nb_hw_breakpoint--;
5754 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5755
5756 return 0;
5757 }
5758
kvm_arch_remove_all_hw_breakpoints(void)5759 void kvm_arch_remove_all_hw_breakpoints(void)
5760 {
5761 nb_hw_breakpoint = 0;
5762 }
5763
5764 static CPUWatchpoint hw_watchpoint;
5765
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5766 static int kvm_handle_debug(X86CPU *cpu,
5767 struct kvm_debug_exit_arch *arch_info)
5768 {
5769 CPUState *cs = CPU(cpu);
5770 CPUX86State *env = &cpu->env;
5771 int ret = 0;
5772 int n;
5773
5774 if (arch_info->exception == EXCP01_DB) {
5775 if (arch_info->dr6 & DR6_BS) {
5776 if (cs->singlestep_enabled) {
5777 ret = EXCP_DEBUG;
5778 }
5779 } else {
5780 for (n = 0; n < 4; n++) {
5781 if (arch_info->dr6 & (1 << n)) {
5782 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5783 case 0x0:
5784 ret = EXCP_DEBUG;
5785 break;
5786 case 0x1:
5787 ret = EXCP_DEBUG;
5788 cs->watchpoint_hit = &hw_watchpoint;
5789 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5790 hw_watchpoint.flags = BP_MEM_WRITE;
5791 break;
5792 case 0x3:
5793 ret = EXCP_DEBUG;
5794 cs->watchpoint_hit = &hw_watchpoint;
5795 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5796 hw_watchpoint.flags = BP_MEM_ACCESS;
5797 break;
5798 }
5799 }
5800 }
5801 }
5802 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5803 ret = EXCP_DEBUG;
5804 }
5805 if (ret == 0) {
5806 cpu_synchronize_state(cs);
5807 assert(env->exception_nr == -1);
5808
5809 /* pass to guest */
5810 kvm_queue_exception(env, arch_info->exception,
5811 arch_info->exception == EXCP01_DB,
5812 arch_info->dr6);
5813 env->has_error_code = 0;
5814 }
5815
5816 return ret;
5817 }
5818
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5819 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5820 {
5821 const uint8_t type_code[] = {
5822 [GDB_BREAKPOINT_HW] = 0x0,
5823 [GDB_WATCHPOINT_WRITE] = 0x1,
5824 [GDB_WATCHPOINT_ACCESS] = 0x3
5825 };
5826 const uint8_t len_code[] = {
5827 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5828 };
5829 int n;
5830
5831 if (kvm_sw_breakpoints_active(cpu)) {
5832 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5833 }
5834 if (nb_hw_breakpoint > 0) {
5835 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5836 dbg->arch.debugreg[7] = 0x0600;
5837 for (n = 0; n < nb_hw_breakpoint; n++) {
5838 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5839 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5840 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5841 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5842 }
5843 }
5844 }
5845
kvm_install_msr_filters(KVMState * s)5846 static bool kvm_install_msr_filters(KVMState *s)
5847 {
5848 uint64_t zero = 0;
5849 struct kvm_msr_filter filter = {
5850 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5851 };
5852 int r, i, j = 0;
5853
5854 for (i = 0; i < KVM_MSR_FILTER_MAX_RANGES; i++) {
5855 KVMMSRHandlers *handler = &msr_handlers[i];
5856 if (handler->msr) {
5857 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5858
5859 *range = (struct kvm_msr_filter_range) {
5860 .flags = 0,
5861 .nmsrs = 1,
5862 .base = handler->msr,
5863 .bitmap = (__u8 *)&zero,
5864 };
5865
5866 if (handler->rdmsr) {
5867 range->flags |= KVM_MSR_FILTER_READ;
5868 }
5869
5870 if (handler->wrmsr) {
5871 range->flags |= KVM_MSR_FILTER_WRITE;
5872 }
5873 }
5874 }
5875
5876 r = kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5877 if (r) {
5878 return false;
5879 }
5880
5881 return true;
5882 }
5883
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5884 static bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5885 QEMUWRMSRHandler *wrmsr)
5886 {
5887 int i;
5888
5889 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5890 if (!msr_handlers[i].msr) {
5891 msr_handlers[i] = (KVMMSRHandlers) {
5892 .msr = msr,
5893 .rdmsr = rdmsr,
5894 .wrmsr = wrmsr,
5895 };
5896
5897 if (!kvm_install_msr_filters(s)) {
5898 msr_handlers[i] = (KVMMSRHandlers) { };
5899 return false;
5900 }
5901
5902 return true;
5903 }
5904 }
5905
5906 return false;
5907 }
5908
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5909 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5910 {
5911 int i;
5912 bool r;
5913
5914 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5915 KVMMSRHandlers *handler = &msr_handlers[i];
5916 if (run->msr.index == handler->msr) {
5917 if (handler->rdmsr) {
5918 r = handler->rdmsr(cpu, handler->msr,
5919 (uint64_t *)&run->msr.data);
5920 run->msr.error = r ? 0 : 1;
5921 return 0;
5922 }
5923 }
5924 }
5925
5926 g_assert_not_reached();
5927 }
5928
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5929 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5930 {
5931 int i;
5932 bool r;
5933
5934 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5935 KVMMSRHandlers *handler = &msr_handlers[i];
5936 if (run->msr.index == handler->msr) {
5937 if (handler->wrmsr) {
5938 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5939 run->msr.error = r ? 0 : 1;
5940 return 0;
5941 }
5942 }
5943 }
5944
5945 g_assert_not_reached();
5946 }
5947
5948 static bool has_sgx_provisioning;
5949
__kvm_enable_sgx_provisioning(KVMState * s)5950 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5951 {
5952 int fd, ret;
5953
5954 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5955 return false;
5956 }
5957
5958 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5959 if (fd < 0) {
5960 return false;
5961 }
5962
5963 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5964 if (ret) {
5965 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5966 exit(1);
5967 }
5968 close(fd);
5969 return true;
5970 }
5971
kvm_enable_sgx_provisioning(KVMState * s)5972 bool kvm_enable_sgx_provisioning(KVMState *s)
5973 {
5974 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5975 }
5976
host_supports_vmx(void)5977 static bool host_supports_vmx(void)
5978 {
5979 uint32_t ecx, unused;
5980
5981 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5982 return ecx & CPUID_EXT_VMX;
5983 }
5984
5985 /*
5986 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
5987 * to service guest-initiated memory attribute update requests so that
5988 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
5989 * backed by the private memory pool provided by guest_memfd, and as such
5990 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
5991 *
5992 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
5993 * migration, are not implemented here currently.
5994 *
5995 * For the guest_memfd use-case, these exits will generally be synthesized
5996 * by KVM based on platform-specific hypercalls, like GHCB requests in the
5997 * case of SEV-SNP, and not issued directly within the guest though the
5998 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
5999 * not actually advertised to guests via the KVM CPUID feature bit, as
6000 * opposed to SEV live migration where it would be. Since it is unlikely the
6001 * SEV live migration use-case would be useful for guest-memfd backed guests,
6002 * because private/shared page tracking is already provided through other
6003 * means, these 2 use-cases should be treated as being mutually-exclusive.
6004 */
kvm_handle_hc_map_gpa_range(struct kvm_run * run)6005 static int kvm_handle_hc_map_gpa_range(struct kvm_run *run)
6006 {
6007 uint64_t gpa, size, attributes;
6008
6009 if (!machine_require_guest_memfd(current_machine))
6010 return -EINVAL;
6011
6012 gpa = run->hypercall.args[0];
6013 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6014 attributes = run->hypercall.args[2];
6015
6016 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6017
6018 return kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6019 }
6020
kvm_handle_hypercall(struct kvm_run * run)6021 static int kvm_handle_hypercall(struct kvm_run *run)
6022 {
6023 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6024 return kvm_handle_hc_map_gpa_range(run);
6025
6026 return -EINVAL;
6027 }
6028
6029 #define VMX_INVALID_GUEST_STATE 0x80000021
6030
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6031 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6032 {
6033 X86CPU *cpu = X86_CPU(cs);
6034 uint64_t code;
6035 int ret;
6036 bool ctx_invalid;
6037 KVMState *state;
6038
6039 switch (run->exit_reason) {
6040 case KVM_EXIT_HLT:
6041 DPRINTF("handle_hlt\n");
6042 bql_lock();
6043 ret = kvm_handle_halt(cpu);
6044 bql_unlock();
6045 break;
6046 case KVM_EXIT_SET_TPR:
6047 ret = 0;
6048 break;
6049 case KVM_EXIT_TPR_ACCESS:
6050 bql_lock();
6051 ret = kvm_handle_tpr_access(cpu);
6052 bql_unlock();
6053 break;
6054 case KVM_EXIT_FAIL_ENTRY:
6055 code = run->fail_entry.hardware_entry_failure_reason;
6056 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6057 code);
6058 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6059 fprintf(stderr,
6060 "\nIf you're running a guest on an Intel machine without "
6061 "unrestricted mode\n"
6062 "support, the failure can be most likely due to the guest "
6063 "entering an invalid\n"
6064 "state for Intel VT. For example, the guest maybe running "
6065 "in big real mode\n"
6066 "which is not supported on less recent Intel processors."
6067 "\n\n");
6068 }
6069 ret = -1;
6070 break;
6071 case KVM_EXIT_EXCEPTION:
6072 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6073 run->ex.exception, run->ex.error_code);
6074 ret = -1;
6075 break;
6076 case KVM_EXIT_DEBUG:
6077 DPRINTF("kvm_exit_debug\n");
6078 bql_lock();
6079 ret = kvm_handle_debug(cpu, &run->debug.arch);
6080 bql_unlock();
6081 break;
6082 case KVM_EXIT_HYPERV:
6083 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6084 break;
6085 case KVM_EXIT_IOAPIC_EOI:
6086 ioapic_eoi_broadcast(run->eoi.vector);
6087 ret = 0;
6088 break;
6089 case KVM_EXIT_X86_BUS_LOCK:
6090 /* already handled in kvm_arch_post_run */
6091 ret = 0;
6092 break;
6093 case KVM_EXIT_NOTIFY:
6094 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6095 state = KVM_STATE(current_accel());
6096 if (ctx_invalid ||
6097 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6098 warn_report("KVM internal error: Encountered a notify exit "
6099 "with invalid context in guest.");
6100 ret = -1;
6101 } else {
6102 warn_report_once("KVM: Encountered a notify exit with valid "
6103 "context in guest. "
6104 "The guest could be misbehaving.");
6105 ret = 0;
6106 }
6107 break;
6108 case KVM_EXIT_X86_RDMSR:
6109 /* We only enable MSR filtering, any other exit is bogus */
6110 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6111 ret = kvm_handle_rdmsr(cpu, run);
6112 break;
6113 case KVM_EXIT_X86_WRMSR:
6114 /* We only enable MSR filtering, any other exit is bogus */
6115 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6116 ret = kvm_handle_wrmsr(cpu, run);
6117 break;
6118 #ifdef CONFIG_XEN_EMU
6119 case KVM_EXIT_XEN:
6120 ret = kvm_xen_handle_exit(cpu, &run->xen);
6121 break;
6122 #endif
6123 case KVM_EXIT_HYPERCALL:
6124 ret = kvm_handle_hypercall(run);
6125 break;
6126 default:
6127 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6128 ret = -1;
6129 break;
6130 }
6131
6132 return ret;
6133 }
6134
kvm_arch_stop_on_emulation_error(CPUState * cs)6135 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6136 {
6137 X86CPU *cpu = X86_CPU(cs);
6138 CPUX86State *env = &cpu->env;
6139
6140 kvm_cpu_synchronize_state(cs);
6141 return !(env->cr[0] & CR0_PE_MASK) ||
6142 ((env->segs[R_CS].selector & 3) != 3);
6143 }
6144
kvm_arch_init_irq_routing(KVMState * s)6145 void kvm_arch_init_irq_routing(KVMState *s)
6146 {
6147 /* We know at this point that we're using the in-kernel
6148 * irqchip, so we can use irqfds, and on x86 we know
6149 * we can use msi via irqfd and GSI routing.
6150 */
6151 kvm_msi_via_irqfd_allowed = true;
6152 kvm_gsi_routing_allowed = true;
6153
6154 if (kvm_irqchip_is_split()) {
6155 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6156 int i;
6157
6158 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6159 MSI routes for signaling interrupts to the local apics. */
6160 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6161 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6162 error_report("Could not enable split IRQ mode.");
6163 exit(1);
6164 }
6165 }
6166 kvm_irqchip_commit_route_changes(&c);
6167 }
6168 }
6169
kvm_arch_irqchip_create(KVMState * s)6170 int kvm_arch_irqchip_create(KVMState *s)
6171 {
6172 int ret;
6173 if (kvm_kernel_irqchip_split()) {
6174 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6175 if (ret) {
6176 error_report("Could not enable split irqchip mode: %s",
6177 strerror(-ret));
6178 exit(1);
6179 } else {
6180 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6181 kvm_split_irqchip = true;
6182 return 1;
6183 }
6184 } else {
6185 return 0;
6186 }
6187 }
6188
kvm_swizzle_msi_ext_dest_id(uint64_t address)6189 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6190 {
6191 CPUX86State *env;
6192 uint64_t ext_id;
6193
6194 if (!first_cpu) {
6195 return address;
6196 }
6197 env = &X86_CPU(first_cpu)->env;
6198 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
6199 return address;
6200 }
6201
6202 /*
6203 * If the remappable format bit is set, or the upper bits are
6204 * already set in address_hi, or the low extended bits aren't
6205 * there anyway, do nothing.
6206 */
6207 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6208 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6209 return address;
6210 }
6211
6212 address &= ~ext_id;
6213 address |= ext_id << 35;
6214 return address;
6215 }
6216
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6217 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6218 uint64_t address, uint32_t data, PCIDevice *dev)
6219 {
6220 X86IOMMUState *iommu = x86_iommu_get_default();
6221
6222 if (iommu) {
6223 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6224
6225 if (class->int_remap) {
6226 int ret;
6227 MSIMessage src, dst;
6228
6229 src.address = route->u.msi.address_hi;
6230 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6231 src.address |= route->u.msi.address_lo;
6232 src.data = route->u.msi.data;
6233
6234 ret = class->int_remap(iommu, &src, &dst, dev ? \
6235 pci_requester_id(dev) : \
6236 X86_IOMMU_SID_INVALID);
6237 if (ret) {
6238 trace_kvm_x86_fixup_msi_error(route->gsi);
6239 return 1;
6240 }
6241
6242 /*
6243 * Handled untranslated compatibility format interrupt with
6244 * extended destination ID in the low bits 11-5. */
6245 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6246
6247 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6248 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6249 route->u.msi.data = dst.data;
6250 return 0;
6251 }
6252 }
6253
6254 #ifdef CONFIG_XEN_EMU
6255 if (xen_mode == XEN_EMULATE) {
6256 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6257
6258 /*
6259 * If it was a PIRQ and successfully routed (handled == 0) or it was
6260 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6261 */
6262 if (handled <= 0) {
6263 return handled;
6264 }
6265 }
6266 #endif
6267
6268 address = kvm_swizzle_msi_ext_dest_id(address);
6269 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6270 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6271 return 0;
6272 }
6273
6274 typedef struct MSIRouteEntry MSIRouteEntry;
6275
6276 struct MSIRouteEntry {
6277 PCIDevice *dev; /* Device pointer */
6278 int vector; /* MSI/MSIX vector index */
6279 int virq; /* Virtual IRQ index */
6280 QLIST_ENTRY(MSIRouteEntry) list;
6281 };
6282
6283 /* List of used GSI routes */
6284 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6285 QLIST_HEAD_INITIALIZER(msi_route_list);
6286
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6287 void kvm_update_msi_routes_all(void *private, bool global,
6288 uint32_t index, uint32_t mask)
6289 {
6290 int cnt = 0, vector;
6291 MSIRouteEntry *entry;
6292 MSIMessage msg;
6293 PCIDevice *dev;
6294
6295 /* TODO: explicit route update */
6296 QLIST_FOREACH(entry, &msi_route_list, list) {
6297 cnt++;
6298 vector = entry->vector;
6299 dev = entry->dev;
6300 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6301 msg = msix_get_message(dev, vector);
6302 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6303 msg = msi_get_message(dev, vector);
6304 } else {
6305 /*
6306 * Either MSI/MSIX is disabled for the device, or the
6307 * specific message was masked out. Skip this one.
6308 */
6309 continue;
6310 }
6311 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6312 }
6313 kvm_irqchip_commit_routes(kvm_state);
6314 trace_kvm_x86_update_msi_routes(cnt);
6315 }
6316
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6317 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6318 int vector, PCIDevice *dev)
6319 {
6320 static bool notify_list_inited = false;
6321 MSIRouteEntry *entry;
6322
6323 if (!dev) {
6324 /* These are (possibly) IOAPIC routes only used for split
6325 * kernel irqchip mode, while what we are housekeeping are
6326 * PCI devices only. */
6327 return 0;
6328 }
6329
6330 entry = g_new0(MSIRouteEntry, 1);
6331 entry->dev = dev;
6332 entry->vector = vector;
6333 entry->virq = route->gsi;
6334 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6335
6336 trace_kvm_x86_add_msi_route(route->gsi);
6337
6338 if (!notify_list_inited) {
6339 /* For the first time we do add route, add ourselves into
6340 * IOMMU's IEC notify list if needed. */
6341 X86IOMMUState *iommu = x86_iommu_get_default();
6342 if (iommu) {
6343 x86_iommu_iec_register_notifier(iommu,
6344 kvm_update_msi_routes_all,
6345 NULL);
6346 }
6347 notify_list_inited = true;
6348 }
6349 return 0;
6350 }
6351
kvm_arch_release_virq_post(int virq)6352 int kvm_arch_release_virq_post(int virq)
6353 {
6354 MSIRouteEntry *entry, *next;
6355 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6356 if (entry->virq == virq) {
6357 trace_kvm_x86_remove_msi_route(virq);
6358 QLIST_REMOVE(entry, list);
6359 g_free(entry);
6360 break;
6361 }
6362 }
6363 return 0;
6364 }
6365
kvm_arch_msi_data_to_gsi(uint32_t data)6366 int kvm_arch_msi_data_to_gsi(uint32_t data)
6367 {
6368 abort();
6369 }
6370
kvm_has_waitpkg(void)6371 bool kvm_has_waitpkg(void)
6372 {
6373 return has_msr_umwait;
6374 }
6375
6376 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6377
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6378 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6379 {
6380 KVMState *s = kvm_state;
6381 uint64_t supported;
6382
6383 mask &= XSTATE_DYNAMIC_MASK;
6384 if (!mask) {
6385 return;
6386 }
6387 /*
6388 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6389 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6390 * about them already because they are not supported features.
6391 */
6392 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6393 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6394 mask &= supported;
6395
6396 while (mask) {
6397 int bit = ctz64(mask);
6398 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6399 if (rc) {
6400 /*
6401 * Older kernel version (<5.17) do not support
6402 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6403 * any dynamic feature from kvm_arch_get_supported_cpuid.
6404 */
6405 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6406 "for feature bit %d", bit);
6407 }
6408 mask &= ~BIT_ULL(bit);
6409 }
6410 }
6411
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6412 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6413 {
6414 KVMState *s = KVM_STATE(obj);
6415 return s->notify_vmexit;
6416 }
6417
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6418 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6419 {
6420 KVMState *s = KVM_STATE(obj);
6421
6422 if (s->fd != -1) {
6423 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6424 return;
6425 }
6426
6427 s->notify_vmexit = value;
6428 }
6429
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6430 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6431 const char *name, void *opaque,
6432 Error **errp)
6433 {
6434 KVMState *s = KVM_STATE(obj);
6435 uint32_t value = s->notify_window;
6436
6437 visit_type_uint32(v, name, &value, errp);
6438 }
6439
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6440 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6441 const char *name, void *opaque,
6442 Error **errp)
6443 {
6444 KVMState *s = KVM_STATE(obj);
6445 uint32_t value;
6446
6447 if (s->fd != -1) {
6448 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6449 return;
6450 }
6451
6452 if (!visit_type_uint32(v, name, &value, errp)) {
6453 return;
6454 }
6455
6456 s->notify_window = value;
6457 }
6458
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6459 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6460 const char *name, void *opaque,
6461 Error **errp)
6462 {
6463 KVMState *s = KVM_STATE(obj);
6464 uint32_t value = s->xen_version;
6465
6466 visit_type_uint32(v, name, &value, errp);
6467 }
6468
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6469 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6470 const char *name, void *opaque,
6471 Error **errp)
6472 {
6473 KVMState *s = KVM_STATE(obj);
6474 Error *error = NULL;
6475 uint32_t value;
6476
6477 visit_type_uint32(v, name, &value, &error);
6478 if (error) {
6479 error_propagate(errp, error);
6480 return;
6481 }
6482
6483 s->xen_version = value;
6484 if (value && xen_mode == XEN_DISABLED) {
6485 xen_mode = XEN_EMULATE;
6486 }
6487 }
6488
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6489 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6490 const char *name, void *opaque,
6491 Error **errp)
6492 {
6493 KVMState *s = KVM_STATE(obj);
6494 uint16_t value = s->xen_gnttab_max_frames;
6495
6496 visit_type_uint16(v, name, &value, errp);
6497 }
6498
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6499 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6500 const char *name, void *opaque,
6501 Error **errp)
6502 {
6503 KVMState *s = KVM_STATE(obj);
6504 Error *error = NULL;
6505 uint16_t value;
6506
6507 visit_type_uint16(v, name, &value, &error);
6508 if (error) {
6509 error_propagate(errp, error);
6510 return;
6511 }
6512
6513 s->xen_gnttab_max_frames = value;
6514 }
6515
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6516 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6517 const char *name, void *opaque,
6518 Error **errp)
6519 {
6520 KVMState *s = KVM_STATE(obj);
6521 uint16_t value = s->xen_evtchn_max_pirq;
6522
6523 visit_type_uint16(v, name, &value, errp);
6524 }
6525
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6526 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6527 const char *name, void *opaque,
6528 Error **errp)
6529 {
6530 KVMState *s = KVM_STATE(obj);
6531 Error *error = NULL;
6532 uint16_t value;
6533
6534 visit_type_uint16(v, name, &value, &error);
6535 if (error) {
6536 error_propagate(errp, error);
6537 return;
6538 }
6539
6540 s->xen_evtchn_max_pirq = value;
6541 }
6542
kvm_arch_accel_class_init(ObjectClass * oc)6543 void kvm_arch_accel_class_init(ObjectClass *oc)
6544 {
6545 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6546 &NotifyVmexitOption_lookup,
6547 kvm_arch_get_notify_vmexit,
6548 kvm_arch_set_notify_vmexit);
6549 object_class_property_set_description(oc, "notify-vmexit",
6550 "Enable notify VM exit");
6551
6552 object_class_property_add(oc, "notify-window", "uint32",
6553 kvm_arch_get_notify_window,
6554 kvm_arch_set_notify_window,
6555 NULL, NULL);
6556 object_class_property_set_description(oc, "notify-window",
6557 "Clock cycles without an event window "
6558 "after which a notification VM exit occurs");
6559
6560 object_class_property_add(oc, "xen-version", "uint32",
6561 kvm_arch_get_xen_version,
6562 kvm_arch_set_xen_version,
6563 NULL, NULL);
6564 object_class_property_set_description(oc, "xen-version",
6565 "Xen version to be emulated "
6566 "(in XENVER_version form "
6567 "e.g. 0x4000a for 4.10)");
6568
6569 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6570 kvm_arch_get_xen_gnttab_max_frames,
6571 kvm_arch_set_xen_gnttab_max_frames,
6572 NULL, NULL);
6573 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6574 "Maximum number of grant table frames");
6575
6576 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6577 kvm_arch_get_xen_evtchn_max_pirq,
6578 kvm_arch_set_xen_evtchn_max_pirq,
6579 NULL, NULL);
6580 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6581 "Maximum number of Xen PIRQs");
6582 }
6583
kvm_set_max_apic_id(uint32_t max_apic_id)6584 void kvm_set_max_apic_id(uint32_t max_apic_id)
6585 {
6586 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6587 }
6588