1 /* 2 * Arm MPS3 board emulation for Cortex-R-based FPGA images. 3 * (For M-profile images see mps2.c and mps2tz.c.) 4 * 5 * Copyright (c) 2017 Linaro Limited 6 * Written by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 or 10 * (at your option) any later version. 11 */ 12 13 /* 14 * The MPS3 is an FPGA based dev board. This file handles FPGA images 15 * which use the Cortex-R CPUs. We model these separately from the 16 * M-profile images, because on M-profile the FPGA image is based on 17 * a "Subsystem for Embedded" which is similar to an SoC, whereas 18 * the R-profile FPGA images don't have that abstraction layer. 19 * 20 * We model the following FPGA images here: 21 * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536 22 * 23 * Application Note AN536: 24 * https://developer.arm.com/documentation/dai0536/latest/ 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qapi/error.h" 30 #include "qobject/qlist.h" 31 #include "system/address-spaces.h" 32 #include "cpu.h" 33 #include "system/system.h" 34 #include "hw/boards.h" 35 #include "hw/or-irq.h" 36 #include "hw/qdev-clock.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/bsa.h" 40 #include "hw/arm/machines-qom.h" 41 #include "hw/char/cmsdk-apb-uart.h" 42 #include "hw/i2c/arm_sbcon_i2c.h" 43 #include "hw/intc/arm_gicv3.h" 44 #include "hw/misc/mps2-scc.h" 45 #include "hw/misc/mps2-fpgaio.h" 46 #include "hw/misc/unimp.h" 47 #include "hw/net/lan9118.h" 48 #include "hw/rtc/pl031.h" 49 #include "hw/ssi/pl022.h" 50 #include "hw/timer/cmsdk-apb-dualtimer.h" 51 #include "hw/watchdog/cmsdk-apb-watchdog.h" 52 53 /* Define the layout of RAM and ROM in a board */ 54 typedef struct RAMInfo { 55 const char *name; 56 hwaddr base; 57 hwaddr size; 58 int mrindex; /* index into rams[]; -1 for the system RAM block */ 59 int flags; 60 } RAMInfo; 61 62 /* 63 * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit 64 * emulation of that much guest RAM, so artificially make it smaller. 65 */ 66 #if HOST_LONG_BITS == 32 67 #define MPS3_DDR_SIZE (1 * GiB) 68 #else 69 #define MPS3_DDR_SIZE (3 * GiB) 70 #endif 71 72 /* 73 * Flag values: 74 * IS_MAIN: this is the main machine RAM 75 * IS_ROM: this area is read-only 76 */ 77 #define IS_MAIN 1 78 #define IS_ROM 2 79 80 #define MPS3R_RAM_MAX 9 81 #define MPS3R_CPU_MAX 2 82 #define MPS3R_UART_MAX 4 /* shared UART count */ 83 84 #define PERIPHBASE 0xf0000000 85 #define NUM_SPIS 96 86 87 typedef enum MPS3RFPGAType { 88 FPGA_AN536, 89 } MPS3RFPGAType; 90 91 struct MPS3RMachineClass { 92 MachineClass parent; 93 MPS3RFPGAType fpga_type; 94 const RAMInfo *raminfo; 95 hwaddr loader_start; 96 }; 97 98 struct MPS3RMachineState { 99 MachineState parent; 100 struct arm_boot_info bootinfo; 101 MemoryRegion ram[MPS3R_RAM_MAX]; 102 Object *cpu[MPS3R_CPU_MAX]; 103 MemoryRegion cpu_sysmem[MPS3R_CPU_MAX]; 104 MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; 105 MemoryRegion cpu_ram[MPS3R_CPU_MAX]; 106 GICv3State gic; 107 /* per-CPU UARTs followed by the shared UARTs */ 108 CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; 109 OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; 110 OrIRQState uart_oflow; 111 CMSDKAPBWatchdog watchdog; 112 CMSDKAPBDualTimer dualtimer; 113 ArmSbconI2CState i2c[5]; 114 PL022State spi[3]; 115 MPS2SCC scc; 116 MPS2FPGAIO fpgaio; 117 UnimplementedDeviceState i2s_audio; 118 PL031State rtc; 119 Clock *clk; 120 }; 121 122 #define TYPE_MPS3R_MACHINE "mps3r" 123 #define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536") 124 125 OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) 126 127 /* 128 * Main clock frequency CLK in Hz (50MHz). In the image there are also 129 * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our 130 * model we just roll them all into one. 131 */ 132 #define CLK_FRQ 50000000 133 134 static const RAMInfo an536_raminfo[] = { 135 { 136 .name = "ATCM", 137 .base = 0x00000000, 138 .size = 0x00008000, 139 .mrindex = 0, 140 }, { 141 /* We model the QSPI flash as simple ROM for now */ 142 .name = "QSPI", 143 .base = 0x08000000, 144 .size = 0x00800000, 145 .flags = IS_ROM, 146 .mrindex = 1, 147 }, { 148 .name = "BRAM", 149 .base = 0x10000000, 150 .size = 0x00080000, 151 .mrindex = 2, 152 }, { 153 .name = "DDR", 154 .base = 0x20000000, 155 .size = MPS3_DDR_SIZE, 156 .mrindex = -1, 157 }, { 158 .name = "ATCM0", 159 .base = 0xee000000, 160 .size = 0x00008000, 161 .mrindex = 3, 162 }, { 163 .name = "BTCM0", 164 .base = 0xee100000, 165 .size = 0x00008000, 166 .mrindex = 4, 167 }, { 168 .name = "CTCM0", 169 .base = 0xee200000, 170 .size = 0x00008000, 171 .mrindex = 5, 172 }, { 173 .name = "ATCM1", 174 .base = 0xee400000, 175 .size = 0x00008000, 176 .mrindex = 6, 177 }, { 178 .name = "BTCM1", 179 .base = 0xee500000, 180 .size = 0x00008000, 181 .mrindex = 7, 182 }, { 183 .name = "CTCM1", 184 .base = 0xee600000, 185 .size = 0x00008000, 186 .mrindex = 8, 187 }, { 188 .name = NULL, 189 } 190 }; 191 192 static const int an536_oscclk[] = { 193 24000000, /* 24MHz reference for RTC and timers */ 194 50000000, /* 50MHz ACLK */ 195 50000000, /* 50MHz MCLK */ 196 50000000, /* 50MHz GPUCLK */ 197 24576000, /* 24.576MHz AUDCLK */ 198 23750000, /* 23.75MHz HDLCDCLK */ 199 100000000, /* 100MHz DDR4_REF_CLK */ 200 }; 201 202 static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, 203 const RAMInfo *raminfo) 204 { 205 /* Return an initialized MemoryRegion for the RAMInfo. */ 206 MemoryRegion *ram; 207 208 if (raminfo->mrindex < 0) { 209 /* Means this RAMInfo is for QEMU's "system memory" */ 210 MachineState *machine = MACHINE(mms); 211 assert(!(raminfo->flags & IS_ROM)); 212 return machine->ram; 213 } 214 215 assert(raminfo->mrindex < MPS3R_RAM_MAX); 216 ram = &mms->ram[raminfo->mrindex]; 217 218 memory_region_init_ram(ram, NULL, raminfo->name, 219 raminfo->size, &error_fatal); 220 if (raminfo->flags & IS_ROM) { 221 memory_region_set_readonly(ram, true); 222 } 223 return ram; 224 } 225 226 /* 227 * There is no defined secondary boot protocol for Linux for the AN536, 228 * because real hardware has a restriction that atomic operations between 229 * the two CPUs do not function correctly, and so true SMP is not 230 * possible. Therefore for cases where the user is directly booting 231 * a kernel, we treat the system as essentially uniprocessor, and 232 * put the secondary CPU into power-off state (as if the user on the 233 * real hardware had configured the secondary to be halted via the 234 * SCC config registers). 235 * 236 * Note that the default secondary boot code would not work here anyway 237 * as it assumes a GICv2, and we have a GICv3. 238 */ 239 static void mps3r_write_secondary_boot(ARMCPU *cpu, 240 const struct arm_boot_info *info) 241 { 242 /* 243 * Power the secondary CPU off. This means we don't need to write any 244 * boot code into guest memory. Note that the 'cpu' argument to this 245 * function is the primary CPU we passed to arm_load_kernel(), not 246 * the secondary. Loop around all the other CPUs, as the boot.c 247 * code does for the "disable secondaries if PSCI is enabled" case. 248 */ 249 for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 250 if (cs != first_cpu) { 251 object_property_set_bool(OBJECT(cs), "start-powered-off", true, 252 &error_abort); 253 } 254 } 255 } 256 257 static void mps3r_secondary_cpu_reset(ARMCPU *cpu, 258 const struct arm_boot_info *info) 259 { 260 /* We don't need to do anything here because the CPU will be off */ 261 } 262 263 static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) 264 { 265 MachineState *machine = MACHINE(mms); 266 DeviceState *gicdev; 267 QList *redist_region_count; 268 269 object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3); 270 gicdev = DEVICE(&mms->gic); 271 qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); 272 qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); 273 redist_region_count = qlist_new(); 274 qlist_append_int(redist_region_count, machine->smp.cpus); 275 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 276 object_property_set_link(OBJECT(&mms->gic), "sysmem", 277 OBJECT(sysmem), &error_fatal); 278 sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal); 279 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE); 280 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000); 281 /* 282 * Wire the outputs from each CPU's generic timer and the GICv3 283 * maintenance interrupt signal to the appropriate GIC PPI inputs, 284 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 285 */ 286 for (int i = 0; i < machine->smp.cpus; i++) { 287 DeviceState *cpudev = DEVICE(mms->cpu[i]); 288 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic); 289 int intidbase = NUM_SPIS + i * GIC_INTERNAL; 290 int irq; 291 /* 292 * Mapping from the output timer irq lines from the CPU to the 293 * GIC PPI inputs used for this board. This isn't a BSA board, 294 * but it uses the standard convention for the PPI numbers. 295 */ 296 const int timer_irq[] = { 297 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 298 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 299 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 300 }; 301 302 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 303 qdev_connect_gpio_out(cpudev, irq, 304 qdev_get_gpio_in(gicdev, 305 intidbase + timer_irq[irq])); 306 } 307 308 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 309 qdev_get_gpio_in(gicdev, 310 intidbase + ARCH_GIC_MAINT_IRQ)); 311 312 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 313 qdev_get_gpio_in(gicdev, 314 intidbase + VIRTUAL_PMU_IRQ)); 315 316 sysbus_connect_irq(gicsbd, i, 317 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 318 sysbus_connect_irq(gicsbd, i + machine->smp.cpus, 319 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 320 sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus, 321 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 322 sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus, 323 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 324 } 325 } 326 327 /* 328 * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr. 329 * The qemu_irq arguments are where we connect the various IRQs from the UART. 330 */ 331 static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem, 332 hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq, 333 qemu_irq txoverirq, qemu_irq rxoverirq, 334 qemu_irq combirq) 335 { 336 g_autofree char *s = g_strdup_printf("uart%d", uartno); 337 SysBusDevice *sbd; 338 339 assert(uartno < ARRAY_SIZE(mms->uart)); 340 object_initialize_child(OBJECT(mms), s, &mms->uart[uartno], 341 TYPE_CMSDK_APB_UART); 342 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); 343 qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno)); 344 sbd = SYS_BUS_DEVICE(&mms->uart[uartno]); 345 sysbus_realize(sbd, &error_fatal); 346 memory_region_add_subregion(mem, baseaddr, 347 sysbus_mmio_get_region(sbd, 0)); 348 sysbus_connect_irq(sbd, 0, txirq); 349 sysbus_connect_irq(sbd, 1, rxirq); 350 sysbus_connect_irq(sbd, 2, txoverirq); 351 sysbus_connect_irq(sbd, 3, rxoverirq); 352 sysbus_connect_irq(sbd, 4, combirq); 353 } 354 355 static void mps3r_common_init(MachineState *machine) 356 { 357 MPS3RMachineState *mms = MPS3R_MACHINE(machine); 358 MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); 359 MemoryRegion *sysmem = get_system_memory(); 360 DeviceState *gicdev; 361 QList *oscclk; 362 363 mms->clk = clock_new(OBJECT(machine), "CLK"); 364 clock_set_hz(mms->clk, CLK_FRQ); 365 366 for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { 367 MemoryRegion *mr = mr_for_raminfo(mms, ri); 368 memory_region_add_subregion(sysmem, ri->base, mr); 369 } 370 371 assert(machine->smp.cpus <= MPS3R_CPU_MAX); 372 for (int i = 0; i < machine->smp.cpus; i++) { 373 g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i); 374 g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i); 375 g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i); 376 377 /* 378 * Each CPU has some private RAM/peripherals, so create the container 379 * which will house those, with the whole-machine system memory being 380 * used where there's no CPU-specific device. Note that we need the 381 * sysmem_alias aliases because we can't put one MR (the original 382 * 'sysmem') into more than one other MR. 383 */ 384 memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine), 385 sysmem_name, UINT64_MAX); 386 memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine), 387 alias_name, sysmem, 0, UINT64_MAX); 388 memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0, 389 &mms->sysmem_alias[i], -1); 390 391 mms->cpu[i] = object_new(machine->cpu_type); 392 object_property_set_link(mms->cpu[i], "memory", 393 OBJECT(&mms->cpu_sysmem[i]), &error_abort); 394 object_property_set_int(mms->cpu[i], "reset-cbar", 395 PERIPHBASE, &error_abort); 396 qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal); 397 object_unref(mms->cpu[i]); 398 399 /* Per-CPU RAM */ 400 memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname, 401 0x1000, &error_fatal); 402 memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000, 403 &mms->cpu_ram[i]); 404 } 405 406 create_gic(mms, sysmem); 407 gicdev = DEVICE(&mms->gic); 408 409 /* 410 * UARTs 0 and 1 are per-CPU; their interrupts are wired to 411 * the relevant CPU's PPI 0..3, aka INTID 16..19 412 */ 413 for (int i = 0; i < machine->smp.cpus; i++) { 414 int intidbase = NUM_SPIS + i * GIC_INTERNAL; 415 g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i); 416 DeviceState *orgate; 417 418 /* The two overflow IRQs from the UART are ORed together into PPI 3 */ 419 object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i], 420 TYPE_OR_IRQ); 421 orgate = DEVICE(&mms->cpu_uart_oflow[i]); 422 qdev_prop_set_uint32(orgate, "num-lines", 2); 423 qdev_realize(orgate, NULL, &error_fatal); 424 qdev_connect_gpio_out(orgate, 0, 425 qdev_get_gpio_in(gicdev, intidbase + 19)); 426 427 create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000, 428 qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */ 429 qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */ 430 qdev_get_gpio_in(orgate, 0), /* txover */ 431 qdev_get_gpio_in(orgate, 1), /* rxover */ 432 qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */); 433 } 434 /* 435 * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed 436 * together into IRQ 17 437 */ 438 object_initialize_child(OBJECT(mms), "uart-oflow-orgate", 439 &mms->uart_oflow, TYPE_OR_IRQ); 440 qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", 441 MPS3R_UART_MAX * 2); 442 qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal); 443 qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0, 444 qdev_get_gpio_in(gicdev, 17)); 445 446 for (int i = 0; i < MPS3R_UART_MAX; i++) { 447 hwaddr baseaddr = 0xe0205000 + i * 0x1000; 448 int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i; 449 450 create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr, 451 qdev_get_gpio_in(gicdev, txirq), 452 qdev_get_gpio_in(gicdev, rxirq), 453 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2), 454 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1), 455 qdev_get_gpio_in(gicdev, combirq)); 456 } 457 458 for (int i = 0; i < 4; i++) { 459 /* CMSDK GPIO controllers */ 460 g_autofree char *s = g_strdup_printf("gpio%d", i); 461 create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000); 462 } 463 464 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, 465 TYPE_CMSDK_APB_WATCHDOG); 466 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); 467 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); 468 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, 469 qdev_get_gpio_in(gicdev, 0)); 470 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000); 471 472 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, 473 TYPE_CMSDK_APB_DUALTIMER); 474 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); 475 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); 476 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, 477 qdev_get_gpio_in(gicdev, 3)); 478 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1, 479 qdev_get_gpio_in(gicdev, 1)); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2, 481 qdev_get_gpio_in(gicdev, 2)); 482 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000); 483 484 for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) { 485 static const hwaddr i2cbase[] = {0xe0102000, /* Touch */ 486 0xe0103000, /* Audio */ 487 0xe0107000, /* Shield0 */ 488 0xe0108000, /* Shield1 */ 489 0xe0109000}; /* DDR4 EEPROM */ 490 g_autofree char *s = g_strdup_printf("i2c%d", i); 491 492 object_initialize_child(OBJECT(mms), s, &mms->i2c[i], 493 TYPE_ARM_SBCON_I2C); 494 sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal); 495 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]); 496 if (i != 2 && i != 3) { 497 /* 498 * internal-only bus: mark it full to avoid user-created 499 * i2c devices being plugged into it. 500 */ 501 qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c")); 502 } 503 } 504 505 for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) { 506 g_autofree char *s = g_strdup_printf("spi%d", i); 507 hwaddr baseaddr = 0xe0104000 + i * 0x1000; 508 509 object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022); 510 sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal); 511 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr); 512 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0, 513 qdev_get_gpio_in(gicdev, 22 + i)); 514 } 515 516 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); 517 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0); 518 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2); 519 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008); 520 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360); 521 oscclk = qlist_new(); 522 for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) { 523 qlist_append_int(oscclk, an536_oscclk[i]); 524 } 525 qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk); 526 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); 527 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000); 528 529 create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000); 530 531 object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio, 532 TYPE_MPS2_FPGAIO); 533 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]); 534 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10); 535 qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true); 536 qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false); 537 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); 538 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000); 539 540 create_unimplemented_device("clcd", 0xe0209000, 0x1000); 541 542 object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031); 543 sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal); 544 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000); 545 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0, 546 qdev_get_gpio_in(gicdev, 4)); 547 548 /* 549 * In hardware this is a LAN9220; the LAN9118 is software compatible 550 * except that it doesn't support the checksum-offload feature. 551 */ 552 lan9118_init(0xe0300000, 553 qdev_get_gpio_in(gicdev, 18)); 554 555 create_unimplemented_device("usb", 0xe0301000, 0x1000); 556 create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000); 557 558 mms->bootinfo.ram_size = machine->ram_size; 559 mms->bootinfo.board_id = -1; 560 mms->bootinfo.loader_start = mmc->loader_start; 561 mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot; 562 mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset; 563 arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo); 564 } 565 566 static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) 567 { 568 /* 569 * Set mc->default_ram_size and default_ram_id from the 570 * information in mmc->raminfo. 571 */ 572 MachineClass *mc = MACHINE_CLASS(mmc); 573 const RAMInfo *p; 574 575 for (p = mmc->raminfo; p->name; p++) { 576 if (p->mrindex < 0) { 577 /* Found the entry for "system memory" */ 578 mc->default_ram_size = p->size; 579 mc->default_ram_id = p->name; 580 mmc->loader_start = p->base; 581 return; 582 } 583 } 584 g_assert_not_reached(); 585 } 586 587 static void mps3r_class_init(ObjectClass *oc, const void *data) 588 { 589 MachineClass *mc = MACHINE_CLASS(oc); 590 591 mc->init = mps3r_common_init; 592 } 593 594 static void mps3r_an536_class_init(ObjectClass *oc, const void *data) 595 { 596 MachineClass *mc = MACHINE_CLASS(oc); 597 MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc); 598 static const char * const valid_cpu_types[] = { 599 ARM_CPU_TYPE_NAME("cortex-r52"), 600 NULL 601 }; 602 603 mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; 604 /* 605 * In the real FPGA image there are always two cores, but the standard 606 * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning 607 * that the second core is held in reset and halted. Many images built for 608 * the board do not expect the second core to run at startup (especially 609 * since on the real FPGA image it is not possible to use LDREX/STREX 610 * in RAM between the two cores, so a true SMP setup isn't supported). 611 * 612 * As QEMU's equivalent of this, we support both -smp 1 and -smp 2, 613 * with the default being -smp 1. This seems a more intuitive UI for 614 * QEMU users than, for instance, having a machine property to allow 615 * the user to set the initial value of the SYSCON 0x000 register. 616 */ 617 mc->default_cpus = 1; 618 mc->min_cpus = 1; 619 mc->max_cpus = 2; 620 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); 621 mc->valid_cpu_types = valid_cpu_types; 622 mmc->raminfo = an536_raminfo; 623 mps3r_set_default_ram_info(mmc); 624 } 625 626 static const TypeInfo mps3r_machine_types[] = { 627 { 628 .name = TYPE_MPS3R_MACHINE, 629 .parent = TYPE_MACHINE, 630 .abstract = true, 631 .instance_size = sizeof(MPS3RMachineState), 632 .class_size = sizeof(MPS3RMachineClass), 633 .class_init = mps3r_class_init, 634 }, { 635 .name = TYPE_MPS3R_AN536_MACHINE, 636 .parent = TYPE_MPS3R_MACHINE, 637 .class_init = mps3r_an536_class_init, 638 .interfaces = arm_machine_interfaces, 639 }, 640 }; 641 642 DEFINE_TYPES(mps3r_machine_types); 643