xref: /openbmc/linux/arch/arm64/boot/dts/qcom/msm8916.dtsi (revision ebd09d81)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/arm/coresight-cti-dt.h>
7#include <dt-bindings/clock/qcom,gcc-msm8916.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/interconnect/qcom,msm8916.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/reset/qcom,gcc-msm8916.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&intc>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	memory@80000000 {
24		device_type = "memory";
25		/* We expect the bootloader to fill in the reg */
26		reg = <0 0x80000000 0 0>;
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		tz-apps@86000000 {
35			reg = <0x0 0x86000000 0x0 0x300000>;
36			no-map;
37		};
38
39		smem@86300000 {
40			compatible = "qcom,smem";
41			reg = <0x0 0x86300000 0x0 0x100000>;
42			no-map;
43
44			hwlocks = <&tcsr_mutex 3>;
45			qcom,rpm-msg-ram = <&rpm_msg_ram>;
46		};
47
48		hypervisor@86400000 {
49			reg = <0x0 0x86400000 0x0 0x100000>;
50			no-map;
51		};
52
53		tz@86500000 {
54			reg = <0x0 0x86500000 0x0 0x180000>;
55			no-map;
56		};
57
58		reserved@86680000 {
59			reg = <0x0 0x86680000 0x0 0x80000>;
60			no-map;
61		};
62
63		rmtfs@86700000 {
64			compatible = "qcom,rmtfs-mem";
65			reg = <0x0 0x86700000 0x0 0xe0000>;
66			no-map;
67
68			qcom,client-id = <1>;
69		};
70
71		rfsa@867e0000 {
72			reg = <0x0 0x867e0000 0x0 0x20000>;
73			no-map;
74		};
75
76		mpss_mem: mpss@86800000 {
77			reg = <0x0 0x86800000 0x0 0x2b00000>;
78			no-map;
79		};
80
81		wcnss_mem: wcnss@89300000 {
82			reg = <0x0 0x89300000 0x0 0x600000>;
83			no-map;
84		};
85
86		venus_mem: venus@89900000 {
87			reg = <0x0 0x89900000 0x0 0x600000>;
88			no-map;
89		};
90
91		mba_mem: mba@8ea00000 {
92			no-map;
93			reg = <0 0x8ea00000 0 0x100000>;
94		};
95	};
96
97	clocks {
98		xo_board: xo-board {
99			compatible = "fixed-clock";
100			#clock-cells = <0>;
101			clock-frequency = <19200000>;
102		};
103
104		sleep_clk: sleep-clk {
105			compatible = "fixed-clock";
106			#clock-cells = <0>;
107			clock-frequency = <32768>;
108		};
109	};
110
111	cpus {
112		#address-cells = <1>;
113		#size-cells = <0>;
114
115		CPU0: cpu@0 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a53";
118			reg = <0x0>;
119			next-level-cache = <&L2_0>;
120			enable-method = "psci";
121			clocks = <&apcs>;
122			operating-points-v2 = <&cpu_opp_table>;
123			#cooling-cells = <2>;
124			power-domains = <&CPU_PD0>;
125			power-domain-names = "psci";
126			qcom,acc = <&cpu0_acc>;
127			qcom,saw = <&cpu0_saw>;
128		};
129
130		CPU1: cpu@1 {
131			device_type = "cpu";
132			compatible = "arm,cortex-a53";
133			reg = <0x1>;
134			next-level-cache = <&L2_0>;
135			enable-method = "psci";
136			clocks = <&apcs>;
137			operating-points-v2 = <&cpu_opp_table>;
138			#cooling-cells = <2>;
139			power-domains = <&CPU_PD1>;
140			power-domain-names = "psci";
141			qcom,acc = <&cpu1_acc>;
142			qcom,saw = <&cpu1_saw>;
143		};
144
145		CPU2: cpu@2 {
146			device_type = "cpu";
147			compatible = "arm,cortex-a53";
148			reg = <0x2>;
149			next-level-cache = <&L2_0>;
150			enable-method = "psci";
151			clocks = <&apcs>;
152			operating-points-v2 = <&cpu_opp_table>;
153			#cooling-cells = <2>;
154			power-domains = <&CPU_PD2>;
155			power-domain-names = "psci";
156			qcom,acc = <&cpu2_acc>;
157			qcom,saw = <&cpu2_saw>;
158		};
159
160		CPU3: cpu@3 {
161			device_type = "cpu";
162			compatible = "arm,cortex-a53";
163			reg = <0x3>;
164			next-level-cache = <&L2_0>;
165			enable-method = "psci";
166			clocks = <&apcs>;
167			operating-points-v2 = <&cpu_opp_table>;
168			#cooling-cells = <2>;
169			power-domains = <&CPU_PD3>;
170			power-domain-names = "psci";
171			qcom,acc = <&cpu3_acc>;
172			qcom,saw = <&cpu3_saw>;
173		};
174
175		L2_0: l2-cache {
176			compatible = "cache";
177			cache-level = <2>;
178			cache-unified;
179		};
180
181		idle-states {
182			entry-method = "psci";
183
184			CPU_SLEEP_0: cpu-sleep-0 {
185				compatible = "arm,idle-state";
186				idle-state-name = "standalone-power-collapse";
187				arm,psci-suspend-param = <0x40000002>;
188				entry-latency-us = <130>;
189				exit-latency-us = <150>;
190				min-residency-us = <2000>;
191				local-timer-stop;
192			};
193		};
194
195		domain-idle-states {
196
197			CLUSTER_RET: cluster-retention {
198				compatible = "domain-idle-state";
199				arm,psci-suspend-param = <0x41000012>;
200				entry-latency-us = <500>;
201				exit-latency-us = <500>;
202				min-residency-us = <2000>;
203			};
204
205			CLUSTER_PWRDN: cluster-gdhs {
206				compatible = "domain-idle-state";
207				arm,psci-suspend-param = <0x41000032>;
208				entry-latency-us = <2000>;
209				exit-latency-us = <2000>;
210				min-residency-us = <6000>;
211			};
212		};
213	};
214
215	cpu_opp_table: opp-table-cpu {
216		compatible = "operating-points-v2";
217		opp-shared;
218
219		opp-200000000 {
220			opp-hz = /bits/ 64 <200000000>;
221		};
222		opp-400000000 {
223			opp-hz = /bits/ 64 <400000000>;
224		};
225		opp-800000000 {
226			opp-hz = /bits/ 64 <800000000>;
227		};
228		opp-998400000 {
229			opp-hz = /bits/ 64 <998400000>;
230		};
231	};
232
233	firmware {
234		scm: scm {
235			compatible = "qcom,scm-msm8916", "qcom,scm";
236			clocks = <&gcc GCC_CRYPTO_CLK>,
237				 <&gcc GCC_CRYPTO_AXI_CLK>,
238				 <&gcc GCC_CRYPTO_AHB_CLK>;
239			clock-names = "core", "bus", "iface";
240			#reset-cells = <1>;
241
242			qcom,dload-mode = <&tcsr 0x6100>;
243		};
244	};
245
246	pmu {
247		compatible = "arm,cortex-a53-pmu";
248		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
249	};
250
251	psci {
252		compatible = "arm,psci-1.0";
253		method = "smc";
254
255		CPU_PD0: power-domain-cpu0 {
256			#power-domain-cells = <0>;
257			power-domains = <&CLUSTER_PD>;
258			domain-idle-states = <&CPU_SLEEP_0>;
259		};
260
261		CPU_PD1: power-domain-cpu1 {
262			#power-domain-cells = <0>;
263			power-domains = <&CLUSTER_PD>;
264			domain-idle-states = <&CPU_SLEEP_0>;
265		};
266
267		CPU_PD2: power-domain-cpu2 {
268			#power-domain-cells = <0>;
269			power-domains = <&CLUSTER_PD>;
270			domain-idle-states = <&CPU_SLEEP_0>;
271		};
272
273		CPU_PD3: power-domain-cpu3 {
274			#power-domain-cells = <0>;
275			power-domains = <&CLUSTER_PD>;
276			domain-idle-states = <&CPU_SLEEP_0>;
277		};
278
279		CLUSTER_PD: power-domain-cluster {
280			#power-domain-cells = <0>;
281			domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
282		};
283	};
284
285	rpm: remoteproc {
286		compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
287
288		smd-edge {
289			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
290			qcom,ipc = <&apcs 8 0>;
291			qcom,smd-edge = <15>;
292
293			rpm_requests: rpm-requests {
294				compatible = "qcom,rpm-msm8916";
295				qcom,smd-channels = "rpm_requests";
296
297				rpmcc: clock-controller {
298					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
299					#clock-cells = <1>;
300					clocks = <&xo_board>;
301					clock-names = "xo";
302				};
303
304				rpmpd: power-controller {
305					compatible = "qcom,msm8916-rpmpd";
306					#power-domain-cells = <1>;
307					operating-points-v2 = <&rpmpd_opp_table>;
308
309					rpmpd_opp_table: opp-table {
310						compatible = "operating-points-v2";
311
312						rpmpd_opp_ret: opp1 {
313							opp-level = <1>;
314						};
315						rpmpd_opp_svs_krait: opp2 {
316							opp-level = <2>;
317						};
318						rpmpd_opp_svs_soc: opp3 {
319							opp-level = <3>;
320						};
321						rpmpd_opp_nom: opp4 {
322							opp-level = <4>;
323						};
324						rpmpd_opp_turbo: opp5 {
325							opp-level = <5>;
326						};
327						rpmpd_opp_super_turbo: opp6 {
328							opp-level = <6>;
329						};
330					};
331				};
332			};
333		};
334	};
335
336	smp2p-hexagon {
337		compatible = "qcom,smp2p";
338		qcom,smem = <435>, <428>;
339
340		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
341
342		qcom,ipc = <&apcs 8 14>;
343
344		qcom,local-pid = <0>;
345		qcom,remote-pid = <1>;
346
347		hexagon_smp2p_out: master-kernel {
348			qcom,entry-name = "master-kernel";
349
350			#qcom,smem-state-cells = <1>;
351		};
352
353		hexagon_smp2p_in: slave-kernel {
354			qcom,entry-name = "slave-kernel";
355
356			interrupt-controller;
357			#interrupt-cells = <2>;
358		};
359	};
360
361	smp2p-wcnss {
362		compatible = "qcom,smp2p";
363		qcom,smem = <451>, <431>;
364
365		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
366
367		qcom,ipc = <&apcs 8 18>;
368
369		qcom,local-pid = <0>;
370		qcom,remote-pid = <4>;
371
372		wcnss_smp2p_out: master-kernel {
373			qcom,entry-name = "master-kernel";
374
375			#qcom,smem-state-cells = <1>;
376		};
377
378		wcnss_smp2p_in: slave-kernel {
379			qcom,entry-name = "slave-kernel";
380
381			interrupt-controller;
382			#interrupt-cells = <2>;
383		};
384	};
385
386	smsm {
387		compatible = "qcom,smsm";
388
389		#address-cells = <1>;
390		#size-cells = <0>;
391
392		qcom,ipc-1 = <&apcs 8 13>;
393		qcom,ipc-3 = <&apcs 8 19>;
394
395		apps_smsm: apps@0 {
396			reg = <0>;
397
398			#qcom,smem-state-cells = <1>;
399		};
400
401		hexagon_smsm: hexagon@1 {
402			reg = <1>;
403			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
404
405			interrupt-controller;
406			#interrupt-cells = <2>;
407		};
408
409		wcnss_smsm: wcnss@6 {
410			reg = <6>;
411			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
412
413			interrupt-controller;
414			#interrupt-cells = <2>;
415		};
416	};
417
418	soc: soc@0 {
419		#address-cells = <1>;
420		#size-cells = <1>;
421		ranges = <0 0 0 0xffffffff>;
422		compatible = "simple-bus";
423
424		rng@22000 {
425			compatible = "qcom,prng";
426			reg = <0x00022000 0x200>;
427			clocks = <&gcc GCC_PRNG_AHB_CLK>;
428			clock-names = "core";
429		};
430
431		restart@4ab000 {
432			compatible = "qcom,pshold";
433			reg = <0x004ab000 0x4>;
434		};
435
436		qfprom: qfprom@5c000 {
437			compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
438			reg = <0x0005c000 0x1000>;
439			#address-cells = <1>;
440			#size-cells = <1>;
441
442			tsens_base1: base1@d0 {
443				reg = <0xd0 0x1>;
444				bits = <0 7>;
445			};
446
447			tsens_s0_p1: s0-p1@d0 {
448				reg = <0xd0 0x2>;
449				bits = <7 5>;
450			};
451
452			tsens_s0_p2: s0-p2@d1 {
453				reg = <0xd1 0x2>;
454				bits = <4 5>;
455			};
456
457			tsens_s1_p1: s1-p1@d2 {
458				reg = <0xd2 0x1>;
459				bits = <1 5>;
460			};
461			tsens_s1_p2: s1-p2@d2 {
462				reg = <0xd2 0x2>;
463				bits = <6 5>;
464			};
465			tsens_s2_p1: s2-p1@d3 {
466				reg = <0xd3 0x1>;
467				bits = <3 5>;
468			};
469
470			tsens_s2_p2: s2-p2@d4 {
471				reg = <0xd4 0x1>;
472				bits = <0 5>;
473			};
474
475			// no tsens with hw_id 3
476
477			tsens_s4_p1: s4-p1@d4 {
478				reg = <0xd4 0x2>;
479				bits = <5 5>;
480			};
481
482			tsens_s4_p2: s4-p2@d5 {
483				reg = <0xd5 0x1>;
484				bits = <2 5>;
485			};
486
487			tsens_s5_p1: s5-p1@d5 {
488				reg = <0xd5 0x2>;
489				bits = <7 5>;
490			};
491
492			tsens_s5_p2: s5-p2@d6 {
493				reg = <0xd6 0x2>;
494				bits = <4 5>;
495			};
496
497			tsens_base2: base2@d7 {
498				reg = <0xd7 0x1>;
499				bits = <1 7>;
500			};
501
502			tsens_mode: mode@ef {
503				reg = <0xef 0x1>;
504				bits = <5 3>;
505			};
506		};
507
508		rpm_msg_ram: sram@60000 {
509			compatible = "qcom,rpm-msg-ram";
510			reg = <0x00060000 0x8000>;
511		};
512
513		sram@290000 {
514			compatible = "qcom,msm8916-rpm-stats";
515			reg = <0x00290000 0x10000>;
516		};
517
518		bimc: interconnect@400000 {
519			compatible = "qcom,msm8916-bimc";
520			reg = <0x00400000 0x62000>;
521			#interconnect-cells = <1>;
522			clock-names = "bus", "bus_a";
523			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
524				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
525		};
526
527		tsens: thermal-sensor@4a9000 {
528			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
529			reg = <0x004a9000 0x1000>, /* TM */
530			      <0x004a8000 0x1000>; /* SROT */
531
532			// no hw_id 3
533			nvmem-cells = <&tsens_mode>,
534				      <&tsens_base1>, <&tsens_base2>,
535				      <&tsens_s0_p1>, <&tsens_s0_p2>,
536				      <&tsens_s1_p1>, <&tsens_s1_p2>,
537				      <&tsens_s2_p1>, <&tsens_s2_p2>,
538				      <&tsens_s4_p1>, <&tsens_s4_p2>,
539				      <&tsens_s5_p1>, <&tsens_s5_p2>;
540			nvmem-cell-names = "mode",
541					   "base1", "base2",
542					   "s0_p1", "s0_p2",
543					   "s1_p1", "s1_p2",
544					   "s2_p1", "s2_p2",
545					   "s4_p1", "s4_p2",
546					   "s5_p1", "s5_p2";
547			#qcom,sensors = <5>;
548			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
549			interrupt-names = "uplow";
550			#thermal-sensor-cells = <1>;
551		};
552
553		pcnoc: interconnect@500000 {
554			compatible = "qcom,msm8916-pcnoc";
555			reg = <0x00500000 0x11000>;
556			#interconnect-cells = <1>;
557			clock-names = "bus", "bus_a";
558			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
559				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
560		};
561
562		snoc: interconnect@580000 {
563			compatible = "qcom,msm8916-snoc";
564			reg = <0x00580000 0x14000>;
565			#interconnect-cells = <1>;
566			clock-names = "bus", "bus_a";
567			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
568				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
569		};
570
571		stm: stm@802000 {
572			compatible = "arm,coresight-stm", "arm,primecell";
573			reg = <0x00802000 0x1000>,
574			      <0x09280000 0x180000>;
575			reg-names = "stm-base", "stm-stimulus-base";
576
577			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
578			clock-names = "apb_pclk", "atclk";
579
580			status = "disabled";
581
582			out-ports {
583				port {
584					stm_out: endpoint {
585						remote-endpoint = <&funnel0_in7>;
586					};
587				};
588			};
589		};
590
591		/* System CTIs */
592		/* CTI 0 - TMC connections */
593		cti0: cti@810000 {
594			compatible = "arm,coresight-cti", "arm,primecell";
595			reg = <0x00810000 0x1000>;
596
597			clocks = <&rpmcc RPM_QDSS_CLK>;
598			clock-names = "apb_pclk";
599
600			status = "disabled";
601		};
602
603		/* CTI 1 - TPIU connections */
604		cti1: cti@811000 {
605			compatible = "arm,coresight-cti", "arm,primecell";
606			reg = <0x00811000 0x1000>;
607
608			clocks = <&rpmcc RPM_QDSS_CLK>;
609			clock-names = "apb_pclk";
610
611			status = "disabled";
612		};
613
614		/* CTIs 2-11 - no information - not instantiated */
615
616		tpiu: tpiu@820000 {
617			compatible = "arm,coresight-tpiu", "arm,primecell";
618			reg = <0x00820000 0x1000>;
619
620			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
621			clock-names = "apb_pclk", "atclk";
622
623			status = "disabled";
624
625			in-ports {
626				port {
627					tpiu_in: endpoint {
628						remote-endpoint = <&replicator_out1>;
629					};
630				};
631			};
632		};
633
634		funnel0: funnel@821000 {
635			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
636			reg = <0x00821000 0x1000>;
637
638			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
639			clock-names = "apb_pclk", "atclk";
640
641			status = "disabled";
642
643			in-ports {
644				#address-cells = <1>;
645				#size-cells = <0>;
646
647				/*
648				 * Not described input ports:
649				 * 0 - connected to Resource and Power Manger CPU ETM
650				 * 1 - not-connected
651				 * 2 - connected to Modem CPU ETM
652				 * 3 - not-connected
653				 * 5 - not-connected
654				 * 6 - connected trought funnel to Wireless CPU ETM
655				 * 7 - connected to STM component
656				 */
657
658				port@4 {
659					reg = <4>;
660					funnel0_in4: endpoint {
661						remote-endpoint = <&funnel1_out>;
662					};
663				};
664
665				port@7 {
666					reg = <7>;
667					funnel0_in7: endpoint {
668						remote-endpoint = <&stm_out>;
669					};
670				};
671			};
672
673			out-ports {
674				port {
675					funnel0_out: endpoint {
676						remote-endpoint = <&etf_in>;
677					};
678				};
679			};
680		};
681
682		replicator: replicator@824000 {
683			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
684			reg = <0x00824000 0x1000>;
685
686			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
687			clock-names = "apb_pclk", "atclk";
688
689			status = "disabled";
690
691			out-ports {
692				#address-cells = <1>;
693				#size-cells = <0>;
694
695				port@0 {
696					reg = <0>;
697					replicator_out0: endpoint {
698						remote-endpoint = <&etr_in>;
699					};
700				};
701				port@1 {
702					reg = <1>;
703					replicator_out1: endpoint {
704						remote-endpoint = <&tpiu_in>;
705					};
706				};
707			};
708
709			in-ports {
710				port {
711					replicator_in: endpoint {
712						remote-endpoint = <&etf_out>;
713					};
714				};
715			};
716		};
717
718		etf: etf@825000 {
719			compatible = "arm,coresight-tmc", "arm,primecell";
720			reg = <0x00825000 0x1000>;
721
722			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
723			clock-names = "apb_pclk", "atclk";
724
725			status = "disabled";
726
727			in-ports {
728				port {
729					etf_in: endpoint {
730						remote-endpoint = <&funnel0_out>;
731					};
732				};
733			};
734
735			out-ports {
736				port {
737					etf_out: endpoint {
738						remote-endpoint = <&replicator_in>;
739					};
740				};
741			};
742		};
743
744		etr: etr@826000 {
745			compatible = "arm,coresight-tmc", "arm,primecell";
746			reg = <0x00826000 0x1000>;
747
748			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
749			clock-names = "apb_pclk", "atclk";
750
751			status = "disabled";
752
753			in-ports {
754				port {
755					etr_in: endpoint {
756						remote-endpoint = <&replicator_out0>;
757					};
758				};
759			};
760		};
761
762		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
763			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
764			reg = <0x00841000 0x1000>;
765
766			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
767			clock-names = "apb_pclk", "atclk";
768
769			status = "disabled";
770
771			in-ports {
772				#address-cells = <1>;
773				#size-cells = <0>;
774
775				port@0 {
776					reg = <0>;
777					funnel1_in0: endpoint {
778						remote-endpoint = <&etm0_out>;
779					};
780				};
781				port@1 {
782					reg = <1>;
783					funnel1_in1: endpoint {
784						remote-endpoint = <&etm1_out>;
785					};
786				};
787				port@2 {
788					reg = <2>;
789					funnel1_in2: endpoint {
790						remote-endpoint = <&etm2_out>;
791					};
792				};
793				port@3 {
794					reg = <3>;
795					funnel1_in3: endpoint {
796						remote-endpoint = <&etm3_out>;
797					};
798				};
799			};
800
801			out-ports {
802				port {
803					funnel1_out: endpoint {
804						remote-endpoint = <&funnel0_in4>;
805					};
806				};
807			};
808		};
809
810		debug0: debug@850000 {
811			compatible = "arm,coresight-cpu-debug", "arm,primecell";
812			reg = <0x00850000 0x1000>;
813			clocks = <&rpmcc RPM_QDSS_CLK>;
814			clock-names = "apb_pclk";
815			cpu = <&CPU0>;
816			status = "disabled";
817		};
818
819		debug1: debug@852000 {
820			compatible = "arm,coresight-cpu-debug", "arm,primecell";
821			reg = <0x00852000 0x1000>;
822			clocks = <&rpmcc RPM_QDSS_CLK>;
823			clock-names = "apb_pclk";
824			cpu = <&CPU1>;
825			status = "disabled";
826		};
827
828		debug2: debug@854000 {
829			compatible = "arm,coresight-cpu-debug", "arm,primecell";
830			reg = <0x00854000 0x1000>;
831			clocks = <&rpmcc RPM_QDSS_CLK>;
832			clock-names = "apb_pclk";
833			cpu = <&CPU2>;
834			status = "disabled";
835		};
836
837		debug3: debug@856000 {
838			compatible = "arm,coresight-cpu-debug", "arm,primecell";
839			reg = <0x00856000 0x1000>;
840			clocks = <&rpmcc RPM_QDSS_CLK>;
841			clock-names = "apb_pclk";
842			cpu = <&CPU3>;
843			status = "disabled";
844		};
845
846		/* Core CTIs; CTIs 12-15 */
847		/* CTI - CPU-0 */
848		cti12: cti@858000 {
849			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
850				     "arm,primecell";
851			reg = <0x00858000 0x1000>;
852
853			clocks = <&rpmcc RPM_QDSS_CLK>;
854			clock-names = "apb_pclk";
855
856			cpu = <&CPU0>;
857			arm,cs-dev-assoc = <&etm0>;
858
859			status = "disabled";
860		};
861
862		/* CTI - CPU-1 */
863		cti13: cti@859000 {
864			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
865				     "arm,primecell";
866			reg = <0x00859000 0x1000>;
867
868			clocks = <&rpmcc RPM_QDSS_CLK>;
869			clock-names = "apb_pclk";
870
871			cpu = <&CPU1>;
872			arm,cs-dev-assoc = <&etm1>;
873
874			status = "disabled";
875		};
876
877		/* CTI - CPU-2 */
878		cti14: cti@85a000 {
879			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
880				     "arm,primecell";
881			reg = <0x0085a000 0x1000>;
882
883			clocks = <&rpmcc RPM_QDSS_CLK>;
884			clock-names = "apb_pclk";
885
886			cpu = <&CPU2>;
887			arm,cs-dev-assoc = <&etm2>;
888
889			status = "disabled";
890		};
891
892		/* CTI - CPU-3 */
893		cti15: cti@85b000 {
894			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
895				     "arm,primecell";
896			reg = <0x0085b000 0x1000>;
897
898			clocks = <&rpmcc RPM_QDSS_CLK>;
899			clock-names = "apb_pclk";
900
901			cpu = <&CPU3>;
902			arm,cs-dev-assoc = <&etm3>;
903
904			status = "disabled";
905		};
906
907		etm0: etm@85c000 {
908			compatible = "arm,coresight-etm4x", "arm,primecell";
909			reg = <0x0085c000 0x1000>;
910
911			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
912			clock-names = "apb_pclk", "atclk";
913			arm,coresight-loses-context-with-cpu;
914
915			cpu = <&CPU0>;
916
917			status = "disabled";
918
919			out-ports {
920				port {
921					etm0_out: endpoint {
922						remote-endpoint = <&funnel1_in0>;
923					};
924				};
925			};
926		};
927
928		etm1: etm@85d000 {
929			compatible = "arm,coresight-etm4x", "arm,primecell";
930			reg = <0x0085d000 0x1000>;
931
932			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
933			clock-names = "apb_pclk", "atclk";
934			arm,coresight-loses-context-with-cpu;
935
936			cpu = <&CPU1>;
937
938			status = "disabled";
939
940			out-ports {
941				port {
942					etm1_out: endpoint {
943						remote-endpoint = <&funnel1_in1>;
944					};
945				};
946			};
947		};
948
949		etm2: etm@85e000 {
950			compatible = "arm,coresight-etm4x", "arm,primecell";
951			reg = <0x0085e000 0x1000>;
952
953			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
954			clock-names = "apb_pclk", "atclk";
955			arm,coresight-loses-context-with-cpu;
956
957			cpu = <&CPU2>;
958
959			status = "disabled";
960
961			out-ports {
962				port {
963					etm2_out: endpoint {
964						remote-endpoint = <&funnel1_in2>;
965					};
966				};
967			};
968		};
969
970		etm3: etm@85f000 {
971			compatible = "arm,coresight-etm4x", "arm,primecell";
972			reg = <0x0085f000 0x1000>;
973
974			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
975			clock-names = "apb_pclk", "atclk";
976			arm,coresight-loses-context-with-cpu;
977
978			cpu = <&CPU3>;
979
980			status = "disabled";
981
982			out-ports {
983				port {
984					etm3_out: endpoint {
985						remote-endpoint = <&funnel1_in3>;
986					};
987				};
988			};
989		};
990
991		tlmm: pinctrl@1000000 {
992			compatible = "qcom,msm8916-pinctrl";
993			reg = <0x01000000 0x300000>;
994			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
995			gpio-controller;
996			gpio-ranges = <&tlmm 0 0 122>;
997			#gpio-cells = <2>;
998			interrupt-controller;
999			#interrupt-cells = <2>;
1000
1001			blsp_i2c1_default: blsp-i2c1-default-state {
1002				pins = "gpio2", "gpio3";
1003				function = "blsp_i2c1";
1004				drive-strength = <2>;
1005				bias-disable;
1006			};
1007
1008			blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1009				pins = "gpio2", "gpio3";
1010				function = "gpio";
1011				drive-strength = <2>;
1012				bias-disable;
1013			};
1014
1015			blsp_i2c2_default: blsp-i2c2-default-state {
1016				pins = "gpio6", "gpio7";
1017				function = "blsp_i2c2";
1018				drive-strength = <2>;
1019				bias-disable;
1020			};
1021
1022			blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1023				pins = "gpio6", "gpio7";
1024				function = "gpio";
1025				drive-strength = <2>;
1026				bias-disable;
1027			};
1028
1029			blsp_i2c3_default: blsp-i2c3-default-state {
1030				pins = "gpio10", "gpio11";
1031				function = "blsp_i2c3";
1032				drive-strength = <2>;
1033				bias-disable;
1034			};
1035
1036			blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1037				pins = "gpio10", "gpio11";
1038				function = "gpio";
1039				drive-strength = <2>;
1040				bias-disable;
1041			};
1042
1043			blsp_i2c4_default: blsp-i2c4-default-state {
1044				pins = "gpio14", "gpio15";
1045				function = "blsp_i2c4";
1046				drive-strength = <2>;
1047				bias-disable;
1048			};
1049
1050			blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1051				pins = "gpio14", "gpio15";
1052				function = "gpio";
1053				drive-strength = <2>;
1054				bias-disable;
1055			};
1056
1057			blsp_i2c5_default: blsp-i2c5-default-state {
1058				pins = "gpio18", "gpio19";
1059				function = "blsp_i2c5";
1060				drive-strength = <2>;
1061				bias-disable;
1062			};
1063
1064			blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1065				pins = "gpio18", "gpio19";
1066				function = "gpio";
1067				drive-strength = <2>;
1068				bias-disable;
1069			};
1070
1071			blsp_i2c6_default: blsp-i2c6-default-state {
1072				pins = "gpio22", "gpio23";
1073				function = "blsp_i2c6";
1074				drive-strength = <2>;
1075				bias-disable;
1076			};
1077
1078			blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1079				pins = "gpio22", "gpio23";
1080				function = "gpio";
1081				drive-strength = <2>;
1082				bias-disable;
1083			};
1084
1085			blsp_spi1_default: blsp-spi1-default-state {
1086				spi-pins {
1087					pins = "gpio0", "gpio1", "gpio3";
1088					function = "blsp_spi1";
1089					drive-strength = <12>;
1090					bias-disable;
1091				};
1092				cs-pins {
1093					pins = "gpio2";
1094					function = "gpio";
1095					drive-strength = <16>;
1096					bias-disable;
1097					output-high;
1098				};
1099			};
1100
1101			blsp_spi1_sleep: blsp-spi1-sleep-state {
1102				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1103				function = "gpio";
1104				drive-strength = <2>;
1105				bias-pull-down;
1106			};
1107
1108			blsp_spi2_default: blsp-spi2-default-state {
1109				spi-pins {
1110					pins = "gpio4", "gpio5", "gpio7";
1111					function = "blsp_spi2";
1112					drive-strength = <12>;
1113					bias-disable;
1114				};
1115				cs-pins {
1116					pins = "gpio6";
1117					function = "gpio";
1118					drive-strength = <16>;
1119					bias-disable;
1120					output-high;
1121				};
1122			};
1123
1124			blsp_spi2_sleep: blsp-spi2-sleep-state {
1125				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1126				function = "gpio";
1127				drive-strength = <2>;
1128				bias-pull-down;
1129			};
1130
1131			blsp_spi3_default: blsp-spi3-default-state {
1132				spi-pins {
1133					pins = "gpio8", "gpio9", "gpio11";
1134					function = "blsp_spi3";
1135					drive-strength = <12>;
1136					bias-disable;
1137				};
1138				cs-pins {
1139					pins = "gpio10";
1140					function = "gpio";
1141					drive-strength = <16>;
1142					bias-disable;
1143					output-high;
1144				};
1145			};
1146
1147			blsp_spi3_sleep: blsp-spi3-sleep-state {
1148				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1149				function = "gpio";
1150				drive-strength = <2>;
1151				bias-pull-down;
1152			};
1153
1154			blsp_spi4_default: blsp-spi4-default-state {
1155				spi-pins {
1156					pins = "gpio12", "gpio13", "gpio15";
1157					function = "blsp_spi4";
1158					drive-strength = <12>;
1159					bias-disable;
1160				};
1161				cs-pins {
1162					pins = "gpio14";
1163					function = "gpio";
1164					drive-strength = <16>;
1165					bias-disable;
1166					output-high;
1167				};
1168			};
1169
1170			blsp_spi4_sleep: blsp-spi4-sleep-state {
1171				pins = "gpio12", "gpio13", "gpio14", "gpio15";
1172				function = "gpio";
1173				drive-strength = <2>;
1174				bias-pull-down;
1175			};
1176
1177			blsp_spi5_default: blsp-spi5-default-state {
1178				spi-pins {
1179					pins = "gpio16", "gpio17", "gpio19";
1180					function = "blsp_spi5";
1181					drive-strength = <12>;
1182					bias-disable;
1183				};
1184				cs-pins {
1185					pins = "gpio18";
1186					function = "gpio";
1187					drive-strength = <16>;
1188					bias-disable;
1189					output-high;
1190				};
1191			};
1192
1193			blsp_spi5_sleep: blsp-spi5-sleep-state {
1194				pins = "gpio16", "gpio17", "gpio18", "gpio19";
1195				function = "gpio";
1196				drive-strength = <2>;
1197				bias-pull-down;
1198			};
1199
1200			blsp_spi6_default: blsp-spi6-default-state {
1201				spi-pins {
1202					pins = "gpio20", "gpio21", "gpio23";
1203					function = "blsp_spi6";
1204					drive-strength = <12>;
1205					bias-disable;
1206				};
1207				cs-pins {
1208					pins = "gpio22";
1209					function = "gpio";
1210					drive-strength = <16>;
1211					bias-disable;
1212					output-high;
1213				};
1214			};
1215
1216			blsp_spi6_sleep: blsp-spi6-sleep-state {
1217				pins = "gpio20", "gpio21", "gpio22", "gpio23";
1218				function = "gpio";
1219				drive-strength = <2>;
1220				bias-pull-down;
1221			};
1222
1223			blsp_uart1_default: blsp-uart1-default-state {
1224				/* TX, RX, CTS_N, RTS_N */
1225				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1226				function = "blsp_uart1";
1227				drive-strength = <16>;
1228				bias-disable;
1229			};
1230
1231			blsp_uart1_sleep: blsp-uart1-sleep-state {
1232				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1233				function = "gpio";
1234				drive-strength = <2>;
1235				bias-pull-down;
1236			};
1237
1238			blsp_uart2_default: blsp-uart2-default-state {
1239				pins = "gpio4", "gpio5";
1240				function = "blsp_uart2";
1241				drive-strength = <16>;
1242				bias-disable;
1243			};
1244
1245			blsp_uart2_sleep: blsp-uart2-sleep-state {
1246				pins = "gpio4", "gpio5";
1247				function = "gpio";
1248				drive-strength = <2>;
1249				bias-pull-down;
1250			};
1251
1252			camera_front_default: camera-front-default-state {
1253				pwdn-pins {
1254					pins = "gpio33";
1255					function = "gpio";
1256					drive-strength = <16>;
1257					bias-disable;
1258				};
1259				rst-pins {
1260					pins = "gpio28";
1261					function = "gpio";
1262					drive-strength = <16>;
1263					bias-disable;
1264				};
1265				mclk1-pins {
1266					pins = "gpio27";
1267					function = "cam_mclk1";
1268					drive-strength = <16>;
1269					bias-disable;
1270				};
1271			};
1272
1273			camera_rear_default: camera-rear-default-state {
1274				pwdn-pins {
1275					pins = "gpio34";
1276					function = "gpio";
1277					drive-strength = <16>;
1278					bias-disable;
1279				};
1280				rst-pins {
1281					pins = "gpio35";
1282					function = "gpio";
1283					drive-strength = <16>;
1284					bias-disable;
1285				};
1286				mclk0-pins {
1287					pins = "gpio26";
1288					function = "cam_mclk0";
1289					drive-strength = <16>;
1290					bias-disable;
1291				};
1292			};
1293
1294			cci0_default: cci0-default-state {
1295				pins = "gpio29", "gpio30";
1296				function = "cci_i2c";
1297				drive-strength = <16>;
1298				bias-disable;
1299			};
1300
1301			cdc_dmic_default: cdc-dmic-default-state {
1302				clk-pins {
1303					pins = "gpio0";
1304					function = "dmic0_clk";
1305					drive-strength = <8>;
1306				};
1307				data-pins {
1308					pins = "gpio1";
1309					function = "dmic0_data";
1310					drive-strength = <8>;
1311				};
1312			};
1313
1314			cdc_dmic_sleep: cdc-dmic-sleep-state {
1315				clk-pins {
1316					pins = "gpio0";
1317					function = "dmic0_clk";
1318					drive-strength = <2>;
1319					bias-disable;
1320				};
1321				data-pins {
1322					pins = "gpio1";
1323					function = "dmic0_data";
1324					drive-strength = <2>;
1325					bias-disable;
1326				};
1327			};
1328
1329			cdc_pdm_default: cdc-pdm-default-state {
1330				pins = "gpio63", "gpio64", "gpio65", "gpio66",
1331				       "gpio67", "gpio68";
1332				function = "cdc_pdm0";
1333				drive-strength = <8>;
1334				bias-disable;
1335			};
1336
1337			cdc_pdm_sleep: cdc-pdm-sleep-state {
1338				pins = "gpio63", "gpio64", "gpio65", "gpio66",
1339				       "gpio67", "gpio68";
1340				function = "cdc_pdm0";
1341				drive-strength = <2>;
1342				bias-pull-down;
1343			};
1344
1345			pri_mi2s_default: mi2s-pri-default-state {
1346				pins = "gpio113", "gpio114", "gpio115", "gpio116";
1347				function = "pri_mi2s";
1348				drive-strength = <8>;
1349				bias-disable;
1350			};
1351
1352			pri_mi2s_sleep: mi2s-pri-sleep-state {
1353				pins = "gpio113", "gpio114", "gpio115", "gpio116";
1354				function = "pri_mi2s";
1355				drive-strength = <2>;
1356				bias-disable;
1357			};
1358
1359			pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1360				pins = "gpio116";
1361				function = "pri_mi2s";
1362				drive-strength = <8>;
1363				bias-disable;
1364			};
1365
1366			pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1367				pins = "gpio116";
1368				function = "pri_mi2s";
1369				drive-strength = <2>;
1370				bias-disable;
1371			};
1372
1373			pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1374				pins = "gpio110";
1375				function = "pri_mi2s_ws";
1376				drive-strength = <8>;
1377				bias-disable;
1378			};
1379
1380			pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1381				pins = "gpio110";
1382				function = "pri_mi2s_ws";
1383				drive-strength = <2>;
1384				bias-disable;
1385			};
1386
1387			sec_mi2s_default: mi2s-sec-default-state {
1388				pins = "gpio112", "gpio117", "gpio118", "gpio119";
1389				function = "sec_mi2s";
1390				drive-strength = <8>;
1391				bias-disable;
1392			};
1393
1394			sec_mi2s_sleep: mi2s-sec-sleep-state {
1395				pins = "gpio112", "gpio117", "gpio118", "gpio119";
1396				function = "sec_mi2s";
1397				drive-strength = <2>;
1398				bias-disable;
1399			};
1400
1401			sdc1_default: sdc1-default-state {
1402				clk-pins {
1403					pins = "sdc1_clk";
1404					bias-disable;
1405					drive-strength = <16>;
1406				};
1407				cmd-pins {
1408					pins = "sdc1_cmd";
1409					bias-pull-up;
1410					drive-strength = <10>;
1411				};
1412				data-pins {
1413					pins = "sdc1_data";
1414					bias-pull-up;
1415					drive-strength = <10>;
1416				};
1417			};
1418
1419			sdc1_sleep: sdc1-sleep-state {
1420				clk-pins {
1421					pins = "sdc1_clk";
1422					bias-disable;
1423					drive-strength = <2>;
1424				};
1425				cmd-pins {
1426					pins = "sdc1_cmd";
1427					bias-pull-up;
1428					drive-strength = <2>;
1429				};
1430				data-pins {
1431					pins = "sdc1_data";
1432					bias-pull-up;
1433					drive-strength = <2>;
1434				};
1435			};
1436
1437			sdc2_default: sdc2-default-state {
1438				clk-pins {
1439					pins = "sdc2_clk";
1440					bias-disable;
1441					drive-strength = <16>;
1442				};
1443				cmd-pins {
1444					pins = "sdc2_cmd";
1445					bias-pull-up;
1446					drive-strength = <10>;
1447				};
1448				data-pins {
1449					pins = "sdc2_data";
1450					bias-pull-up;
1451					drive-strength = <10>;
1452				};
1453			};
1454
1455			sdc2_sleep: sdc2-sleep-state {
1456				clk-pins {
1457					pins = "sdc2_clk";
1458					bias-disable;
1459					drive-strength = <2>;
1460				};
1461				cmd-pins {
1462					pins = "sdc2_cmd";
1463					bias-pull-up;
1464					drive-strength = <2>;
1465				};
1466				data-pins {
1467					pins = "sdc2_data";
1468					bias-pull-up;
1469					drive-strength = <2>;
1470				};
1471			};
1472
1473			wcss_wlan_default: wcss-wlan-default-state {
1474				pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1475				function = "wcss_wlan";
1476				drive-strength = <6>;
1477				bias-pull-up;
1478			};
1479		};
1480
1481		gcc: clock-controller@1800000 {
1482			compatible = "qcom,gcc-msm8916";
1483			#clock-cells = <1>;
1484			#reset-cells = <1>;
1485			#power-domain-cells = <1>;
1486			reg = <0x01800000 0x80000>;
1487			clocks = <&xo_board>,
1488				 <&sleep_clk>,
1489				 <&mdss_dsi0_phy 1>,
1490				 <&mdss_dsi0_phy 0>,
1491				 <0>,
1492				 <0>,
1493				 <0>;
1494			clock-names = "xo",
1495				      "sleep_clk",
1496				      "dsi0pll",
1497				      "dsi0pllbyte",
1498				      "ext_mclk",
1499				      "ext_pri_i2s",
1500				      "ext_sec_i2s";
1501		};
1502
1503		tcsr_mutex: hwlock@1905000 {
1504			compatible = "qcom,tcsr-mutex";
1505			reg = <0x01905000 0x20000>;
1506			#hwlock-cells = <1>;
1507		};
1508
1509		tcsr: syscon@1937000 {
1510			compatible = "qcom,tcsr-msm8916", "syscon";
1511			reg = <0x01937000 0x30000>;
1512		};
1513
1514		mdss: display-subsystem@1a00000 {
1515			status = "disabled";
1516			compatible = "qcom,mdss";
1517			reg = <0x01a00000 0x1000>,
1518			      <0x01ac8000 0x3000>;
1519			reg-names = "mdss_phys", "vbif_phys";
1520
1521			power-domains = <&gcc MDSS_GDSC>;
1522
1523			clocks = <&gcc GCC_MDSS_AHB_CLK>,
1524				 <&gcc GCC_MDSS_AXI_CLK>,
1525				 <&gcc GCC_MDSS_VSYNC_CLK>;
1526			clock-names = "iface",
1527				      "bus",
1528				      "vsync";
1529
1530			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1531
1532			interrupt-controller;
1533			#interrupt-cells = <1>;
1534
1535			#address-cells = <1>;
1536			#size-cells = <1>;
1537			ranges;
1538
1539			mdss_mdp: display-controller@1a01000 {
1540				compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1541				reg = <0x01a01000 0x89000>;
1542				reg-names = "mdp_phys";
1543
1544				interrupt-parent = <&mdss>;
1545				interrupts = <0>;
1546
1547				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1548					 <&gcc GCC_MDSS_AXI_CLK>,
1549					 <&gcc GCC_MDSS_MDP_CLK>,
1550					 <&gcc GCC_MDSS_VSYNC_CLK>;
1551				clock-names = "iface",
1552					      "bus",
1553					      "core",
1554					      "vsync";
1555
1556				iommus = <&apps_iommu 4>;
1557
1558				ports {
1559					#address-cells = <1>;
1560					#size-cells = <0>;
1561
1562					port@0 {
1563						reg = <0>;
1564						mdss_mdp_intf1_out: endpoint {
1565							remote-endpoint = <&mdss_dsi0_in>;
1566						};
1567					};
1568				};
1569			};
1570
1571			mdss_dsi0: dsi@1a98000 {
1572				compatible = "qcom,msm8916-dsi-ctrl",
1573					     "qcom,mdss-dsi-ctrl";
1574				reg = <0x01a98000 0x25c>;
1575				reg-names = "dsi_ctrl";
1576
1577				interrupt-parent = <&mdss>;
1578				interrupts = <4>;
1579
1580				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1581						  <&gcc PCLK0_CLK_SRC>;
1582				assigned-clock-parents = <&mdss_dsi0_phy 0>,
1583							 <&mdss_dsi0_phy 1>;
1584
1585				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1586					 <&gcc GCC_MDSS_AHB_CLK>,
1587					 <&gcc GCC_MDSS_AXI_CLK>,
1588					 <&gcc GCC_MDSS_BYTE0_CLK>,
1589					 <&gcc GCC_MDSS_PCLK0_CLK>,
1590					 <&gcc GCC_MDSS_ESC0_CLK>;
1591				clock-names = "mdp_core",
1592					      "iface",
1593					      "bus",
1594					      "byte",
1595					      "pixel",
1596					      "core";
1597				phys = <&mdss_dsi0_phy>;
1598
1599				#address-cells = <1>;
1600				#size-cells = <0>;
1601
1602				ports {
1603					#address-cells = <1>;
1604					#size-cells = <0>;
1605
1606					port@0 {
1607						reg = <0>;
1608						mdss_dsi0_in: endpoint {
1609							remote-endpoint = <&mdss_mdp_intf1_out>;
1610						};
1611					};
1612
1613					port@1 {
1614						reg = <1>;
1615						mdss_dsi0_out: endpoint {
1616						};
1617					};
1618				};
1619			};
1620
1621			mdss_dsi0_phy: phy@1a98300 {
1622				compatible = "qcom,dsi-phy-28nm-lp";
1623				reg = <0x01a98300 0xd4>,
1624				      <0x01a98500 0x280>,
1625				      <0x01a98780 0x30>;
1626				reg-names = "dsi_pll",
1627					    "dsi_phy",
1628					    "dsi_phy_regulator";
1629
1630				#clock-cells = <1>;
1631				#phy-cells = <0>;
1632
1633				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1634					 <&xo_board>;
1635				clock-names = "iface", "ref";
1636			};
1637		};
1638
1639		camss: camss@1b0ac00 {
1640			compatible = "qcom,msm8916-camss";
1641			reg = <0x01b0ac00 0x200>,
1642				<0x01b00030 0x4>,
1643				<0x01b0b000 0x200>,
1644				<0x01b00038 0x4>,
1645				<0x01b08000 0x100>,
1646				<0x01b08400 0x100>,
1647				<0x01b0a000 0x500>,
1648				<0x01b00020 0x10>,
1649				<0x01b10000 0x1000>;
1650			reg-names = "csiphy0",
1651				"csiphy0_clk_mux",
1652				"csiphy1",
1653				"csiphy1_clk_mux",
1654				"csid0",
1655				"csid1",
1656				"ispif",
1657				"csi_clk_mux",
1658				"vfe0";
1659			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1660				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1661				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1662				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1663				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1664				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1665			interrupt-names = "csiphy0",
1666				"csiphy1",
1667				"csid0",
1668				"csid1",
1669				"ispif",
1670				"vfe0";
1671			power-domains = <&gcc VFE_GDSC>;
1672			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1673				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1674				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1675				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1676				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1677				<&gcc GCC_CAMSS_CSI0_CLK>,
1678				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
1679				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
1680				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
1681				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1682				<&gcc GCC_CAMSS_CSI1_CLK>,
1683				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
1684				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
1685				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
1686				<&gcc GCC_CAMSS_AHB_CLK>,
1687				<&gcc GCC_CAMSS_VFE0_CLK>,
1688				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1689				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
1690				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
1691			clock-names = "top_ahb",
1692				"ispif_ahb",
1693				"csiphy0_timer",
1694				"csiphy1_timer",
1695				"csi0_ahb",
1696				"csi0",
1697				"csi0_phy",
1698				"csi0_pix",
1699				"csi0_rdi",
1700				"csi1_ahb",
1701				"csi1",
1702				"csi1_phy",
1703				"csi1_pix",
1704				"csi1_rdi",
1705				"ahb",
1706				"vfe0",
1707				"csi_vfe0",
1708				"vfe_ahb",
1709				"vfe_axi";
1710			iommus = <&apps_iommu 3>;
1711			status = "disabled";
1712			ports {
1713				#address-cells = <1>;
1714				#size-cells = <0>;
1715
1716				port@0 {
1717					reg = <0>;
1718				};
1719
1720				port@1 {
1721					reg = <1>;
1722				};
1723			};
1724		};
1725
1726		cci: cci@1b0c000 {
1727			compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1728			#address-cells = <1>;
1729			#size-cells = <0>;
1730			reg = <0x01b0c000 0x1000>;
1731			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1732			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1733				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
1734				<&gcc GCC_CAMSS_CCI_CLK>,
1735				<&gcc GCC_CAMSS_AHB_CLK>;
1736			clock-names = "camss_top_ahb", "cci_ahb",
1737					  "cci", "camss_ahb";
1738			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1739					  <&gcc GCC_CAMSS_CCI_CLK>;
1740			assigned-clock-rates = <80000000>, <19200000>;
1741			pinctrl-names = "default";
1742			pinctrl-0 = <&cci0_default>;
1743			status = "disabled";
1744
1745			cci_i2c0: i2c-bus@0 {
1746				reg = <0>;
1747				clock-frequency = <400000>;
1748				#address-cells = <1>;
1749				#size-cells = <0>;
1750			};
1751		};
1752
1753		gpu@1c00000 {
1754			compatible = "qcom,adreno-306.0", "qcom,adreno";
1755			reg = <0x01c00000 0x20000>;
1756			reg-names = "kgsl_3d0_reg_memory";
1757			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1758			interrupt-names = "kgsl_3d0_irq";
1759			clock-names =
1760			    "core",
1761			    "iface",
1762			    "mem",
1763			    "mem_iface",
1764			    "alt_mem_iface",
1765			    "gfx3d";
1766			clocks =
1767			    <&gcc GCC_OXILI_GFX3D_CLK>,
1768			    <&gcc GCC_OXILI_AHB_CLK>,
1769			    <&gcc GCC_OXILI_GMEM_CLK>,
1770			    <&gcc GCC_BIMC_GFX_CLK>,
1771			    <&gcc GCC_BIMC_GPU_CLK>,
1772			    <&gcc GFX3D_CLK_SRC>;
1773			power-domains = <&gcc OXILI_GDSC>;
1774			operating-points-v2 = <&gpu_opp_table>;
1775			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1776
1777			gpu_opp_table: opp-table {
1778				compatible = "operating-points-v2";
1779
1780				opp-400000000 {
1781					opp-hz = /bits/ 64 <400000000>;
1782				};
1783				opp-19200000 {
1784					opp-hz = /bits/ 64 <19200000>;
1785				};
1786			};
1787		};
1788
1789		venus: video-codec@1d00000 {
1790			compatible = "qcom,msm8916-venus";
1791			reg = <0x01d00000 0xff000>;
1792			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1793			power-domains = <&gcc VENUS_GDSC>;
1794			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1795				 <&gcc GCC_VENUS0_AHB_CLK>,
1796				 <&gcc GCC_VENUS0_AXI_CLK>;
1797			clock-names = "core", "iface", "bus";
1798			iommus = <&apps_iommu 5>;
1799			memory-region = <&venus_mem>;
1800			status = "okay";
1801
1802			video-decoder {
1803				compatible = "venus-decoder";
1804			};
1805
1806			video-encoder {
1807				compatible = "venus-encoder";
1808			};
1809		};
1810
1811		apps_iommu: iommu@1ef0000 {
1812			#address-cells = <1>;
1813			#size-cells = <1>;
1814			#iommu-cells = <1>;
1815			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1816			ranges = <0 0x01e20000 0x20000>;
1817			reg = <0x01ef0000 0x3000>;
1818			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1819				 <&gcc GCC_APSS_TCU_CLK>;
1820			clock-names = "iface", "bus";
1821			qcom,iommu-secure-id = <17>;
1822
1823			/* VFE */
1824			iommu-ctx@3000 {
1825				compatible = "qcom,msm-iommu-v1-sec";
1826				reg = <0x3000 0x1000>;
1827				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1828			};
1829
1830			/* MDP_0 */
1831			iommu-ctx@4000 {
1832				compatible = "qcom,msm-iommu-v1-ns";
1833				reg = <0x4000 0x1000>;
1834				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1835			};
1836
1837			/* VENUS_NS */
1838			iommu-ctx@5000 {
1839				compatible = "qcom,msm-iommu-v1-sec";
1840				reg = <0x5000 0x1000>;
1841				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1842			};
1843		};
1844
1845		gpu_iommu: iommu@1f08000 {
1846			#address-cells = <1>;
1847			#size-cells = <1>;
1848			#iommu-cells = <1>;
1849			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1850			ranges = <0 0x01f08000 0x10000>;
1851			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1852				 <&gcc GCC_GFX_TCU_CLK>;
1853			clock-names = "iface", "bus";
1854			qcom,iommu-secure-id = <18>;
1855
1856			/* GFX3D_USER */
1857			iommu-ctx@1000 {
1858				compatible = "qcom,msm-iommu-v1-ns";
1859				reg = <0x1000 0x1000>;
1860				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1861			};
1862
1863			/* GFX3D_PRIV */
1864			iommu-ctx@2000 {
1865				compatible = "qcom,msm-iommu-v1-ns";
1866				reg = <0x2000 0x1000>;
1867				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1868			};
1869		};
1870
1871		spmi_bus: spmi@200f000 {
1872			compatible = "qcom,spmi-pmic-arb";
1873			reg = <0x0200f000 0x001000>,
1874			      <0x02400000 0x400000>,
1875			      <0x02c00000 0x400000>,
1876			      <0x03800000 0x200000>,
1877			      <0x0200a000 0x002100>;
1878			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1879			interrupt-names = "periph_irq";
1880			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1881			qcom,ee = <0>;
1882			qcom,channel = <0>;
1883			#address-cells = <2>;
1884			#size-cells = <0>;
1885			interrupt-controller;
1886			#interrupt-cells = <4>;
1887		};
1888
1889		bam_dmux_dma: dma-controller@4044000 {
1890			compatible = "qcom,bam-v1.7.0";
1891			reg = <0x04044000 0x19000>;
1892			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1893			#dma-cells = <1>;
1894			qcom,ee = <0>;
1895
1896			num-channels = <6>;
1897			qcom,num-ees = <1>;
1898			qcom,powered-remotely;
1899
1900			status = "disabled";
1901		};
1902
1903		mpss: remoteproc@4080000 {
1904			compatible = "qcom,msm8916-mss-pil";
1905			reg = <0x04080000 0x100>,
1906			      <0x04020000 0x040>;
1907
1908			reg-names = "qdsp6", "rmb";
1909
1910			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1911					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1912					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1913					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1914					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1915			interrupt-names = "wdog", "fatal", "ready",
1916					  "handover", "stop-ack";
1917
1918			power-domains = <&rpmpd MSM8916_VDDCX>,
1919					<&rpmpd MSM8916_VDDMX>;
1920			power-domain-names = "cx", "mx";
1921
1922			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1923				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1924				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1925				 <&xo_board>;
1926			clock-names = "iface", "bus", "mem", "xo";
1927
1928			qcom,smem-states = <&hexagon_smp2p_out 0>;
1929			qcom,smem-state-names = "stop";
1930
1931			resets = <&scm 0>;
1932			reset-names = "mss_restart";
1933
1934			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1935
1936			status = "disabled";
1937
1938			mba {
1939				memory-region = <&mba_mem>;
1940			};
1941
1942			mpss {
1943				memory-region = <&mpss_mem>;
1944			};
1945
1946			bam_dmux: bam-dmux {
1947				compatible = "qcom,bam-dmux";
1948
1949				interrupt-parent = <&hexagon_smsm>;
1950				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1951				interrupt-names = "pc", "pc-ack";
1952
1953				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1954				qcom,smem-state-names = "pc", "pc-ack";
1955
1956				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1957				dma-names = "tx", "rx";
1958
1959				status = "disabled";
1960			};
1961
1962			smd-edge {
1963				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1964
1965				qcom,smd-edge = <0>;
1966				qcom,ipc = <&apcs 8 12>;
1967				qcom,remote-pid = <1>;
1968
1969				label = "hexagon";
1970
1971				fastrpc {
1972					compatible = "qcom,fastrpc";
1973					qcom,smd-channels = "fastrpcsmd-apps-dsp";
1974					label = "adsp";
1975					qcom,non-secure-domain;
1976
1977					#address-cells = <1>;
1978					#size-cells = <0>;
1979
1980					cb@1 {
1981						compatible = "qcom,fastrpc-compute-cb";
1982						reg = <1>;
1983					};
1984				};
1985			};
1986		};
1987
1988		sound: sound@7702000 {
1989			status = "disabled";
1990			compatible = "qcom,apq8016-sbc-sndcard";
1991			reg = <0x07702000 0x4>, <0x07702004 0x4>;
1992			reg-names = "mic-iomux", "spkr-iomux";
1993		};
1994
1995		lpass: audio-controller@7708000 {
1996			status = "disabled";
1997			compatible = "qcom,apq8016-lpass-cpu";
1998
1999			/*
2000			 * Note: Unlike the name would suggest, the SEC_I2S_CLK
2001			 * is actually only used by Tertiary MI2S while
2002			 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
2003			 */
2004			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2005				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2006				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2007				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2008				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2009				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2010				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2011
2012			clock-names = "ahbix-clk",
2013					"mi2s-bit-clk0",
2014					"mi2s-bit-clk1",
2015					"mi2s-bit-clk2",
2016					"mi2s-bit-clk3",
2017					"pcnoc-mport-clk",
2018					"pcnoc-sway-clk";
2019			#sound-dai-cells = <1>;
2020
2021			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2022			interrupt-names = "lpass-irq-lpaif";
2023			reg = <0x07708000 0x10000>;
2024			reg-names = "lpass-lpaif";
2025
2026			#address-cells = <1>;
2027			#size-cells = <0>;
2028		};
2029
2030		lpass_codec: audio-codec@771c000 {
2031			compatible = "qcom,msm8916-wcd-digital-codec";
2032			reg = <0x0771c000 0x400>;
2033			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2034				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
2035			clock-names = "ahbix-clk", "mclk";
2036			#sound-dai-cells = <1>;
2037			status = "disabled";
2038		};
2039
2040		sdhc_1: mmc@7824900 {
2041			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2042			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2043			reg-names = "hc", "core";
2044
2045			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2046				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2047			interrupt-names = "hc_irq", "pwr_irq";
2048			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2049				 <&gcc GCC_SDCC1_APPS_CLK>,
2050				 <&xo_board>;
2051			clock-names = "iface", "core", "xo";
2052			pinctrl-0 = <&sdc1_default>;
2053			pinctrl-1 = <&sdc1_sleep>;
2054			pinctrl-names = "default", "sleep";
2055			mmc-ddr-1_8v;
2056			bus-width = <8>;
2057			non-removable;
2058			status = "disabled";
2059		};
2060
2061		sdhc_2: mmc@7864900 {
2062			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2063			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2064			reg-names = "hc", "core";
2065
2066			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2067				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2068			interrupt-names = "hc_irq", "pwr_irq";
2069			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2070				 <&gcc GCC_SDCC2_APPS_CLK>,
2071				 <&xo_board>;
2072			clock-names = "iface", "core", "xo";
2073			pinctrl-0 = <&sdc2_default>;
2074			pinctrl-1 = <&sdc2_sleep>;
2075			pinctrl-names = "default", "sleep";
2076			bus-width = <4>;
2077			status = "disabled";
2078		};
2079
2080		blsp_dma: dma-controller@7884000 {
2081			compatible = "qcom,bam-v1.7.0";
2082			reg = <0x07884000 0x23000>;
2083			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2084			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2085			clock-names = "bam_clk";
2086			#dma-cells = <1>;
2087			qcom,ee = <0>;
2088			qcom,controlled-remotely;
2089		};
2090
2091		blsp_uart1: serial@78af000 {
2092			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2093			reg = <0x078af000 0x200>;
2094			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2095			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2096			clock-names = "core", "iface";
2097			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2098			dma-names = "tx", "rx";
2099			pinctrl-names = "default", "sleep";
2100			pinctrl-0 = <&blsp_uart1_default>;
2101			pinctrl-1 = <&blsp_uart1_sleep>;
2102			status = "disabled";
2103		};
2104
2105		blsp_uart2: serial@78b0000 {
2106			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2107			reg = <0x078b0000 0x200>;
2108			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2109			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2110			clock-names = "core", "iface";
2111			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
2112			dma-names = "tx", "rx";
2113			pinctrl-names = "default", "sleep";
2114			pinctrl-0 = <&blsp_uart2_default>;
2115			pinctrl-1 = <&blsp_uart2_sleep>;
2116			status = "disabled";
2117		};
2118
2119		blsp_i2c1: i2c@78b5000 {
2120			compatible = "qcom,i2c-qup-v2.2.1";
2121			reg = <0x078b5000 0x500>;
2122			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2123			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2124				 <&gcc GCC_BLSP1_AHB_CLK>;
2125			clock-names = "core", "iface";
2126			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2127			dma-names = "tx", "rx";
2128			pinctrl-names = "default", "sleep";
2129			pinctrl-0 = <&blsp_i2c1_default>;
2130			pinctrl-1 = <&blsp_i2c1_sleep>;
2131			#address-cells = <1>;
2132			#size-cells = <0>;
2133			status = "disabled";
2134		};
2135
2136		blsp_spi1: spi@78b5000 {
2137			compatible = "qcom,spi-qup-v2.2.1";
2138			reg = <0x078b5000 0x500>;
2139			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2140			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2141				 <&gcc GCC_BLSP1_AHB_CLK>;
2142			clock-names = "core", "iface";
2143			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2144			dma-names = "tx", "rx";
2145			pinctrl-names = "default", "sleep";
2146			pinctrl-0 = <&blsp_spi1_default>;
2147			pinctrl-1 = <&blsp_spi1_sleep>;
2148			#address-cells = <1>;
2149			#size-cells = <0>;
2150			status = "disabled";
2151		};
2152
2153		blsp_i2c2: i2c@78b6000 {
2154			compatible = "qcom,i2c-qup-v2.2.1";
2155			reg = <0x078b6000 0x500>;
2156			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2157			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2158				 <&gcc GCC_BLSP1_AHB_CLK>;
2159			clock-names = "core", "iface";
2160			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2161			dma-names = "tx", "rx";
2162			pinctrl-names = "default", "sleep";
2163			pinctrl-0 = <&blsp_i2c2_default>;
2164			pinctrl-1 = <&blsp_i2c2_sleep>;
2165			#address-cells = <1>;
2166			#size-cells = <0>;
2167			status = "disabled";
2168		};
2169
2170		blsp_spi2: spi@78b6000 {
2171			compatible = "qcom,spi-qup-v2.2.1";
2172			reg = <0x078b6000 0x500>;
2173			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2174			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2175				 <&gcc GCC_BLSP1_AHB_CLK>;
2176			clock-names = "core", "iface";
2177			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2178			dma-names = "tx", "rx";
2179			pinctrl-names = "default", "sleep";
2180			pinctrl-0 = <&blsp_spi2_default>;
2181			pinctrl-1 = <&blsp_spi2_sleep>;
2182			#address-cells = <1>;
2183			#size-cells = <0>;
2184			status = "disabled";
2185		};
2186
2187		blsp_i2c3: i2c@78b7000 {
2188			compatible = "qcom,i2c-qup-v2.2.1";
2189			reg = <0x078b7000 0x500>;
2190			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2191			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2192				 <&gcc GCC_BLSP1_AHB_CLK>;
2193			clock-names = "core", "iface";
2194			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2195			dma-names = "tx", "rx";
2196			pinctrl-names = "default", "sleep";
2197			pinctrl-0 = <&blsp_i2c3_default>;
2198			pinctrl-1 = <&blsp_i2c3_sleep>;
2199			#address-cells = <1>;
2200			#size-cells = <0>;
2201			status = "disabled";
2202		};
2203
2204		blsp_spi3: spi@78b7000 {
2205			compatible = "qcom,spi-qup-v2.2.1";
2206			reg = <0x078b7000 0x500>;
2207			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2208			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2209				 <&gcc GCC_BLSP1_AHB_CLK>;
2210			clock-names = "core", "iface";
2211			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2212			dma-names = "tx", "rx";
2213			pinctrl-names = "default", "sleep";
2214			pinctrl-0 = <&blsp_spi3_default>;
2215			pinctrl-1 = <&blsp_spi3_sleep>;
2216			#address-cells = <1>;
2217			#size-cells = <0>;
2218			status = "disabled";
2219		};
2220
2221		blsp_i2c4: i2c@78b8000 {
2222			compatible = "qcom,i2c-qup-v2.2.1";
2223			reg = <0x078b8000 0x500>;
2224			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2225			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2226				 <&gcc GCC_BLSP1_AHB_CLK>;
2227			clock-names = "core", "iface";
2228			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2229			dma-names = "tx", "rx";
2230			pinctrl-names = "default", "sleep";
2231			pinctrl-0 = <&blsp_i2c4_default>;
2232			pinctrl-1 = <&blsp_i2c4_sleep>;
2233			#address-cells = <1>;
2234			#size-cells = <0>;
2235			status = "disabled";
2236		};
2237
2238		blsp_spi4: spi@78b8000 {
2239			compatible = "qcom,spi-qup-v2.2.1";
2240			reg = <0x078b8000 0x500>;
2241			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2242			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2243				 <&gcc GCC_BLSP1_AHB_CLK>;
2244			clock-names = "core", "iface";
2245			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2246			dma-names = "tx", "rx";
2247			pinctrl-names = "default", "sleep";
2248			pinctrl-0 = <&blsp_spi4_default>;
2249			pinctrl-1 = <&blsp_spi4_sleep>;
2250			#address-cells = <1>;
2251			#size-cells = <0>;
2252			status = "disabled";
2253		};
2254
2255		blsp_i2c5: i2c@78b9000 {
2256			compatible = "qcom,i2c-qup-v2.2.1";
2257			reg = <0x078b9000 0x500>;
2258			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2259			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2260				 <&gcc GCC_BLSP1_AHB_CLK>;
2261			clock-names = "core", "iface";
2262			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2263			dma-names = "tx", "rx";
2264			pinctrl-names = "default", "sleep";
2265			pinctrl-0 = <&blsp_i2c5_default>;
2266			pinctrl-1 = <&blsp_i2c5_sleep>;
2267			#address-cells = <1>;
2268			#size-cells = <0>;
2269			status = "disabled";
2270		};
2271
2272		blsp_spi5: spi@78b9000 {
2273			compatible = "qcom,spi-qup-v2.2.1";
2274			reg = <0x078b9000 0x500>;
2275			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2276			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2277				 <&gcc GCC_BLSP1_AHB_CLK>;
2278			clock-names = "core", "iface";
2279			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2280			dma-names = "tx", "rx";
2281			pinctrl-names = "default", "sleep";
2282			pinctrl-0 = <&blsp_spi5_default>;
2283			pinctrl-1 = <&blsp_spi5_sleep>;
2284			#address-cells = <1>;
2285			#size-cells = <0>;
2286			status = "disabled";
2287		};
2288
2289		blsp_i2c6: i2c@78ba000 {
2290			compatible = "qcom,i2c-qup-v2.2.1";
2291			reg = <0x078ba000 0x500>;
2292			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2293			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2294				 <&gcc GCC_BLSP1_AHB_CLK>;
2295			clock-names = "core", "iface";
2296			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2297			dma-names = "tx", "rx";
2298			pinctrl-names = "default", "sleep";
2299			pinctrl-0 = <&blsp_i2c6_default>;
2300			pinctrl-1 = <&blsp_i2c6_sleep>;
2301			#address-cells = <1>;
2302			#size-cells = <0>;
2303			status = "disabled";
2304		};
2305
2306		blsp_spi6: spi@78ba000 {
2307			compatible = "qcom,spi-qup-v2.2.1";
2308			reg = <0x078ba000 0x500>;
2309			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2310			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2311				 <&gcc GCC_BLSP1_AHB_CLK>;
2312			clock-names = "core", "iface";
2313			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2314			dma-names = "tx", "rx";
2315			pinctrl-names = "default", "sleep";
2316			pinctrl-0 = <&blsp_spi6_default>;
2317			pinctrl-1 = <&blsp_spi6_sleep>;
2318			#address-cells = <1>;
2319			#size-cells = <0>;
2320			status = "disabled";
2321		};
2322
2323		usb: usb@78d9000 {
2324			compatible = "qcom,ci-hdrc";
2325			reg = <0x078d9000 0x200>,
2326			      <0x078d9200 0x200>;
2327			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2328				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2329			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2330				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
2331			clock-names = "iface", "core";
2332			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2333			assigned-clock-rates = <80000000>;
2334			resets = <&gcc GCC_USB_HS_BCR>;
2335			reset-names = "core";
2336			phy_type = "ulpi";
2337			dr_mode = "otg";
2338			hnp-disable;
2339			srp-disable;
2340			adp-disable;
2341			ahb-burst-config = <0>;
2342			phy-names = "usb-phy";
2343			phys = <&usb_hs_phy>;
2344			status = "disabled";
2345			#reset-cells = <1>;
2346
2347			ulpi {
2348				usb_hs_phy: phy {
2349					compatible = "qcom,usb-hs-phy-msm8916",
2350						     "qcom,usb-hs-phy";
2351					#phy-cells = <0>;
2352					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2353					clock-names = "ref", "sleep";
2354					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2355					reset-names = "phy", "por";
2356					qcom,init-seq = /bits/ 8 <0x0 0x44>,
2357								 <0x1 0x6b>,
2358								 <0x2 0x24>,
2359								 <0x3 0x13>;
2360				};
2361			};
2362		};
2363
2364		wcnss: remoteproc@a204000 {
2365			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2366			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2367			reg-names = "ccu", "dxe", "pmu";
2368
2369			memory-region = <&wcnss_mem>;
2370
2371			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2372					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2373					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2374					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2375					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2376			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2377
2378			power-domains = <&rpmpd MSM8916_VDDCX>,
2379					<&rpmpd MSM8916_VDDMX>;
2380			power-domain-names = "cx", "mx";
2381
2382			qcom,smem-states = <&wcnss_smp2p_out 0>;
2383			qcom,smem-state-names = "stop";
2384
2385			pinctrl-names = "default";
2386			pinctrl-0 = <&wcss_wlan_default>;
2387
2388			status = "disabled";
2389
2390			wcnss_iris: iris {
2391				/* Separate chip, compatible is board-specific */
2392				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2393				clock-names = "xo";
2394			};
2395
2396			smd-edge {
2397				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2398
2399				qcom,ipc = <&apcs 8 17>;
2400				qcom,smd-edge = <6>;
2401				qcom,remote-pid = <4>;
2402
2403				label = "pronto";
2404
2405				wcnss_ctrl: wcnss {
2406					compatible = "qcom,wcnss";
2407					qcom,smd-channels = "WCNSS_CTRL";
2408
2409					qcom,mmio = <&wcnss>;
2410
2411					wcnss_bt: bluetooth {
2412						compatible = "qcom,wcnss-bt";
2413					};
2414
2415					wcnss_wifi: wifi {
2416						compatible = "qcom,wcnss-wlan";
2417
2418						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2419							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2420						interrupt-names = "tx", "rx";
2421
2422						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2423						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2424					};
2425				};
2426			};
2427		};
2428
2429		intc: interrupt-controller@b000000 {
2430			compatible = "qcom,msm-qgic2";
2431			interrupt-controller;
2432			#interrupt-cells = <3>;
2433			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2434			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2435			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2436		};
2437
2438		apcs: mailbox@b011000 {
2439			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2440			reg = <0x0b011000 0x1000>;
2441			#mbox-cells = <1>;
2442			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2443			clock-names = "pll", "aux";
2444			#clock-cells = <0>;
2445		};
2446
2447		a53pll: clock@b016000 {
2448			compatible = "qcom,msm8916-a53pll";
2449			reg = <0x0b016000 0x40>;
2450			#clock-cells = <0>;
2451			clocks = <&xo_board>;
2452			clock-names = "xo";
2453		};
2454
2455		timer@b020000 {
2456			#address-cells = <1>;
2457			#size-cells = <1>;
2458			ranges;
2459			compatible = "arm,armv7-timer-mem";
2460			reg = <0x0b020000 0x1000>;
2461			clock-frequency = <19200000>;
2462
2463			frame@b021000 {
2464				frame-number = <0>;
2465				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2466					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2467				reg = <0x0b021000 0x1000>,
2468				      <0x0b022000 0x1000>;
2469			};
2470
2471			frame@b023000 {
2472				frame-number = <1>;
2473				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2474				reg = <0x0b023000 0x1000>;
2475				status = "disabled";
2476			};
2477
2478			frame@b024000 {
2479				frame-number = <2>;
2480				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2481				reg = <0x0b024000 0x1000>;
2482				status = "disabled";
2483			};
2484
2485			frame@b025000 {
2486				frame-number = <3>;
2487				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2488				reg = <0x0b025000 0x1000>;
2489				status = "disabled";
2490			};
2491
2492			frame@b026000 {
2493				frame-number = <4>;
2494				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2495				reg = <0x0b026000 0x1000>;
2496				status = "disabled";
2497			};
2498
2499			frame@b027000 {
2500				frame-number = <5>;
2501				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2502				reg = <0x0b027000 0x1000>;
2503				status = "disabled";
2504			};
2505
2506			frame@b028000 {
2507				frame-number = <6>;
2508				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2509				reg = <0x0b028000 0x1000>;
2510				status = "disabled";
2511			};
2512		};
2513
2514		cpu0_acc: power-manager@b088000 {
2515			compatible = "qcom,msm8916-acc";
2516			reg = <0x0b088000 0x1000>;
2517			status = "reserved"; /* Controlled by PSCI firmware */
2518		};
2519
2520		cpu0_saw: power-manager@b089000 {
2521			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2522			reg = <0x0b089000 0x1000>;
2523			status = "reserved"; /* Controlled by PSCI firmware */
2524		};
2525
2526		cpu1_acc: power-manager@b098000 {
2527			compatible = "qcom,msm8916-acc";
2528			reg = <0x0b098000 0x1000>;
2529			status = "reserved"; /* Controlled by PSCI firmware */
2530		};
2531
2532		cpu1_saw: power-manager@b099000 {
2533			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2534			reg = <0x0b099000 0x1000>;
2535			status = "reserved"; /* Controlled by PSCI firmware */
2536		};
2537
2538		cpu2_acc: power-manager@b0a8000 {
2539			compatible = "qcom,msm8916-acc";
2540			reg = <0x0b0a8000 0x1000>;
2541			status = "reserved"; /* Controlled by PSCI firmware */
2542		};
2543
2544		cpu2_saw: power-manager@b0a9000 {
2545			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2546			reg = <0x0b0a9000 0x1000>;
2547			status = "reserved"; /* Controlled by PSCI firmware */
2548		};
2549
2550		cpu3_acc: power-manager@b0b8000 {
2551			compatible = "qcom,msm8916-acc";
2552			reg = <0x0b0b8000 0x1000>;
2553			status = "reserved"; /* Controlled by PSCI firmware */
2554		};
2555
2556		cpu3_saw: power-manager@b0b9000 {
2557			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2558			reg = <0x0b0b9000 0x1000>;
2559			status = "reserved"; /* Controlled by PSCI firmware */
2560		};
2561	};
2562
2563	thermal-zones {
2564		cpu0-1-thermal {
2565			polling-delay-passive = <250>;
2566			polling-delay = <1000>;
2567
2568			thermal-sensors = <&tsens 5>;
2569
2570			trips {
2571				cpu0_1_alert0: trip-point0 {
2572					temperature = <75000>;
2573					hysteresis = <2000>;
2574					type = "passive";
2575				};
2576				cpu0_1_crit: cpu-crit {
2577					temperature = <110000>;
2578					hysteresis = <2000>;
2579					type = "critical";
2580				};
2581			};
2582
2583			cooling-maps {
2584				map0 {
2585					trip = <&cpu0_1_alert0>;
2586					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2587							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2588							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2589							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2590				};
2591			};
2592		};
2593
2594		cpu2-3-thermal {
2595			polling-delay-passive = <250>;
2596			polling-delay = <1000>;
2597
2598			thermal-sensors = <&tsens 4>;
2599
2600			trips {
2601				cpu2_3_alert0: trip-point0 {
2602					temperature = <75000>;
2603					hysteresis = <2000>;
2604					type = "passive";
2605				};
2606				cpu2_3_crit: cpu-crit {
2607					temperature = <110000>;
2608					hysteresis = <2000>;
2609					type = "critical";
2610				};
2611			};
2612
2613			cooling-maps {
2614				map0 {
2615					trip = <&cpu2_3_alert0>;
2616					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2617							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2618							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2619							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2620				};
2621			};
2622		};
2623
2624		gpu-thermal {
2625			polling-delay-passive = <250>;
2626			polling-delay = <1000>;
2627
2628			thermal-sensors = <&tsens 2>;
2629
2630			trips {
2631				gpu_alert0: trip-point0 {
2632					temperature = <75000>;
2633					hysteresis = <2000>;
2634					type = "passive";
2635				};
2636				gpu_crit: gpu-crit {
2637					temperature = <95000>;
2638					hysteresis = <2000>;
2639					type = "critical";
2640				};
2641			};
2642		};
2643
2644		camera-thermal {
2645			polling-delay-passive = <250>;
2646			polling-delay = <1000>;
2647
2648			thermal-sensors = <&tsens 1>;
2649
2650			trips {
2651				cam_alert0: trip-point0 {
2652					temperature = <75000>;
2653					hysteresis = <2000>;
2654					type = "hot";
2655				};
2656			};
2657		};
2658
2659		modem-thermal {
2660			polling-delay-passive = <250>;
2661			polling-delay = <1000>;
2662
2663			thermal-sensors = <&tsens 0>;
2664
2665			trips {
2666				modem_alert0: trip-point0 {
2667					temperature = <85000>;
2668					hysteresis = <2000>;
2669					type = "hot";
2670				};
2671			};
2672		};
2673	};
2674
2675	timer {
2676		compatible = "arm,armv8-timer";
2677		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2678			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2679			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2680			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2681	};
2682};
2683