1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #include <linux/cpu.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/sched/task_stack.h>
11 #include <linux/sched/hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/smp.h>
14 #include <linux/types.h>
15 #include <linux/irq.h>
16
17 #include <asm/bcache.h>
18 #include <asm/mips-cps.h>
19 #include <asm/mips_mt.h>
20 #include <asm/mipsregs.h>
21 #include <asm/pm-cps.h>
22 #include <asm/r4kcache.h>
23 #include <asm/smp.h>
24 #include <asm/smp-cps.h>
25 #include <asm/time.h>
26 #include <asm/uasm.h>
27
28 static DECLARE_BITMAP(core_power, NR_CPUS);
29
30 struct core_boot_config *mips_cps_core_bootcfg;
31
core_vpe_count(unsigned int cluster,unsigned core)32 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
33 {
34 return min(smp_max_threads, mips_cps_numvps(cluster, core));
35 }
36
cps_smp_setup(void)37 static void __init cps_smp_setup(void)
38 {
39 unsigned int nclusters, ncores, nvpes, core_vpes;
40 unsigned long core_entry;
41 int cl, c, v;
42
43 /* Detect & record VPE topology */
44 nvpes = 0;
45 nclusters = mips_cps_numclusters();
46 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
47 for (cl = 0; cl < nclusters; cl++) {
48 if (cl > 0)
49 pr_cont(",");
50 pr_cont("{");
51
52 ncores = mips_cps_numcores(cl);
53 for (c = 0; c < ncores; c++) {
54 core_vpes = core_vpe_count(cl, c);
55
56 if (c > 0)
57 pr_cont(",");
58 pr_cont("%u", core_vpes);
59
60 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
61 if (!cl && !c)
62 smp_num_siblings = core_vpes;
63
64 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
65 cpu_set_cluster(&cpu_data[nvpes + v], cl);
66 cpu_set_core(&cpu_data[nvpes + v], c);
67 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
68 }
69
70 nvpes += core_vpes;
71 }
72
73 pr_cont("}");
74 }
75 pr_cont(" total %u\n", nvpes);
76
77 /* Indicate present CPUs (CPU being synonymous with VPE) */
78 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
79 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
80 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
81 __cpu_number_map[v] = v;
82 __cpu_logical_map[v] = v;
83 }
84
85 /* Set a coherent default CCA (CWB) */
86 change_c0_config(CONF_CM_CMASK, 0x5);
87
88 /* Core 0 is powered up (we're running on it) */
89 bitmap_set(core_power, 0, 1);
90
91 /* Initialise core 0 */
92 mips_cps_core_init();
93
94 /* Make core 0 coherent with everything */
95 write_gcr_cl_coherence(0xff);
96
97 if (mips_cm_revision() >= CM_REV_CM3) {
98 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
99 write_gcr_bev_base(core_entry);
100 }
101
102 #ifdef CONFIG_MIPS_MT_FPAFF
103 /* If we have an FPU, enroll ourselves in the FPU-full mask */
104 if (cpu_has_fpu)
105 cpumask_set_cpu(0, &mt_fpu_cpumask);
106 #endif /* CONFIG_MIPS_MT_FPAFF */
107 }
108
cps_prepare_cpus(unsigned int max_cpus)109 static void __init cps_prepare_cpus(unsigned int max_cpus)
110 {
111 unsigned ncores, core_vpes, c, cca;
112 bool cca_unsuitable, cores_limited;
113 u32 *entry_code;
114
115 mips_mt_set_cpuoptions();
116
117 /* Detect whether the CCA is unsuited to multi-core SMP */
118 cca = read_c0_config() & CONF_CM_CMASK;
119 switch (cca) {
120 case 0x4: /* CWBE */
121 case 0x5: /* CWB */
122 /* The CCA is coherent, multi-core is fine */
123 cca_unsuitable = false;
124 break;
125
126 default:
127 /* CCA is not coherent, multi-core is not usable */
128 cca_unsuitable = true;
129 }
130
131 /* Warn the user if the CCA prevents multi-core */
132 cores_limited = false;
133 if (cca_unsuitable || cpu_has_dc_aliases) {
134 for_each_present_cpu(c) {
135 if (cpus_are_siblings(smp_processor_id(), c))
136 continue;
137
138 set_cpu_present(c, false);
139 cores_limited = true;
140 }
141 }
142 if (cores_limited)
143 pr_warn("Using only one core due to %s%s%s\n",
144 cca_unsuitable ? "unsuitable CCA" : "",
145 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
146 cpu_has_dc_aliases ? "dcache aliasing" : "");
147
148 /*
149 * Patch the start of mips_cps_core_entry to provide:
150 *
151 * s0 = kseg0 CCA
152 */
153 entry_code = (u32 *)&mips_cps_core_entry;
154 uasm_i_addiu(&entry_code, 16, 0, cca);
155 UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
156 BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
157 blast_dcache_range((unsigned long)&mips_cps_core_entry,
158 (unsigned long)entry_code);
159 bc_wback_inv((unsigned long)&mips_cps_core_entry,
160 (void *)entry_code - (void *)&mips_cps_core_entry);
161 __sync();
162
163 /* Allocate core boot configuration structs */
164 ncores = mips_cps_numcores(0);
165 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
166 GFP_KERNEL);
167 if (!mips_cps_core_bootcfg) {
168 pr_err("Failed to allocate boot config for %u cores\n", ncores);
169 goto err_out;
170 }
171
172 /* Allocate VPE boot configuration structs */
173 for (c = 0; c < ncores; c++) {
174 core_vpes = core_vpe_count(0, c);
175 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
176 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
177 GFP_KERNEL);
178 if (!mips_cps_core_bootcfg[c].vpe_config) {
179 pr_err("Failed to allocate %u VPE boot configs\n",
180 core_vpes);
181 goto err_out;
182 }
183 }
184
185 /* Mark this CPU as booted */
186 atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
187 1 << cpu_vpe_id(¤t_cpu_data));
188
189 return;
190 err_out:
191 /* Clean up allocations */
192 if (mips_cps_core_bootcfg) {
193 for (c = 0; c < ncores; c++)
194 kfree(mips_cps_core_bootcfg[c].vpe_config);
195 kfree(mips_cps_core_bootcfg);
196 mips_cps_core_bootcfg = NULL;
197 }
198
199 /* Effectively disable SMP by declaring CPUs not present */
200 for_each_possible_cpu(c) {
201 if (c == 0)
202 continue;
203 set_cpu_present(c, false);
204 }
205 }
206
boot_core(unsigned int core,unsigned int vpe_id)207 static void boot_core(unsigned int core, unsigned int vpe_id)
208 {
209 u32 stat, seq_state;
210 unsigned timeout;
211
212 /* Select the appropriate core */
213 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
214
215 /* Set its reset vector */
216 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
217
218 /* Ensure its coherency is disabled */
219 write_gcr_co_coherence(0);
220
221 /* Start it with the legacy memory map and exception base */
222 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
223
224 /* Ensure the core can access the GCRs */
225 if (mips_cm_revision() < CM_REV_CM3)
226 set_gcr_access(1 << core);
227 else
228 set_gcr_access_cm3(1 << core);
229
230 if (mips_cpc_present()) {
231 /* Reset the core */
232 mips_cpc_lock_other(core);
233
234 if (mips_cm_revision() >= CM_REV_CM3) {
235 /* Run only the requested VP following the reset */
236 write_cpc_co_vp_stop(0xf);
237 write_cpc_co_vp_run(1 << vpe_id);
238
239 /*
240 * Ensure that the VP_RUN register is written before the
241 * core leaves reset.
242 */
243 wmb();
244 }
245
246 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
247
248 timeout = 100;
249 while (true) {
250 stat = read_cpc_co_stat_conf();
251 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
252 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
253
254 /* U6 == coherent execution, ie. the core is up */
255 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
256 break;
257
258 /* Delay a little while before we start warning */
259 if (timeout) {
260 timeout--;
261 mdelay(10);
262 continue;
263 }
264
265 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
266 core, stat);
267 mdelay(1000);
268 }
269
270 mips_cpc_unlock_other();
271 } else {
272 /* Take the core out of reset */
273 write_gcr_co_reset_release(0);
274 }
275
276 mips_cm_unlock_other();
277
278 /* The core is now powered up */
279 bitmap_set(core_power, core, 1);
280 }
281
remote_vpe_boot(void * dummy)282 static void remote_vpe_boot(void *dummy)
283 {
284 unsigned core = cpu_core(¤t_cpu_data);
285 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
286
287 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
288 }
289
cps_boot_secondary(int cpu,struct task_struct * idle)290 static int cps_boot_secondary(int cpu, struct task_struct *idle)
291 {
292 unsigned core = cpu_core(&cpu_data[cpu]);
293 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
294 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
295 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
296 unsigned long core_entry;
297 unsigned int remote;
298 int err;
299
300 /* We don't yet support booting CPUs in other clusters */
301 if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
302 return -ENOSYS;
303
304 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
305 vpe_cfg->sp = __KSTK_TOS(idle);
306 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
307
308 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
309
310 preempt_disable();
311
312 if (!test_bit(core, core_power)) {
313 /* Boot a VPE on a powered down core */
314 boot_core(core, vpe_id);
315 goto out;
316 }
317
318 if (cpu_has_vp) {
319 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
320 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
321 write_gcr_co_reset_base(core_entry);
322 mips_cm_unlock_other();
323 }
324
325 if (!cpus_are_siblings(cpu, smp_processor_id())) {
326 /* Boot a VPE on another powered up core */
327 for (remote = 0; remote < NR_CPUS; remote++) {
328 if (!cpus_are_siblings(cpu, remote))
329 continue;
330 if (cpu_online(remote))
331 break;
332 }
333 if (remote >= NR_CPUS) {
334 pr_crit("No online CPU in core %u to start CPU%d\n",
335 core, cpu);
336 goto out;
337 }
338
339 err = smp_call_function_single(remote, remote_vpe_boot,
340 NULL, 1);
341 if (err)
342 panic("Failed to call remote CPU\n");
343 goto out;
344 }
345
346 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
347
348 /* Boot a VPE on this core */
349 mips_cps_boot_vpes(core_cfg, vpe_id);
350 out:
351 preempt_enable();
352 return 0;
353 }
354
cps_init_secondary(void)355 static void cps_init_secondary(void)
356 {
357 int core = cpu_core(¤t_cpu_data);
358
359 /* Disable MT - we only want to run 1 TC per VPE */
360 if (cpu_has_mipsmt)
361 dmt();
362
363 if (mips_cm_revision() >= CM_REV_CM3) {
364 unsigned int ident = read_gic_vl_ident();
365
366 /*
367 * Ensure that our calculation of the VP ID matches up with
368 * what the GIC reports, otherwise we'll have configured
369 * interrupts incorrectly.
370 */
371 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
372 }
373
374 if (core > 0 && !read_gcr_cl_coherence())
375 pr_warn("Core %u is not in coherent domain\n", core);
376
377 if (cpu_has_veic)
378 clear_c0_status(ST0_IM);
379 else
380 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
381 STATUSF_IP4 | STATUSF_IP5 |
382 STATUSF_IP6 | STATUSF_IP7);
383 }
384
cps_smp_finish(void)385 static void cps_smp_finish(void)
386 {
387 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
388
389 #ifdef CONFIG_MIPS_MT_FPAFF
390 /* If we have an FPU, enroll ourselves in the FPU-full mask */
391 if (cpu_has_fpu)
392 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
393 #endif /* CONFIG_MIPS_MT_FPAFF */
394
395 local_irq_enable();
396 }
397
398 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
399
400 enum cpu_death {
401 CPU_DEATH_HALT,
402 CPU_DEATH_POWER,
403 };
404
cps_shutdown_this_cpu(enum cpu_death death)405 static void cps_shutdown_this_cpu(enum cpu_death death)
406 {
407 unsigned int cpu, core, vpe_id;
408
409 cpu = smp_processor_id();
410 core = cpu_core(&cpu_data[cpu]);
411
412 if (death == CPU_DEATH_HALT) {
413 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
414
415 pr_debug("Halting core %d VP%d\n", core, vpe_id);
416 if (cpu_has_mipsmt) {
417 /* Halt this TC */
418 write_c0_tchalt(TCHALT_H);
419 instruction_hazard();
420 } else if (cpu_has_vp) {
421 write_cpc_cl_vp_stop(1 << vpe_id);
422
423 /* Ensure that the VP_STOP register is written */
424 wmb();
425 }
426 } else {
427 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
428 pr_debug("Gating power to core %d\n", core);
429 /* Power down the core */
430 cps_pm_enter_state(CPS_PM_POWER_GATED);
431 }
432 }
433 }
434
435 #ifdef CONFIG_KEXEC
436
cps_kexec_nonboot_cpu(void)437 static void cps_kexec_nonboot_cpu(void)
438 {
439 if (cpu_has_mipsmt || cpu_has_vp)
440 cps_shutdown_this_cpu(CPU_DEATH_HALT);
441 else
442 cps_shutdown_this_cpu(CPU_DEATH_POWER);
443 }
444
445 #endif /* CONFIG_KEXEC */
446
447 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
448
449 #ifdef CONFIG_HOTPLUG_CPU
450
cps_cpu_disable(void)451 static int cps_cpu_disable(void)
452 {
453 unsigned cpu = smp_processor_id();
454 struct core_boot_config *core_cfg;
455
456 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
457 return -EINVAL;
458
459 core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
460 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
461 smp_mb__after_atomic();
462 set_cpu_online(cpu, false);
463 calculate_cpu_foreign_map();
464 irq_migrate_all_off_this_cpu();
465
466 return 0;
467 }
468
469 static unsigned cpu_death_sibling;
470 static enum cpu_death cpu_death;
471
play_dead(void)472 void play_dead(void)
473 {
474 unsigned int cpu;
475
476 local_irq_disable();
477 idle_task_exit();
478 cpu = smp_processor_id();
479 cpu_death = CPU_DEATH_POWER;
480
481 pr_debug("CPU%d going offline\n", cpu);
482
483 if (cpu_has_mipsmt || cpu_has_vp) {
484 /* Look for another online VPE within the core */
485 for_each_online_cpu(cpu_death_sibling) {
486 if (!cpus_are_siblings(cpu, cpu_death_sibling))
487 continue;
488
489 /*
490 * There is an online VPE within the core. Just halt
491 * this TC and leave the core alone.
492 */
493 cpu_death = CPU_DEATH_HALT;
494 break;
495 }
496 }
497
498 cpuhp_ap_report_dead();
499
500 cps_shutdown_this_cpu(cpu_death);
501
502 /* This should never be reached */
503 panic("Failed to offline CPU %u", cpu);
504 }
505
wait_for_sibling_halt(void * ptr_cpu)506 static void wait_for_sibling_halt(void *ptr_cpu)
507 {
508 unsigned cpu = (unsigned long)ptr_cpu;
509 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
510 unsigned halted;
511 unsigned long flags;
512
513 do {
514 local_irq_save(flags);
515 settc(vpe_id);
516 halted = read_tc_c0_tchalt();
517 local_irq_restore(flags);
518 } while (!(halted & TCHALT_H));
519 }
520
cps_cpu_die(unsigned int cpu)521 static void cps_cpu_die(unsigned int cpu) { }
522
cps_cleanup_dead_cpu(unsigned cpu)523 static void cps_cleanup_dead_cpu(unsigned cpu)
524 {
525 unsigned core = cpu_core(&cpu_data[cpu]);
526 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
527 ktime_t fail_time;
528 unsigned stat;
529 int err;
530
531 /*
532 * Now wait for the CPU to actually offline. Without doing this that
533 * offlining may race with one or more of:
534 *
535 * - Onlining the CPU again.
536 * - Powering down the core if another VPE within it is offlined.
537 * - A sibling VPE entering a non-coherent state.
538 *
539 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
540 * with which we could race, so do nothing.
541 */
542 if (cpu_death == CPU_DEATH_POWER) {
543 /*
544 * Wait for the core to enter a powered down or clock gated
545 * state, the latter happening when a JTAG probe is connected
546 * in which case the CPC will refuse to power down the core.
547 */
548 fail_time = ktime_add_ms(ktime_get(), 2000);
549 do {
550 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
551 mips_cpc_lock_other(core);
552 stat = read_cpc_co_stat_conf();
553 stat &= CPC_Cx_STAT_CONF_SEQSTATE;
554 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
555 mips_cpc_unlock_other();
556 mips_cm_unlock_other();
557
558 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
559 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
560 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
561 break;
562
563 /*
564 * The core ought to have powered down, but didn't &
565 * now we don't really know what state it's in. It's
566 * likely that its _pwr_up pin has been wired to logic
567 * 1 & it powered back up as soon as we powered it
568 * down...
569 *
570 * The best we can do is warn the user & continue in
571 * the hope that the core is doing nothing harmful &
572 * might behave properly if we online it later.
573 */
574 if (WARN(ktime_after(ktime_get(), fail_time),
575 "CPU%u hasn't powered down, seq. state %u\n",
576 cpu, stat))
577 break;
578 } while (1);
579
580 /* Indicate the core is powered off */
581 bitmap_clear(core_power, core, 1);
582 } else if (cpu_has_mipsmt) {
583 /*
584 * Have a CPU with access to the offlined CPUs registers wait
585 * for its TC to halt.
586 */
587 err = smp_call_function_single(cpu_death_sibling,
588 wait_for_sibling_halt,
589 (void *)(unsigned long)cpu, 1);
590 if (err)
591 panic("Failed to call remote sibling CPU\n");
592 } else if (cpu_has_vp) {
593 do {
594 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
595 stat = read_cpc_co_vp_running();
596 mips_cm_unlock_other();
597 } while (stat & (1 << vpe_id));
598 }
599 }
600
601 #endif /* CONFIG_HOTPLUG_CPU */
602
603 static const struct plat_smp_ops cps_smp_ops = {
604 .smp_setup = cps_smp_setup,
605 .prepare_cpus = cps_prepare_cpus,
606 .boot_secondary = cps_boot_secondary,
607 .init_secondary = cps_init_secondary,
608 .smp_finish = cps_smp_finish,
609 .send_ipi_single = mips_smp_send_ipi_single,
610 .send_ipi_mask = mips_smp_send_ipi_mask,
611 #ifdef CONFIG_HOTPLUG_CPU
612 .cpu_disable = cps_cpu_disable,
613 .cpu_die = cps_cpu_die,
614 .cleanup_dead_cpu = cps_cleanup_dead_cpu,
615 #endif
616 #ifdef CONFIG_KEXEC
617 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu,
618 #endif
619 };
620
mips_cps_smp_in_use(void)621 bool mips_cps_smp_in_use(void)
622 {
623 extern const struct plat_smp_ops *mp_ops;
624 return mp_ops == &cps_smp_ops;
625 }
626
register_cps_smp_ops(void)627 int register_cps_smp_ops(void)
628 {
629 if (!mips_cm_present()) {
630 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
631 return -ENODEV;
632 }
633
634 /* check we have a GIC - we need one for IPIs */
635 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
636 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
637 return -ENODEV;
638 }
639
640 register_smp_ops(&cps_smp_ops);
641 return 0;
642 }
643