xref: /openbmc/u-boot/arch/arm/dts/zynqmp-clk.dtsi (revision 3b52847a451a81001b578353e793d7d9739b69d6) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Clock specification for Xilinx ZynqMP
4  *
5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
6  *
7  * Michal Simek <michal.simek@xilinx.com>
8  */
9 
10 / {
11 	clk100: clk100 {
12 		compatible = "fixed-clock";
13 		#clock-cells = <0>;
14 		clock-frequency = <100000000>;
15 		u-boot,dm-pre-reloc;
16 	};
17 
18 	clk125: clk125 {
19 		compatible = "fixed-clock";
20 		#clock-cells = <0>;
21 		clock-frequency = <125000000>;
22 	};
23 
24 	clk200: clk200 {
25 		compatible = "fixed-clock";
26 		#clock-cells = <0>;
27 		clock-frequency = <200000000>;
28 		u-boot,dm-pre-reloc;
29 	};
30 
31 	clk250: clk250 {
32 		compatible = "fixed-clock";
33 		#clock-cells = <0>;
34 		clock-frequency = <250000000>;
35 	};
36 
37 	clk300: clk300 {
38 		compatible = "fixed-clock";
39 		#clock-cells = <0>;
40 		clock-frequency = <300000000>;
41 	};
42 
43 	clk600: clk600 {
44 		compatible = "fixed-clock";
45 		#clock-cells = <0>;
46 		clock-frequency = <600000000>;
47 	};
48 
49 	dp_aclk: clock0 {
50 		compatible = "fixed-clock";
51 		#clock-cells = <0>;
52 		clock-frequency = <100000000>;
53 		clock-accuracy = <100>;
54 	};
55 
56 	dp_aud_clk: clock1 {
57 		compatible = "fixed-clock";
58 		#clock-cells = <0>;
59 		clock-frequency = <24576000>;
60 		clock-accuracy = <100>;
61 	};
62 
63 	dpdma_clk: dpdma_clk {
64 		compatible = "fixed-clock";
65 		#clock-cells = <0x0>;
66 		clock-frequency = <533000000>;
67 	};
68 
69 	drm_clock: drm_clock {
70 		compatible = "fixed-clock";
71 		#clock-cells = <0x0>;
72 		clock-frequency = <262750000>;
73 		clock-accuracy = <0x64>;
74 	};
75 };
76 
77 &can0 {
78 	clocks = <&clk100 &clk100>;
79 };
80 
81 &can1 {
82 	clocks = <&clk100 &clk100>;
83 };
84 
85 &fpd_dma_chan1 {
86 	clocks = <&clk600>, <&clk100>;
87 };
88 
89 &fpd_dma_chan2 {
90 	clocks = <&clk600>, <&clk100>;
91 };
92 
93 &fpd_dma_chan3 {
94 	clocks = <&clk600>, <&clk100>;
95 };
96 
97 &fpd_dma_chan4 {
98 	clocks = <&clk600>, <&clk100>;
99 };
100 
101 &fpd_dma_chan5 {
102 	clocks = <&clk600>, <&clk100>;
103 };
104 
105 &fpd_dma_chan6 {
106 	clocks = <&clk600>, <&clk100>;
107 };
108 
109 &fpd_dma_chan7 {
110 	clocks = <&clk600>, <&clk100>;
111 };
112 
113 &fpd_dma_chan8 {
114 	clocks = <&clk600>, <&clk100>;
115 };
116 
117 &lpd_dma_chan1 {
118 	clocks = <&clk600>, <&clk100>;
119 };
120 
121 &lpd_dma_chan2 {
122 	clocks = <&clk600>, <&clk100>;
123 };
124 
125 &lpd_dma_chan3 {
126 	clocks = <&clk600>, <&clk100>;
127 };
128 
129 &lpd_dma_chan4 {
130 	clocks = <&clk600>, <&clk100>;
131 };
132 
133 &lpd_dma_chan5 {
134 	clocks = <&clk600>, <&clk100>;
135 };
136 
137 &lpd_dma_chan6 {
138 	clocks = <&clk600>, <&clk100>;
139 };
140 
141 &lpd_dma_chan7 {
142 	clocks = <&clk600>, <&clk100>;
143 };
144 
145 &lpd_dma_chan8 {
146 	clocks = <&clk600>, <&clk100>;
147 };
148 
149 &nand0 {
150 	clocks = <&clk100 &clk100>;
151 };
152 
153 &gem0 {
154 	clocks = <&clk125>, <&clk125>, <&clk125>;
155 };
156 
157 &gem1 {
158 	clocks = <&clk125>, <&clk125>, <&clk125>;
159 };
160 
161 &gem2 {
162 	clocks = <&clk125>, <&clk125>, <&clk125>;
163 };
164 
165 &gem3 {
166 	clocks = <&clk125>, <&clk125>, <&clk125>;
167 };
168 
169 &gpio {
170 	clocks = <&clk100>;
171 };
172 
173 &i2c0 {
174 	clocks = <&clk100>;
175 };
176 
177 &i2c1 {
178 	clocks = <&clk100>;
179 };
180 
181 &qspi {
182 	clocks = <&clk300 &clk300>;
183 };
184 
185 &sata {
186 	clocks = <&clk250>;
187 };
188 
189 &sdhci0 {
190 	clocks = <&clk200 &clk200>;
191 };
192 
193 &sdhci1 {
194 	clocks = <&clk200 &clk200>;
195 };
196 
197 &spi0 {
198 	clocks = <&clk200 &clk200>;
199 };
200 
201 &spi1 {
202 	clocks = <&clk200 &clk200>;
203 };
204 
205 &uart0 {
206 	clocks = <&clk100 &clk100>;
207 };
208 
209 &uart1 {
210 	clocks = <&clk100 &clk100>;
211 };
212 
213 &usb0 {
214 	clocks = <&clk250>, <&clk250>;
215 };
216 
217 &usb1 {
218 	clocks = <&clk250>, <&clk250>;
219 };
220 
221 &watchdog0 {
222 	clocks = <&clk100>;
223 };
224 
225 &xilinx_drm {
226 	clocks = <&drm_clock>;
227 };
228 
229 &xlnx_dp {
230 	clocks = <&dp_aclk>, <&dp_aud_clk>;
231 };
232 
233 &xlnx_dpdma {
234 	clocks = <&dpdma_clk>;
235 };
236 
237 &xlnx_dp_snd_codec0 {
238 	clocks = <&dp_aud_clk>;
239 };
240