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Searched defs:cl_value (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c344 u32 cl_value = 0, cwl_val = 0; in hws_ddr3_tip_init_controller() local
1199 u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, in ddr3_tip_freq_set() local
1587 u32 if_id, u32 cl_value, u32 cwl_value) in ddr3_tip_write_odt()