1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 &cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 20 tifs-sram@1f0000 { 21 reg = <0x1f0000 0x10000>; 22 }; 23 24 l3cache-sram@200000 { 25 reg = <0x200000 0x200000>; 26 }; 27 }; 28 29 gic500: interrupt-controller@1800000 { 30 compatible = "arm,gic-v3"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 37 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 38 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 39 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 40 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 41 42 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 main_gpio_intr: interrupt-controller@a00000 { 55 compatible = "ti,sci-intr"; 56 reg = <0x00 0x00a00000 0x00 0x800>; 57 ti,intr-trigger-type = <1>; 58 interrupt-controller; 59 interrupt-parent = <&gic500>; 60 #interrupt-cells = <1>; 61 ti,sci = <&sms>; 62 ti,sci-dev-id = <10>; 63 ti,interrupt-ranges = <8 392 56>; 64 }; 65 66 main_pmx0: pinctrl@11c000 { 67 compatible = "pinctrl-single"; 68 /* Proxy 0 addressing */ 69 reg = <0x00 0x11c000 0x00 0x120>; 70 #pinctrl-cells = <1>; 71 pinctrl-single,register-width = <32>; 72 pinctrl-single,function-mask = <0xffffffff>; 73 }; 74 75 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 76 main_timerio_input: pinctrl@104200 { 77 compatible = "pinctrl-single"; 78 reg = <0x00 0x104200 0x00 0x50>; 79 #pinctrl-cells = <1>; 80 pinctrl-single,register-width = <32>; 81 pinctrl-single,function-mask = <0x00000007>; 82 }; 83 84 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 85 main_timerio_output: pinctrl@104280 { 86 compatible = "pinctrl-single"; 87 reg = <0x00 0x104280 0x00 0x20>; 88 #pinctrl-cells = <1>; 89 pinctrl-single,register-width = <32>; 90 pinctrl-single,function-mask = <0x0000001f>; 91 }; 92 93 main_crypto: crypto@4e00000 { 94 compatible = "ti,j721e-sa2ul"; 95 reg = <0x00 0x4e00000 0x00 0x1200>; 96 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 100 101 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 102 <&main_udmap 0x4a41>; 103 dma-names = "tx", "rx1", "rx2"; 104 105 rng: rng@4e10000 { 106 compatible = "inside-secure,safexcel-eip76"; 107 reg = <0x00 0x4e10000 0x00 0x7d>; 108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 109 }; 110 }; 111 112 main_timer0: timer@2400000 { 113 compatible = "ti,am654-timer"; 114 reg = <0x00 0x2400000 0x00 0x400>; 115 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&k3_clks 97 2>; 117 clock-names = "fck"; 118 assigned-clocks = <&k3_clks 97 2>; 119 assigned-clock-parents = <&k3_clks 97 3>; 120 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 121 ti,timer-pwm; 122 }; 123 124 main_timer1: timer@2410000 { 125 compatible = "ti,am654-timer"; 126 reg = <0x00 0x2410000 0x00 0x400>; 127 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&k3_clks 98 2>; 129 clock-names = "fck"; 130 assigned-clocks = <&k3_clks 98 2>; 131 assigned-clock-parents = <&k3_clks 98 3>; 132 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 133 ti,timer-pwm; 134 }; 135 136 main_timer2: timer@2420000 { 137 compatible = "ti,am654-timer"; 138 reg = <0x00 0x2420000 0x00 0x400>; 139 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&k3_clks 99 2>; 141 clock-names = "fck"; 142 assigned-clocks = <&k3_clks 99 2>; 143 assigned-clock-parents = <&k3_clks 99 3>; 144 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 145 ti,timer-pwm; 146 }; 147 148 main_timer3: timer@2430000 { 149 compatible = "ti,am654-timer"; 150 reg = <0x00 0x2430000 0x00 0x400>; 151 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&k3_clks 100 2>; 153 clock-names = "fck"; 154 assigned-clocks = <&k3_clks 100 2>; 155 assigned-clock-parents = <&k3_clks 100 3>; 156 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 157 ti,timer-pwm; 158 }; 159 160 main_timer4: timer@2440000 { 161 compatible = "ti,am654-timer"; 162 reg = <0x00 0x2440000 0x00 0x400>; 163 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&k3_clks 101 2>; 165 clock-names = "fck"; 166 assigned-clocks = <&k3_clks 101 2>; 167 assigned-clock-parents = <&k3_clks 101 3>; 168 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 169 ti,timer-pwm; 170 }; 171 172 main_timer5: timer@2450000 { 173 compatible = "ti,am654-timer"; 174 reg = <0x00 0x2450000 0x00 0x400>; 175 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&k3_clks 102 2>; 177 clock-names = "fck"; 178 assigned-clocks = <&k3_clks 102 2>; 179 assigned-clock-parents = <&k3_clks 102 3>; 180 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 181 ti,timer-pwm; 182 }; 183 184 main_timer6: timer@2460000 { 185 compatible = "ti,am654-timer"; 186 reg = <0x00 0x2460000 0x00 0x400>; 187 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&k3_clks 103 2>; 189 clock-names = "fck"; 190 assigned-clocks = <&k3_clks 103 2>; 191 assigned-clock-parents = <&k3_clks 103 3>; 192 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 193 ti,timer-pwm; 194 }; 195 196 main_timer7: timer@2470000 { 197 compatible = "ti,am654-timer"; 198 reg = <0x00 0x2470000 0x00 0x400>; 199 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&k3_clks 104 2>; 201 clock-names = "fck"; 202 assigned-clocks = <&k3_clks 104 2>; 203 assigned-clock-parents = <&k3_clks 104 3>; 204 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 205 ti,timer-pwm; 206 }; 207 208 main_timer8: timer@2480000 { 209 compatible = "ti,am654-timer"; 210 reg = <0x00 0x2480000 0x00 0x400>; 211 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&k3_clks 105 2>; 213 clock-names = "fck"; 214 assigned-clocks = <&k3_clks 105 2>; 215 assigned-clock-parents = <&k3_clks 105 3>; 216 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 217 ti,timer-pwm; 218 }; 219 220 main_timer9: timer@2490000 { 221 compatible = "ti,am654-timer"; 222 reg = <0x00 0x2490000 0x00 0x400>; 223 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&k3_clks 106 2>; 225 clock-names = "fck"; 226 assigned-clocks = <&k3_clks 106 2>; 227 assigned-clock-parents = <&k3_clks 106 3>; 228 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 229 ti,timer-pwm; 230 }; 231 232 main_timer10: timer@24a0000 { 233 compatible = "ti,am654-timer"; 234 reg = <0x00 0x24a0000 0x00 0x400>; 235 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&k3_clks 107 2>; 237 clock-names = "fck"; 238 assigned-clocks = <&k3_clks 107 2>; 239 assigned-clock-parents = <&k3_clks 107 3>; 240 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 241 ti,timer-pwm; 242 }; 243 244 main_timer11: timer@24b0000 { 245 compatible = "ti,am654-timer"; 246 reg = <0x00 0x24b0000 0x00 0x400>; 247 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&k3_clks 108 2>; 249 clock-names = "fck"; 250 assigned-clocks = <&k3_clks 108 2>; 251 assigned-clock-parents = <&k3_clks 108 3>; 252 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 253 ti,timer-pwm; 254 }; 255 256 main_timer12: timer@24c0000 { 257 compatible = "ti,am654-timer"; 258 reg = <0x00 0x24c0000 0x00 0x400>; 259 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&k3_clks 109 2>; 261 clock-names = "fck"; 262 assigned-clocks = <&k3_clks 109 2>; 263 assigned-clock-parents = <&k3_clks 109 3>; 264 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 265 ti,timer-pwm; 266 }; 267 268 main_timer13: timer@24d0000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x24d0000 0x00 0x400>; 271 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 110 2>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 110 2>; 275 assigned-clock-parents = <&k3_clks 110 3>; 276 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer14: timer@24e0000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x24e0000 0x00 0x400>; 283 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 111 2>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 111 2>; 287 assigned-clock-parents = <&k3_clks 111 3>; 288 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer15: timer@24f0000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x24f0000 0x00 0x400>; 295 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 112 2>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 112 2>; 299 assigned-clock-parents = <&k3_clks 112 3>; 300 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer16: timer@2500000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2500000 0x00 0x400>; 307 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 113 2>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 113 2>; 311 assigned-clock-parents = <&k3_clks 113 3>; 312 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer17: timer@2510000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2510000 0x00 0x400>; 319 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 114 2>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 114 2>; 323 assigned-clock-parents = <&k3_clks 114 3>; 324 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_timer18: timer@2520000 { 329 compatible = "ti,am654-timer"; 330 reg = <0x00 0x2520000 0x00 0x400>; 331 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&k3_clks 115 2>; 333 clock-names = "fck"; 334 assigned-clocks = <&k3_clks 115 2>; 335 assigned-clock-parents = <&k3_clks 115 3>; 336 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 337 ti,timer-pwm; 338 }; 339 340 main_timer19: timer@2530000 { 341 compatible = "ti,am654-timer"; 342 reg = <0x00 0x2530000 0x00 0x400>; 343 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 116 2>; 345 clock-names = "fck"; 346 assigned-clocks = <&k3_clks 116 2>; 347 assigned-clock-parents = <&k3_clks 116 3>; 348 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 349 ti,timer-pwm; 350 }; 351 352 main_uart0: serial@2800000 { 353 compatible = "ti,j721e-uart", "ti,am654-uart"; 354 reg = <0x00 0x02800000 0x00 0x200>; 355 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 356 current-speed = <115200>; 357 clocks = <&k3_clks 146 0>; 358 clock-names = "fclk"; 359 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 360 status = "disabled"; 361 }; 362 363 main_uart1: serial@2810000 { 364 compatible = "ti,j721e-uart", "ti,am654-uart"; 365 reg = <0x00 0x02810000 0x00 0x200>; 366 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 367 current-speed = <115200>; 368 clocks = <&k3_clks 388 0>; 369 clock-names = "fclk"; 370 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 371 status = "disabled"; 372 }; 373 374 main_uart2: serial@2820000 { 375 compatible = "ti,j721e-uart", "ti,am654-uart"; 376 reg = <0x00 0x02820000 0x00 0x200>; 377 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 378 current-speed = <115200>; 379 clocks = <&k3_clks 389 0>; 380 clock-names = "fclk"; 381 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 382 status = "disabled"; 383 }; 384 385 main_uart3: serial@2830000 { 386 compatible = "ti,j721e-uart", "ti,am654-uart"; 387 reg = <0x00 0x02830000 0x00 0x200>; 388 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 389 current-speed = <115200>; 390 clocks = <&k3_clks 390 0>; 391 clock-names = "fclk"; 392 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 393 status = "disabled"; 394 }; 395 396 main_uart4: serial@2840000 { 397 compatible = "ti,j721e-uart", "ti,am654-uart"; 398 reg = <0x00 0x02840000 0x00 0x200>; 399 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 400 current-speed = <115200>; 401 clocks = <&k3_clks 391 0>; 402 clock-names = "fclk"; 403 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 404 status = "disabled"; 405 }; 406 407 main_uart5: serial@2850000 { 408 compatible = "ti,j721e-uart", "ti,am654-uart"; 409 reg = <0x00 0x02850000 0x00 0x200>; 410 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 411 current-speed = <115200>; 412 clocks = <&k3_clks 392 0>; 413 clock-names = "fclk"; 414 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 415 status = "disabled"; 416 }; 417 418 main_uart6: serial@2860000 { 419 compatible = "ti,j721e-uart", "ti,am654-uart"; 420 reg = <0x00 0x02860000 0x00 0x200>; 421 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 422 current-speed = <115200>; 423 clocks = <&k3_clks 393 0>; 424 clock-names = "fclk"; 425 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 426 status = "disabled"; 427 }; 428 429 main_uart7: serial@2870000 { 430 compatible = "ti,j721e-uart", "ti,am654-uart"; 431 reg = <0x00 0x02870000 0x00 0x200>; 432 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 433 current-speed = <115200>; 434 clocks = <&k3_clks 394 0>; 435 clock-names = "fclk"; 436 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 437 status = "disabled"; 438 }; 439 440 main_uart8: serial@2880000 { 441 compatible = "ti,j721e-uart", "ti,am654-uart"; 442 reg = <0x00 0x02880000 0x00 0x200>; 443 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 444 current-speed = <115200>; 445 clocks = <&k3_clks 395 0>; 446 clock-names = "fclk"; 447 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 448 status = "disabled"; 449 }; 450 451 main_uart9: serial@2890000 { 452 compatible = "ti,j721e-uart", "ti,am654-uart"; 453 reg = <0x00 0x02890000 0x00 0x200>; 454 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 455 current-speed = <115200>; 456 clocks = <&k3_clks 396 0>; 457 clock-names = "fclk"; 458 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 459 status = "disabled"; 460 }; 461 462 main_gpio0: gpio@600000 { 463 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 464 reg = <0x00 0x00600000 0x00 0x100>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-parent = <&main_gpio_intr>; 468 interrupts = <145>, <146>, <147>, <148>, <149>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 ti,ngpio = <66>; 472 ti,davinci-gpio-unbanked = <0>; 473 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 474 clocks = <&k3_clks 163 0>; 475 clock-names = "gpio"; 476 status = "disabled"; 477 }; 478 479 main_gpio2: gpio@610000 { 480 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 481 reg = <0x00 0x00610000 0x00 0x100>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-parent = <&main_gpio_intr>; 485 interrupts = <154>, <155>, <156>, <157>, <158>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 ti,ngpio = <66>; 489 ti,davinci-gpio-unbanked = <0>; 490 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 491 clocks = <&k3_clks 164 0>; 492 clock-names = "gpio"; 493 status = "disabled"; 494 }; 495 496 main_gpio4: gpio@620000 { 497 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 498 reg = <0x00 0x00620000 0x00 0x100>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-parent = <&main_gpio_intr>; 502 interrupts = <163>, <164>, <165>, <166>, <167>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 ti,ngpio = <66>; 506 ti,davinci-gpio-unbanked = <0>; 507 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 508 clocks = <&k3_clks 165 0>; 509 clock-names = "gpio"; 510 status = "disabled"; 511 }; 512 513 main_gpio6: gpio@630000 { 514 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 515 reg = <0x00 0x00630000 0x00 0x100>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-parent = <&main_gpio_intr>; 519 interrupts = <172>, <173>, <174>, <175>, <176>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 ti,ngpio = <66>; 523 ti,davinci-gpio-unbanked = <0>; 524 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 525 clocks = <&k3_clks 166 0>; 526 clock-names = "gpio"; 527 status = "disabled"; 528 }; 529 530 main_i2c0: i2c@2000000 { 531 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 532 reg = <0x00 0x02000000 0x00 0x100>; 533 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&k3_clks 270 2>; 537 clock-names = "fck"; 538 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 539 status = "disabled"; 540 }; 541 542 main_i2c1: i2c@2010000 { 543 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 544 reg = <0x00 0x02010000 0x00 0x100>; 545 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&k3_clks 271 2>; 549 clock-names = "fck"; 550 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 551 status = "disabled"; 552 }; 553 554 main_i2c2: i2c@2020000 { 555 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 556 reg = <0x00 0x02020000 0x00 0x100>; 557 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&k3_clks 272 2>; 561 clock-names = "fck"; 562 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 563 status = "disabled"; 564 }; 565 566 main_i2c3: i2c@2030000 { 567 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 568 reg = <0x00 0x02030000 0x00 0x100>; 569 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&k3_clks 273 2>; 573 clock-names = "fck"; 574 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 575 status = "disabled"; 576 }; 577 578 main_i2c4: i2c@2040000 { 579 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 580 reg = <0x00 0x02040000 0x00 0x100>; 581 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&k3_clks 274 2>; 585 clock-names = "fck"; 586 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 587 status = "disabled"; 588 }; 589 590 main_i2c5: i2c@2050000 { 591 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 592 reg = <0x00 0x02050000 0x00 0x100>; 593 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&k3_clks 275 2>; 597 clock-names = "fck"; 598 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 599 status = "disabled"; 600 }; 601 602 main_i2c6: i2c@2060000 { 603 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 604 reg = <0x00 0x02060000 0x00 0x100>; 605 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&k3_clks 276 2>; 609 clock-names = "fck"; 610 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 611 status = "disabled"; 612 }; 613 614 main_sdhci0: mmc@4f80000 { 615 compatible = "ti,j721e-sdhci-8bit"; 616 reg = <0x00 0x04f80000 0x00 0x1000>, 617 <0x00 0x04f88000 0x00 0x400>; 618 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 619 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 620 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 621 clock-names = "clk_ahb", "clk_xin"; 622 assigned-clocks = <&k3_clks 140 2>; 623 assigned-clock-parents = <&k3_clks 140 3>; 624 bus-width = <8>; 625 ti,otap-del-sel-legacy = <0x0>; 626 ti,otap-del-sel-mmc-hs = <0x0>; 627 ti,otap-del-sel-ddr52 = <0x6>; 628 ti,otap-del-sel-hs200 = <0x8>; 629 ti,otap-del-sel-hs400 = <0x5>; 630 ti,itap-del-sel-legacy = <0x10>; 631 ti,itap-del-sel-mmc-hs = <0xa>; 632 ti,strobe-sel = <0x77>; 633 ti,clkbuf-sel = <0x7>; 634 ti,trm-icp = <0x8>; 635 mmc-ddr-1_8v; 636 mmc-hs200-1_8v; 637 mmc-hs400-1_8v; 638 dma-coherent; 639 status = "disabled"; 640 }; 641 642 main_sdhci1: mmc@4fb0000 { 643 compatible = "ti,j721e-sdhci-4bit"; 644 reg = <0x00 0x04fb0000 0x00 0x1000>, 645 <0x00 0x04fb8000 0x00 0x400>; 646 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 647 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 648 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 649 clock-names = "clk_ahb", "clk_xin"; 650 assigned-clocks = <&k3_clks 141 4>; 651 assigned-clock-parents = <&k3_clks 141 5>; 652 bus-width = <4>; 653 ti,otap-del-sel-legacy = <0x0>; 654 ti,otap-del-sel-sd-hs = <0x0>; 655 ti,otap-del-sel-sdr12 = <0xf>; 656 ti,otap-del-sel-sdr25 = <0xf>; 657 ti,otap-del-sel-sdr50 = <0xc>; 658 ti,otap-del-sel-sdr104 = <0x5>; 659 ti,otap-del-sel-ddr50 = <0xc>; 660 ti,itap-del-sel-legacy = <0x0>; 661 ti,itap-del-sel-sd-hs = <0x0>; 662 ti,itap-del-sel-sdr12 = <0x0>; 663 ti,itap-del-sel-sdr25 = <0x0>; 664 ti,clkbuf-sel = <0x7>; 665 ti,trm-icp = <0x8>; 666 dma-coherent; 667 sdhci-caps-mask = <0x00000003 0x00000000>; 668 no-1-8-v; 669 status = "disabled"; 670 }; 671 672 main_navss: bus@30000000 { 673 bootph-all; 674 compatible = "simple-bus"; 675 #address-cells = <2>; 676 #size-cells = <2>; 677 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 678 ti,sci-dev-id = <280>; 679 dma-coherent; 680 dma-ranges; 681 682 main_navss_intr: interrupt-controller@310e0000 { 683 compatible = "ti,sci-intr"; 684 reg = <0x00 0x310e0000 0x00 0x4000>; 685 ti,intr-trigger-type = <4>; 686 interrupt-controller; 687 interrupt-parent = <&gic500>; 688 #interrupt-cells = <1>; 689 ti,sci = <&sms>; 690 ti,sci-dev-id = <283>; 691 ti,interrupt-ranges = <0 64 64>, 692 <64 448 64>, 693 <128 672 64>; 694 }; 695 696 main_udmass_inta: msi-controller@33d00000 { 697 compatible = "ti,sci-inta"; 698 reg = <0x00 0x33d00000 0x00 0x100000>; 699 interrupt-controller; 700 #interrupt-cells = <0>; 701 interrupt-parent = <&main_navss_intr>; 702 msi-controller; 703 ti,sci = <&sms>; 704 ti,sci-dev-id = <321>; 705 ti,interrupt-ranges = <0 0 256>; 706 }; 707 708 secure_proxy_main: mailbox@32c00000 { 709 bootph-all; 710 compatible = "ti,am654-secure-proxy"; 711 #mbox-cells = <1>; 712 reg-names = "target_data", "rt", "scfg"; 713 reg = <0x00 0x32c00000 0x00 0x100000>, 714 <0x00 0x32400000 0x00 0x100000>, 715 <0x00 0x32800000 0x00 0x100000>; 716 interrupt-names = "rx_011"; 717 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 718 }; 719 720 hwspinlock: hwlock@30e00000 { 721 compatible = "ti,am654-hwspinlock"; 722 reg = <0x00 0x30e00000 0x00 0x1000>; 723 #hwlock-cells = <1>; 724 }; 725 726 mailbox0_cluster0: mailbox@31f80000 { 727 compatible = "ti,am654-mailbox"; 728 reg = <0x00 0x31f80000 0x00 0x200>; 729 #mbox-cells = <1>; 730 ti,mbox-num-users = <4>; 731 ti,mbox-num-fifos = <16>; 732 interrupt-parent = <&main_navss_intr>; 733 status = "disabled"; 734 }; 735 736 mailbox0_cluster1: mailbox@31f81000 { 737 compatible = "ti,am654-mailbox"; 738 reg = <0x00 0x31f81000 0x00 0x200>; 739 #mbox-cells = <1>; 740 ti,mbox-num-users = <4>; 741 ti,mbox-num-fifos = <16>; 742 interrupt-parent = <&main_navss_intr>; 743 status = "disabled"; 744 }; 745 746 mailbox0_cluster2: mailbox@31f82000 { 747 compatible = "ti,am654-mailbox"; 748 reg = <0x00 0x31f82000 0x00 0x200>; 749 #mbox-cells = <1>; 750 ti,mbox-num-users = <4>; 751 ti,mbox-num-fifos = <16>; 752 interrupt-parent = <&main_navss_intr>; 753 status = "disabled"; 754 }; 755 756 mailbox0_cluster3: mailbox@31f83000 { 757 compatible = "ti,am654-mailbox"; 758 reg = <0x00 0x31f83000 0x00 0x200>; 759 #mbox-cells = <1>; 760 ti,mbox-num-users = <4>; 761 ti,mbox-num-fifos = <16>; 762 interrupt-parent = <&main_navss_intr>; 763 status = "disabled"; 764 }; 765 766 mailbox0_cluster4: mailbox@31f84000 { 767 compatible = "ti,am654-mailbox"; 768 reg = <0x00 0x31f84000 0x00 0x200>; 769 #mbox-cells = <1>; 770 ti,mbox-num-users = <4>; 771 ti,mbox-num-fifos = <16>; 772 interrupt-parent = <&main_navss_intr>; 773 status = "disabled"; 774 }; 775 776 mailbox0_cluster5: mailbox@31f85000 { 777 compatible = "ti,am654-mailbox"; 778 reg = <0x00 0x31f85000 0x00 0x200>; 779 #mbox-cells = <1>; 780 ti,mbox-num-users = <4>; 781 ti,mbox-num-fifos = <16>; 782 interrupt-parent = <&main_navss_intr>; 783 status = "disabled"; 784 }; 785 786 mailbox0_cluster6: mailbox@31f86000 { 787 compatible = "ti,am654-mailbox"; 788 reg = <0x00 0x31f86000 0x00 0x200>; 789 #mbox-cells = <1>; 790 ti,mbox-num-users = <4>; 791 ti,mbox-num-fifos = <16>; 792 interrupt-parent = <&main_navss_intr>; 793 status = "disabled"; 794 }; 795 796 mailbox0_cluster7: mailbox@31f87000 { 797 compatible = "ti,am654-mailbox"; 798 reg = <0x00 0x31f87000 0x00 0x200>; 799 #mbox-cells = <1>; 800 ti,mbox-num-users = <4>; 801 ti,mbox-num-fifos = <16>; 802 interrupt-parent = <&main_navss_intr>; 803 status = "disabled"; 804 }; 805 806 mailbox0_cluster8: mailbox@31f88000 { 807 compatible = "ti,am654-mailbox"; 808 reg = <0x00 0x31f88000 0x00 0x200>; 809 #mbox-cells = <1>; 810 ti,mbox-num-users = <4>; 811 ti,mbox-num-fifos = <16>; 812 interrupt-parent = <&main_navss_intr>; 813 status = "disabled"; 814 }; 815 816 mailbox0_cluster9: mailbox@31f89000 { 817 compatible = "ti,am654-mailbox"; 818 reg = <0x00 0x31f89000 0x00 0x200>; 819 #mbox-cells = <1>; 820 ti,mbox-num-users = <4>; 821 ti,mbox-num-fifos = <16>; 822 interrupt-parent = <&main_navss_intr>; 823 status = "disabled"; 824 }; 825 826 mailbox0_cluster10: mailbox@31f8a000 { 827 compatible = "ti,am654-mailbox"; 828 reg = <0x00 0x31f8a000 0x00 0x200>; 829 #mbox-cells = <1>; 830 ti,mbox-num-users = <4>; 831 ti,mbox-num-fifos = <16>; 832 interrupt-parent = <&main_navss_intr>; 833 status = "disabled"; 834 }; 835 836 mailbox0_cluster11: mailbox@31f8b000 { 837 compatible = "ti,am654-mailbox"; 838 reg = <0x00 0x31f8b000 0x00 0x200>; 839 #mbox-cells = <1>; 840 ti,mbox-num-users = <4>; 841 ti,mbox-num-fifos = <16>; 842 interrupt-parent = <&main_navss_intr>; 843 status = "disabled"; 844 }; 845 846 mailbox1_cluster0: mailbox@31f90000 { 847 compatible = "ti,am654-mailbox"; 848 reg = <0x00 0x31f90000 0x00 0x200>; 849 #mbox-cells = <1>; 850 ti,mbox-num-users = <4>; 851 ti,mbox-num-fifos = <16>; 852 interrupt-parent = <&main_navss_intr>; 853 status = "disabled"; 854 }; 855 856 mailbox1_cluster1: mailbox@31f91000 { 857 compatible = "ti,am654-mailbox"; 858 reg = <0x00 0x31f91000 0x00 0x200>; 859 #mbox-cells = <1>; 860 ti,mbox-num-users = <4>; 861 ti,mbox-num-fifos = <16>; 862 interrupt-parent = <&main_navss_intr>; 863 status = "disabled"; 864 }; 865 866 mailbox1_cluster2: mailbox@31f92000 { 867 compatible = "ti,am654-mailbox"; 868 reg = <0x00 0x31f92000 0x00 0x200>; 869 #mbox-cells = <1>; 870 ti,mbox-num-users = <4>; 871 ti,mbox-num-fifos = <16>; 872 interrupt-parent = <&main_navss_intr>; 873 status = "disabled"; 874 }; 875 876 mailbox1_cluster3: mailbox@31f93000 { 877 compatible = "ti,am654-mailbox"; 878 reg = <0x00 0x31f93000 0x00 0x200>; 879 #mbox-cells = <1>; 880 ti,mbox-num-users = <4>; 881 ti,mbox-num-fifos = <16>; 882 interrupt-parent = <&main_navss_intr>; 883 status = "disabled"; 884 }; 885 886 mailbox1_cluster4: mailbox@31f94000 { 887 compatible = "ti,am654-mailbox"; 888 reg = <0x00 0x31f94000 0x00 0x200>; 889 #mbox-cells = <1>; 890 ti,mbox-num-users = <4>; 891 ti,mbox-num-fifos = <16>; 892 interrupt-parent = <&main_navss_intr>; 893 status = "disabled"; 894 }; 895 896 mailbox1_cluster5: mailbox@31f95000 { 897 compatible = "ti,am654-mailbox"; 898 reg = <0x00 0x31f95000 0x00 0x200>; 899 #mbox-cells = <1>; 900 ti,mbox-num-users = <4>; 901 ti,mbox-num-fifos = <16>; 902 interrupt-parent = <&main_navss_intr>; 903 status = "disabled"; 904 }; 905 906 mailbox1_cluster6: mailbox@31f96000 { 907 compatible = "ti,am654-mailbox"; 908 reg = <0x00 0x31f96000 0x00 0x200>; 909 #mbox-cells = <1>; 910 ti,mbox-num-users = <4>; 911 ti,mbox-num-fifos = <16>; 912 interrupt-parent = <&main_navss_intr>; 913 status = "disabled"; 914 }; 915 916 mailbox1_cluster7: mailbox@31f97000 { 917 compatible = "ti,am654-mailbox"; 918 reg = <0x00 0x31f97000 0x00 0x200>; 919 #mbox-cells = <1>; 920 ti,mbox-num-users = <4>; 921 ti,mbox-num-fifos = <16>; 922 interrupt-parent = <&main_navss_intr>; 923 status = "disabled"; 924 }; 925 926 mailbox1_cluster8: mailbox@31f98000 { 927 compatible = "ti,am654-mailbox"; 928 reg = <0x00 0x31f98000 0x00 0x200>; 929 #mbox-cells = <1>; 930 ti,mbox-num-users = <4>; 931 ti,mbox-num-fifos = <16>; 932 interrupt-parent = <&main_navss_intr>; 933 status = "disabled"; 934 }; 935 936 mailbox1_cluster9: mailbox@31f99000 { 937 compatible = "ti,am654-mailbox"; 938 reg = <0x00 0x31f99000 0x00 0x200>; 939 #mbox-cells = <1>; 940 ti,mbox-num-users = <4>; 941 ti,mbox-num-fifos = <16>; 942 interrupt-parent = <&main_navss_intr>; 943 status = "disabled"; 944 }; 945 946 mailbox1_cluster10: mailbox@31f9a000 { 947 compatible = "ti,am654-mailbox"; 948 reg = <0x00 0x31f9a000 0x00 0x200>; 949 #mbox-cells = <1>; 950 ti,mbox-num-users = <4>; 951 ti,mbox-num-fifos = <16>; 952 interrupt-parent = <&main_navss_intr>; 953 status = "disabled"; 954 }; 955 956 mailbox1_cluster11: mailbox@31f9b000 { 957 compatible = "ti,am654-mailbox"; 958 reg = <0x00 0x31f9b000 0x00 0x200>; 959 #mbox-cells = <1>; 960 ti,mbox-num-users = <4>; 961 ti,mbox-num-fifos = <16>; 962 interrupt-parent = <&main_navss_intr>; 963 status = "disabled"; 964 }; 965 966 main_ringacc: ringacc@3c000000 { 967 compatible = "ti,am654-navss-ringacc"; 968 reg = <0x00 0x3c000000 0x00 0x400000>, 969 <0x00 0x38000000 0x00 0x400000>, 970 <0x00 0x31120000 0x00 0x100>, 971 <0x00 0x33000000 0x00 0x40000>, 972 <0x00 0x31080000 0x00 0x40000>; 973 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 974 ti,num-rings = <1024>; 975 ti,sci-rm-range-gp-rings = <0x1>; 976 ti,sci = <&sms>; 977 ti,sci-dev-id = <315>; 978 msi-parent = <&main_udmass_inta>; 979 }; 980 981 main_udmap: dma-controller@31150000 { 982 compatible = "ti,j721e-navss-main-udmap"; 983 reg = <0x00 0x31150000 0x00 0x100>, 984 <0x00 0x34000000 0x00 0x80000>, 985 <0x00 0x35000000 0x00 0x200000>; 986 reg-names = "gcfg", "rchanrt", "tchanrt"; 987 msi-parent = <&main_udmass_inta>; 988 #dma-cells = <1>; 989 990 ti,sci = <&sms>; 991 ti,sci-dev-id = <319>; 992 ti,ringacc = <&main_ringacc>; 993 994 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 995 <0x0f>, /* TX_HCHAN */ 996 <0x10>; /* TX_UHCHAN */ 997 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 998 <0x0b>, /* RX_HCHAN */ 999 <0x0c>; /* RX_UHCHAN */ 1000 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1001 }; 1002 1003 cpts@310d0000 { 1004 compatible = "ti,j721e-cpts"; 1005 reg = <0x00 0x310d0000 0x00 0x400>; 1006 reg-names = "cpts"; 1007 clocks = <&k3_clks 282 0>; 1008 clock-names = "cpts"; 1009 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1010 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1011 interrupts-extended = <&main_navss_intr 391>; 1012 interrupt-names = "cpts"; 1013 ti,cpts-periodic-outputs = <6>; 1014 ti,cpts-ext-ts-inputs = <8>; 1015 }; 1016 }; 1017 1018 main_mcan0: can@2701000 { 1019 compatible = "bosch,m_can"; 1020 reg = <0x00 0x02701000 0x00 0x200>, 1021 <0x00 0x02708000 0x00 0x8000>; 1022 reg-names = "m_can", "message_ram"; 1023 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1024 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1025 clock-names = "hclk", "cclk"; 1026 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupt-names = "int0", "int1"; 1029 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1030 status = "disabled"; 1031 }; 1032 1033 main_mcan1: can@2711000 { 1034 compatible = "bosch,m_can"; 1035 reg = <0x00 0x02711000 0x00 0x200>, 1036 <0x00 0x02718000 0x00 0x8000>; 1037 reg-names = "m_can", "message_ram"; 1038 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1039 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1040 clock-names = "hclk", "cclk"; 1041 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1043 interrupt-names = "int0", "int1"; 1044 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1045 status = "disabled"; 1046 }; 1047 1048 main_mcan2: can@2721000 { 1049 compatible = "bosch,m_can"; 1050 reg = <0x00 0x02721000 0x00 0x200>, 1051 <0x00 0x02728000 0x00 0x8000>; 1052 reg-names = "m_can", "message_ram"; 1053 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1054 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1055 clock-names = "hclk", "cclk"; 1056 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-names = "int0", "int1"; 1059 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1060 status = "disabled"; 1061 }; 1062 1063 main_mcan3: can@2731000 { 1064 compatible = "bosch,m_can"; 1065 reg = <0x00 0x02731000 0x00 0x200>, 1066 <0x00 0x02738000 0x00 0x8000>; 1067 reg-names = "m_can", "message_ram"; 1068 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1069 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1070 clock-names = "hclk", "cclk"; 1071 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "int0", "int1"; 1074 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1075 status = "disabled"; 1076 }; 1077 1078 main_mcan4: can@2741000 { 1079 compatible = "bosch,m_can"; 1080 reg = <0x00 0x02741000 0x00 0x200>, 1081 <0x00 0x02748000 0x00 0x8000>; 1082 reg-names = "m_can", "message_ram"; 1083 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1084 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1085 clock-names = "hclk", "cclk"; 1086 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1088 interrupt-names = "int0", "int1"; 1089 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1090 status = "disabled"; 1091 }; 1092 1093 main_mcan5: can@2751000 { 1094 compatible = "bosch,m_can"; 1095 reg = <0x00 0x02751000 0x00 0x200>, 1096 <0x00 0x02758000 0x00 0x8000>; 1097 reg-names = "m_can", "message_ram"; 1098 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1099 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1100 clock-names = "hclk", "cclk"; 1101 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "int0", "int1"; 1104 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1105 status = "disabled"; 1106 }; 1107 1108 main_mcan6: can@2761000 { 1109 compatible = "bosch,m_can"; 1110 reg = <0x00 0x02761000 0x00 0x200>, 1111 <0x00 0x02768000 0x00 0x8000>; 1112 reg-names = "m_can", "message_ram"; 1113 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1114 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1115 clock-names = "hclk", "cclk"; 1116 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1118 interrupt-names = "int0", "int1"; 1119 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1120 status = "disabled"; 1121 }; 1122 1123 main_mcan7: can@2771000 { 1124 compatible = "bosch,m_can"; 1125 reg = <0x00 0x02771000 0x00 0x200>, 1126 <0x00 0x02778000 0x00 0x8000>; 1127 reg-names = "m_can", "message_ram"; 1128 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1129 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1130 clock-names = "hclk", "cclk"; 1131 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1133 interrupt-names = "int0", "int1"; 1134 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1135 status = "disabled"; 1136 }; 1137 1138 main_mcan8: can@2781000 { 1139 compatible = "bosch,m_can"; 1140 reg = <0x00 0x02781000 0x00 0x200>, 1141 <0x00 0x02788000 0x00 0x8000>; 1142 reg-names = "m_can", "message_ram"; 1143 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1144 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1145 clock-names = "hclk", "cclk"; 1146 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1148 interrupt-names = "int0", "int1"; 1149 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1150 status = "disabled"; 1151 }; 1152 1153 main_mcan9: can@2791000 { 1154 compatible = "bosch,m_can"; 1155 reg = <0x00 0x02791000 0x00 0x200>, 1156 <0x00 0x02798000 0x00 0x8000>; 1157 reg-names = "m_can", "message_ram"; 1158 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1160 clock-names = "hclk", "cclk"; 1161 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1163 interrupt-names = "int0", "int1"; 1164 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1165 status = "disabled"; 1166 }; 1167 1168 main_mcan10: can@27a1000 { 1169 compatible = "bosch,m_can"; 1170 reg = <0x00 0x027a1000 0x00 0x200>, 1171 <0x00 0x027a8000 0x00 0x8000>; 1172 reg-names = "m_can", "message_ram"; 1173 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1174 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1175 clock-names = "hclk", "cclk"; 1176 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1178 interrupt-names = "int0", "int1"; 1179 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1180 status = "disabled"; 1181 }; 1182 1183 main_mcan11: can@27b1000 { 1184 compatible = "bosch,m_can"; 1185 reg = <0x00 0x027b1000 0x00 0x200>, 1186 <0x00 0x027b8000 0x00 0x8000>; 1187 reg-names = "m_can", "message_ram"; 1188 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1189 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1190 clock-names = "hclk", "cclk"; 1191 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1193 interrupt-names = "int0", "int1"; 1194 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1195 status = "disabled"; 1196 }; 1197 1198 main_mcan12: can@27c1000 { 1199 compatible = "bosch,m_can"; 1200 reg = <0x00 0x027c1000 0x00 0x200>, 1201 <0x00 0x027c8000 0x00 0x8000>; 1202 reg-names = "m_can", "message_ram"; 1203 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1204 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1205 clock-names = "hclk", "cclk"; 1206 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "int0", "int1"; 1209 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1210 status = "disabled"; 1211 }; 1212 1213 main_mcan13: can@27d1000 { 1214 compatible = "bosch,m_can"; 1215 reg = <0x00 0x027d1000 0x00 0x200>, 1216 <0x00 0x027d8000 0x00 0x8000>; 1217 reg-names = "m_can", "message_ram"; 1218 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1219 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1220 clock-names = "hclk", "cclk"; 1221 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1223 interrupt-names = "int0", "int1"; 1224 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1225 status = "disabled"; 1226 }; 1227 1228 main_mcan14: can@2681000 { 1229 compatible = "bosch,m_can"; 1230 reg = <0x00 0x02681000 0x00 0x200>, 1231 <0x00 0x02688000 0x00 0x8000>; 1232 reg-names = "m_can", "message_ram"; 1233 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1234 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1235 clock-names = "hclk", "cclk"; 1236 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1238 interrupt-names = "int0", "int1"; 1239 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1240 status = "disabled"; 1241 }; 1242 1243 main_mcan15: can@2691000 { 1244 compatible = "bosch,m_can"; 1245 reg = <0x00 0x02691000 0x00 0x200>, 1246 <0x00 0x02698000 0x00 0x8000>; 1247 reg-names = "m_can", "message_ram"; 1248 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1249 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1250 clock-names = "hclk", "cclk"; 1251 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1253 interrupt-names = "int0", "int1"; 1254 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1255 status = "disabled"; 1256 }; 1257 1258 main_mcan16: can@26a1000 { 1259 compatible = "bosch,m_can"; 1260 reg = <0x00 0x026a1000 0x00 0x200>, 1261 <0x00 0x026a8000 0x00 0x8000>; 1262 reg-names = "m_can", "message_ram"; 1263 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1264 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1265 clock-names = "hclk", "cclk"; 1266 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1268 interrupt-names = "int0", "int1"; 1269 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1270 status = "disabled"; 1271 }; 1272 1273 main_mcan17: can@26b1000 { 1274 compatible = "bosch,m_can"; 1275 reg = <0x00 0x026b1000 0x00 0x200>, 1276 <0x00 0x026b8000 0x00 0x8000>; 1277 reg-names = "m_can", "message_ram"; 1278 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1279 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1280 clock-names = "hclk", "cclk"; 1281 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-names = "int0", "int1"; 1284 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1285 status = "disabled"; 1286 }; 1287 1288 main_spi0: spi@2100000 { 1289 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1290 reg = <0x00 0x02100000 0x00 0x400>; 1291 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1295 clocks = <&k3_clks 376 1>; 1296 status = "disabled"; 1297 }; 1298 1299 main_spi1: spi@2110000 { 1300 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1301 reg = <0x00 0x02110000 0x00 0x400>; 1302 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1306 clocks = <&k3_clks 377 1>; 1307 status = "disabled"; 1308 }; 1309 1310 main_spi2: spi@2120000 { 1311 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1312 reg = <0x00 0x02120000 0x00 0x400>; 1313 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1317 clocks = <&k3_clks 378 1>; 1318 status = "disabled"; 1319 }; 1320 1321 main_spi3: spi@2130000 { 1322 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1323 reg = <0x00 0x02130000 0x00 0x400>; 1324 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1328 clocks = <&k3_clks 379 1>; 1329 status = "disabled"; 1330 }; 1331 1332 main_spi4: spi@2140000 { 1333 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1334 reg = <0x00 0x02140000 0x00 0x400>; 1335 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1339 clocks = <&k3_clks 380 1>; 1340 status = "disabled"; 1341 }; 1342 1343 main_spi5: spi@2150000 { 1344 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1345 reg = <0x00 0x02150000 0x00 0x400>; 1346 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1350 clocks = <&k3_clks 381 1>; 1351 status = "disabled"; 1352 }; 1353 1354 main_spi6: spi@2160000 { 1355 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1356 reg = <0x00 0x02160000 0x00 0x400>; 1357 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1361 clocks = <&k3_clks 382 1>; 1362 status = "disabled"; 1363 }; 1364 1365 main_spi7: spi@2170000 { 1366 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1367 reg = <0x00 0x02170000 0x00 0x400>; 1368 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1372 clocks = <&k3_clks 383 1>; 1373 status = "disabled"; 1374 }; 1375 1376 ufs_wrapper: ufs-wrapper@4e80000 { 1377 compatible = "ti,j721e-ufs"; 1378 reg = <0x00 0x4e80000 0x00 0x100>; 1379 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1380 clocks = <&k3_clks 387 3>; 1381 assigned-clocks = <&k3_clks 387 3>; 1382 assigned-clock-parents = <&k3_clks 387 6>; 1383 ranges; 1384 #address-cells = <2>; 1385 #size-cells = <2>; 1386 status = "disabled"; 1387 1388 ufs@4e84000 { 1389 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1390 reg = <0x00 0x4e84000 0x00 0x10000>; 1391 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1392 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1393 <19200000 19200000>; 1394 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1395 clock-names = "core_clk", "phy_clk", "ref_clk"; 1396 dma-coherent; 1397 }; 1398 }; 1399 1400 main_r5fss0: r5fss@5c00000 { 1401 compatible = "ti,j721s2-r5fss"; 1402 ti,cluster-mode = <1>; 1403 #address-cells = <1>; 1404 #size-cells = <1>; 1405 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1406 <0x5d00000 0x00 0x5d00000 0x20000>; 1407 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1408 1409 main_r5fss0_core0: r5f@5c00000 { 1410 compatible = "ti,j721s2-r5f"; 1411 reg = <0x5c00000 0x00010000>, 1412 <0x5c10000 0x00010000>; 1413 reg-names = "atcm", "btcm"; 1414 ti,sci = <&sms>; 1415 ti,sci-dev-id = <339>; 1416 ti,sci-proc-ids = <0x06 0xff>; 1417 resets = <&k3_reset 339 1>; 1418 firmware-name = "j784s4-main-r5f0_0-fw"; 1419 ti,atcm-enable = <1>; 1420 ti,btcm-enable = <1>; 1421 ti,loczrama = <1>; 1422 }; 1423 1424 main_r5fss0_core1: r5f@5d00000 { 1425 compatible = "ti,j721s2-r5f"; 1426 reg = <0x5d00000 0x00010000>, 1427 <0x5d10000 0x00010000>; 1428 reg-names = "atcm", "btcm"; 1429 ti,sci = <&sms>; 1430 ti,sci-dev-id = <340>; 1431 ti,sci-proc-ids = <0x07 0xff>; 1432 resets = <&k3_reset 340 1>; 1433 firmware-name = "j784s4-main-r5f0_1-fw"; 1434 ti,atcm-enable = <1>; 1435 ti,btcm-enable = <1>; 1436 ti,loczrama = <1>; 1437 }; 1438 }; 1439 1440 main_r5fss1: r5fss@5e00000 { 1441 compatible = "ti,j721s2-r5fss"; 1442 ti,cluster-mode = <1>; 1443 #address-cells = <1>; 1444 #size-cells = <1>; 1445 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1446 <0x5f00000 0x00 0x5f00000 0x20000>; 1447 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1448 1449 main_r5fss1_core0: r5f@5e00000 { 1450 compatible = "ti,j721s2-r5f"; 1451 reg = <0x5e00000 0x00010000>, 1452 <0x5e10000 0x00010000>; 1453 reg-names = "atcm", "btcm"; 1454 ti,sci = <&sms>; 1455 ti,sci-dev-id = <341>; 1456 ti,sci-proc-ids = <0x08 0xff>; 1457 resets = <&k3_reset 341 1>; 1458 firmware-name = "j784s4-main-r5f1_0-fw"; 1459 ti,atcm-enable = <1>; 1460 ti,btcm-enable = <1>; 1461 ti,loczrama = <1>; 1462 }; 1463 1464 main_r5fss1_core1: r5f@5f00000 { 1465 compatible = "ti,j721s2-r5f"; 1466 reg = <0x5f00000 0x00010000>, 1467 <0x5f10000 0x00010000>; 1468 reg-names = "atcm", "btcm"; 1469 ti,sci = <&sms>; 1470 ti,sci-dev-id = <342>; 1471 ti,sci-proc-ids = <0x09 0xff>; 1472 resets = <&k3_reset 342 1>; 1473 firmware-name = "j784s4-main-r5f1_1-fw"; 1474 ti,atcm-enable = <1>; 1475 ti,btcm-enable = <1>; 1476 ti,loczrama = <1>; 1477 }; 1478 }; 1479 1480 main_r5fss2: r5fss@5900000 { 1481 compatible = "ti,j721s2-r5fss"; 1482 ti,cluster-mode = <1>; 1483 #address-cells = <1>; 1484 #size-cells = <1>; 1485 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1486 <0x5a00000 0x00 0x5a00000 0x20000>; 1487 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1488 1489 main_r5fss2_core0: r5f@5900000 { 1490 compatible = "ti,j721s2-r5f"; 1491 reg = <0x5900000 0x00010000>, 1492 <0x5910000 0x00010000>; 1493 reg-names = "atcm", "btcm"; 1494 ti,sci = <&sms>; 1495 ti,sci-dev-id = <343>; 1496 ti,sci-proc-ids = <0x0a 0xff>; 1497 resets = <&k3_reset 343 1>; 1498 firmware-name = "j784s4-main-r5f2_0-fw"; 1499 ti,atcm-enable = <1>; 1500 ti,btcm-enable = <1>; 1501 ti,loczrama = <1>; 1502 }; 1503 1504 main_r5fss2_core1: r5f@5a00000 { 1505 compatible = "ti,j721s2-r5f"; 1506 reg = <0x5a00000 0x00010000>, 1507 <0x5a10000 0x00010000>; 1508 reg-names = "atcm", "btcm"; 1509 ti,sci = <&sms>; 1510 ti,sci-dev-id = <344>; 1511 ti,sci-proc-ids = <0x0b 0xff>; 1512 resets = <&k3_reset 344 1>; 1513 firmware-name = "j784s4-main-r5f2_1-fw"; 1514 ti,atcm-enable = <1>; 1515 ti,btcm-enable = <1>; 1516 ti,loczrama = <1>; 1517 }; 1518 }; 1519 1520 c71_0: dsp@64800000 { 1521 compatible = "ti,j721s2-c71-dsp"; 1522 reg = <0x00 0x64800000 0x00 0x00080000>, 1523 <0x00 0x64e00000 0x00 0x0000c000>; 1524 reg-names = "l2sram", "l1dram"; 1525 ti,sci = <&sms>; 1526 ti,sci-dev-id = <30>; 1527 ti,sci-proc-ids = <0x30 0xff>; 1528 resets = <&k3_reset 30 1>; 1529 firmware-name = "j784s4-c71_0-fw"; 1530 status = "disabled"; 1531 }; 1532 1533 c71_1: dsp@65800000 { 1534 compatible = "ti,j721s2-c71-dsp"; 1535 reg = <0x00 0x65800000 0x00 0x00080000>, 1536 <0x00 0x65e00000 0x00 0x0000c000>; 1537 reg-names = "l2sram", "l1dram"; 1538 ti,sci = <&sms>; 1539 ti,sci-dev-id = <33>; 1540 ti,sci-proc-ids = <0x31 0xff>; 1541 resets = <&k3_reset 33 1>; 1542 firmware-name = "j784s4-c71_1-fw"; 1543 status = "disabled"; 1544 }; 1545 1546 c71_2: dsp@66800000 { 1547 compatible = "ti,j721s2-c71-dsp"; 1548 reg = <0x00 0x66800000 0x00 0x00080000>, 1549 <0x00 0x66e00000 0x00 0x0000c000>; 1550 reg-names = "l2sram", "l1dram"; 1551 ti,sci = <&sms>; 1552 ti,sci-dev-id = <37>; 1553 ti,sci-proc-ids = <0x32 0xff>; 1554 resets = <&k3_reset 37 1>; 1555 firmware-name = "j784s4-c71_2-fw"; 1556 status = "disabled"; 1557 }; 1558 1559 c71_3: dsp@67800000 { 1560 compatible = "ti,j721s2-c71-dsp"; 1561 reg = <0x00 0x67800000 0x00 0x00080000>, 1562 <0x00 0x67e00000 0x00 0x0000c000>; 1563 reg-names = "l2sram", "l1dram"; 1564 ti,sci = <&sms>; 1565 ti,sci-dev-id = <40>; 1566 ti,sci-proc-ids = <0x33 0xff>; 1567 resets = <&k3_reset 40 1>; 1568 firmware-name = "j784s4-c71_3-fw"; 1569 status = "disabled"; 1570 }; 1571 }; 1572