1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/usb/gadget/emxx_udc.c
4 * EMXX FCD (Function Controller Driver) for USB.
5 *
6 * Copyright (C) 2010 Renesas Electronics Corporation
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/interrupt.h>
18 #include <linux/proc_fs.h>
19 #include <linux/clk.h>
20 #include <linux/ctype.h>
21 #include <linux/string.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/workqueue.h>
24 #include <linux/device.h>
25
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28
29 #include <linux/irq.h>
30 #include <linux/gpio/consumer.h>
31
32 #include "emxx_udc.h"
33
34 #define DRIVER_DESC "EMXX UDC driver"
35 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
36
37 static struct gpio_desc *vbus_gpio;
38 static int vbus_irq;
39
40 static const char driver_name[] = "emxx_udc";
41
42 /*===========================================================================*/
43 /* Prototype */
44 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
45 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
46 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
47 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
48 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
49 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
50
51 static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
52 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
53
54 /*===========================================================================*/
55 /* Macro */
56 #define _nbu2ss_zero_len_pkt(udc, epnum) \
57 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
58
59 /*===========================================================================*/
60 /* Global */
61 static struct nbu2ss_udc udc_controller;
62
63 /*-------------------------------------------------------------------------*/
64 /* Read */
_nbu2ss_readl(void __iomem * address)65 static inline u32 _nbu2ss_readl(void __iomem *address)
66 {
67 return __raw_readl(address);
68 }
69
70 /*-------------------------------------------------------------------------*/
71 /* Write */
_nbu2ss_writel(void __iomem * address,u32 udata)72 static inline void _nbu2ss_writel(void __iomem *address, u32 udata)
73 {
74 __raw_writel(udata, address);
75 }
76
77 /*-------------------------------------------------------------------------*/
78 /* Set Bit */
_nbu2ss_bitset(void __iomem * address,u32 udata)79 static inline void _nbu2ss_bitset(void __iomem *address, u32 udata)
80 {
81 u32 reg_dt = __raw_readl(address) | (udata);
82
83 __raw_writel(reg_dt, address);
84 }
85
86 /*-------------------------------------------------------------------------*/
87 /* Clear Bit */
_nbu2ss_bitclr(void __iomem * address,u32 udata)88 static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata)
89 {
90 u32 reg_dt = __raw_readl(address) & ~(udata);
91
92 __raw_writel(reg_dt, address);
93 }
94
95 #ifdef UDC_DEBUG_DUMP
96 /*-------------------------------------------------------------------------*/
_nbu2ss_dump_register(struct nbu2ss_udc * udc)97 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
98 {
99 int i;
100 u32 reg_data;
101
102 pr_info("=== %s()\n", __func__);
103
104 if (!udc) {
105 pr_err("%s udc == NULL\n", __func__);
106 return;
107 }
108
109 spin_unlock(&udc->lock);
110
111 dev_dbg(&udc->dev, "\n-USB REG-\n");
112 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
113 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i));
114 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
115
116 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
117 dev_dbg(&udc->dev, " %08x", (int)reg_data);
118
119 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
120 dev_dbg(&udc->dev, " %08x", (int)reg_data);
121
122 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
123 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
124 }
125
126 spin_lock(&udc->lock);
127 }
128 #endif /* UDC_DEBUG_DUMP */
129
130 /*-------------------------------------------------------------------------*/
131 /* Endpoint 0 Callback (Complete) */
_nbu2ss_ep0_complete(struct usb_ep * _ep,struct usb_request * _req)132 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
133 {
134 u8 recipient;
135 u16 selector;
136 u16 wIndex;
137 u32 test_mode;
138 struct usb_ctrlrequest *p_ctrl;
139 struct nbu2ss_udc *udc;
140
141 if (!_ep || !_req)
142 return;
143
144 udc = (struct nbu2ss_udc *)_req->context;
145 p_ctrl = &udc->ctrl;
146 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
147 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
148 /*-------------------------------------------------*/
149 /* SET_FEATURE */
150 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
151 selector = le16_to_cpu(p_ctrl->wValue);
152 if ((recipient == USB_RECIP_DEVICE) &&
153 (selector == USB_DEVICE_TEST_MODE)) {
154 wIndex = le16_to_cpu(p_ctrl->wIndex);
155 test_mode = (u32)(wIndex >> 8);
156 _nbu2ss_set_test_mode(udc, test_mode);
157 }
158 }
159 }
160 }
161
162 /*-------------------------------------------------------------------------*/
163 /* Initialization usb_request */
_nbu2ss_create_ep0_packet(struct nbu2ss_udc * udc,void * p_buf,unsigned int length)164 static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc,
165 void *p_buf, unsigned int length)
166 {
167 udc->ep0_req.req.buf = p_buf;
168 udc->ep0_req.req.length = length;
169 udc->ep0_req.req.dma = 0;
170 udc->ep0_req.req.zero = true;
171 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
172 udc->ep0_req.req.status = -EINPROGRESS;
173 udc->ep0_req.req.context = udc;
174 udc->ep0_req.req.actual = 0;
175 }
176
177 /*-------------------------------------------------------------------------*/
178 /* Acquisition of the first address of RAM(FIFO) */
_nbu2ss_get_begin_ram_address(struct nbu2ss_udc * udc)179 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
180 {
181 u32 num, buf_type;
182 u32 data, last_ram_adr, use_ram_size;
183
184 struct ep_regs __iomem *p_ep_regs;
185
186 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
187 use_ram_size = 0;
188
189 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
190 p_ep_regs = &udc->p_regs->EP_REGS[num];
191 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
192 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE;
193 if (buf_type == 0) {
194 /* Single Buffer */
195 use_ram_size += (data & EPN_MPKT) / sizeof(u32);
196 } else {
197 /* Double Buffer */
198 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2;
199 }
200
201 if ((data >> 16) > last_ram_adr)
202 last_ram_adr = data >> 16;
203 }
204
205 return last_ram_adr + use_ram_size;
206 }
207
208 /*-------------------------------------------------------------------------*/
209 /* Construction of Endpoint */
_nbu2ss_ep_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)210 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
211 {
212 u32 num;
213 u32 data;
214 u32 begin_adrs;
215
216 if (ep->epnum == 0)
217 return -EINVAL;
218
219 num = ep->epnum - 1;
220
221 /*-------------------------------------------------------------*/
222 /* RAM Transfer Address */
223 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
224 data = (begin_adrs << 16) | ep->ep.maxpacket;
225 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
226
227 /*-------------------------------------------------------------*/
228 /* Interrupt Enable */
229 data = 1 << (ep->epnum + 8);
230 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
231
232 /*-------------------------------------------------------------*/
233 /* Endpoint Type(Mode) */
234 /* Bulk, Interrupt, ISO */
235 switch (ep->ep_type) {
236 case USB_ENDPOINT_XFER_BULK:
237 data = EPN_BULK;
238 break;
239
240 case USB_ENDPOINT_XFER_INT:
241 data = EPN_BUF_SINGLE | EPN_INTERRUPT;
242 break;
243
244 case USB_ENDPOINT_XFER_ISOC:
245 data = EPN_ISO;
246 break;
247
248 default:
249 data = 0;
250 break;
251 }
252
253 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
254 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct));
255
256 if (ep->direct == USB_DIR_OUT) {
257 /*---------------------------------------------------------*/
258 /* OUT */
259 data = EPN_EN | EPN_BCLR | EPN_DIR0;
260 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
261
262 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL;
263 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
264
265 data = EPN_OUT_EN | EPN_OUT_END_EN;
266 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
267 } else {
268 /*---------------------------------------------------------*/
269 /* IN */
270 data = EPN_EN | EPN_BCLR | EPN_AUTO;
271 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
272
273 data = EPN_ISTL;
274 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
275
276 data = EPN_IN_EN | EPN_IN_END_EN;
277 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
278 }
279
280 return 0;
281 }
282
283 /*-------------------------------------------------------------------------*/
284 /* Release of Endpoint */
_nbu2ss_epn_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)285 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
286 {
287 u32 num;
288 u32 data;
289
290 if ((ep->epnum == 0) || (udc->vbus_active == 0))
291 return -EINVAL;
292
293 num = ep->epnum - 1;
294
295 /*-------------------------------------------------------------*/
296 /* RAM Transfer Address */
297 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
298
299 /*-------------------------------------------------------------*/
300 /* Interrupt Disable */
301 data = 1 << (ep->epnum + 8);
302 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
303
304 if (ep->direct == USB_DIR_OUT) {
305 /*---------------------------------------------------------*/
306 /* OUT */
307 data = EPN_ONAK | EPN_BCLR;
308 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
309
310 data = EPN_EN | EPN_DIR0;
311 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
312
313 data = EPN_OUT_EN | EPN_OUT_END_EN;
314 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
315 } else {
316 /*---------------------------------------------------------*/
317 /* IN */
318 data = EPN_BCLR;
319 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
320
321 data = EPN_EN | EPN_AUTO;
322 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
323
324 data = EPN_IN_EN | EPN_IN_END_EN;
325 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
326 }
327
328 return 0;
329 }
330
331 /*-------------------------------------------------------------------------*/
332 /* DMA setting (without Endpoint 0) */
_nbu2ss_ep_dma_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)333 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
334 {
335 u32 num;
336 u32 data;
337
338 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
339 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
340 return; /* Not Support DMA */
341
342 num = ep->epnum - 1;
343
344 if (ep->direct == USB_DIR_OUT) {
345 /*---------------------------------------------------------*/
346 /* OUT */
347 data = ep->ep.maxpacket;
348 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
349
350 /*---------------------------------------------------------*/
351 /* Transfer Direct */
352 data = DCR1_EPN_DIR0;
353 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
354
355 /*---------------------------------------------------------*/
356 /* DMA Mode etc. */
357 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0;
358 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
359 } else {
360 /*---------------------------------------------------------*/
361 /* IN */
362 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO);
363
364 /*---------------------------------------------------------*/
365 /* DMA Mode etc. */
366 data = EPN_BURST_SET | EPN_DMAMODE0;
367 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
368 }
369 }
370
371 /*-------------------------------------------------------------------------*/
372 /* DMA setting release */
_nbu2ss_ep_dma_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)373 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
374 {
375 u32 num;
376 u32 data;
377 struct fc_regs __iomem *preg = udc->p_regs;
378
379 if (udc->vbus_active == 0)
380 return; /* VBUS OFF */
381
382 data = _nbu2ss_readl(&preg->USBSSCONF);
383 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
384 return; /* Not Support DMA */
385
386 num = ep->epnum - 1;
387
388 _nbu2ss_ep_dma_abort(udc, ep);
389
390 if (ep->direct == USB_DIR_OUT) {
391 /*---------------------------------------------------------*/
392 /* OUT */
393 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
394 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0);
395 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
396 } else {
397 /*---------------------------------------------------------*/
398 /* IN */
399 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
400 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
401 }
402 }
403
404 /*-------------------------------------------------------------------------*/
405 /* Abort DMA */
_nbu2ss_ep_dma_abort(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)406 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
407 {
408 struct fc_regs __iomem *preg = udc->p_regs;
409
410 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN);
411 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */
412 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN);
413 }
414
415 /*-------------------------------------------------------------------------*/
416 /* Start IN Transfer */
_nbu2ss_ep_in_end(struct nbu2ss_udc * udc,u32 epnum,u32 data32,u32 length)417 static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc,
418 u32 epnum, u32 data32, u32 length)
419 {
420 u32 data;
421 u32 num;
422 struct fc_regs __iomem *preg = udc->p_regs;
423
424 if (length >= sizeof(u32))
425 return;
426
427 if (epnum == 0) {
428 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
429
430 /* Writing of 1-4 bytes */
431 if (length)
432 _nbu2ss_writel(&preg->EP0_WRITE, data32);
433
434 data = ((length << 5) & EP0_DW) | EP0_DEND;
435 _nbu2ss_writel(&preg->EP0_CONTROL, data);
436
437 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
438 } else {
439 num = epnum - 1;
440
441 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
442
443 /* Writing of 1-4 bytes */
444 if (length)
445 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
446
447 data = (((length) << 5) & EPN_DW) | EPN_DEND;
448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
449
450 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
451 }
452 }
453
454 #ifdef USE_DMA
455 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_map_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)456 static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc,
457 struct nbu2ss_ep *ep,
458 struct nbu2ss_req *req, u8 direct)
459 {
460 if (req->req.dma == DMA_ADDR_INVALID) {
461 if (req->unaligned) {
462 req->req.dma = ep->phys_buf;
463 } else {
464 req->req.dma = dma_map_single(udc->gadget.dev.parent,
465 req->req.buf,
466 req->req.length,
467 (direct == USB_DIR_IN)
468 ? DMA_TO_DEVICE
469 : DMA_FROM_DEVICE);
470 }
471 req->mapped = 1;
472 } else {
473 if (!req->unaligned)
474 dma_sync_single_for_device(udc->gadget.dev.parent,
475 req->req.dma,
476 req->req.length,
477 (direct == USB_DIR_IN)
478 ? DMA_TO_DEVICE
479 : DMA_FROM_DEVICE);
480
481 req->mapped = 0;
482 }
483 }
484
485 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_unmap_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)486 static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc,
487 struct nbu2ss_ep *ep,
488 struct nbu2ss_req *req, u8 direct)
489 {
490 u8 data[4];
491 u8 *p;
492 u32 count = 0;
493
494 if (direct == USB_DIR_OUT) {
495 count = req->req.actual % 4;
496 if (count) {
497 p = req->req.buf;
498 p += (req->req.actual - count);
499 memcpy(data, p, count);
500 }
501 }
502
503 if (req->mapped) {
504 if (req->unaligned) {
505 if (direct == USB_DIR_OUT)
506 memcpy(req->req.buf, ep->virt_buf,
507 req->req.actual & 0xfffffffc);
508 } else {
509 dma_unmap_single(udc->gadget.dev.parent,
510 req->req.dma, req->req.length,
511 (direct == USB_DIR_IN)
512 ? DMA_TO_DEVICE
513 : DMA_FROM_DEVICE);
514 }
515 req->req.dma = DMA_ADDR_INVALID;
516 req->mapped = 0;
517 } else {
518 if (!req->unaligned)
519 dma_sync_single_for_cpu(udc->gadget.dev.parent,
520 req->req.dma, req->req.length,
521 (direct == USB_DIR_IN)
522 ? DMA_TO_DEVICE
523 : DMA_FROM_DEVICE);
524 }
525
526 if (count) {
527 p = req->req.buf;
528 p += (req->req.actual - count);
529 memcpy(p, data, count);
530 }
531 }
532 #endif
533
534 /*-------------------------------------------------------------------------*/
535 /* Endpoint 0 OUT Transfer (PIO) */
ep0_out_pio(struct nbu2ss_udc * udc,u8 * buf,u32 length)536 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length)
537 {
538 u32 i;
539 u32 numreads = length / sizeof(u32);
540 union usb_reg_access *buf32 = (union usb_reg_access *)buf;
541
542 if (!numreads)
543 return 0;
544
545 /* PIO Read */
546 for (i = 0; i < numreads; i++) {
547 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
548 buf32++;
549 }
550
551 return numreads * sizeof(u32);
552 }
553
554 /*-------------------------------------------------------------------------*/
555 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */
ep0_out_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)556 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
557 {
558 u32 i;
559 u32 i_read_size = 0;
560 union usb_reg_access temp_32;
561 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
562
563 if ((length > 0) && (length < sizeof(u32))) {
564 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
565 for (i = 0 ; i < length ; i++)
566 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
567 i_read_size += length;
568 }
569
570 return i_read_size;
571 }
572
573 /*-------------------------------------------------------------------------*/
574 /* Endpoint 0 IN Transfer (PIO) */
EP0_in_PIO(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)575 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
576 {
577 u32 i;
578 u32 i_max_length = EP0_PACKETSIZE;
579 u32 i_word_length = 0;
580 u32 i_write_length = 0;
581 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
582
583 /*------------------------------------------------------------*/
584 /* Transfer Length */
585 if (i_max_length < length)
586 i_word_length = i_max_length / sizeof(u32);
587 else
588 i_word_length = length / sizeof(u32);
589
590 /*------------------------------------------------------------*/
591 /* PIO */
592 for (i = 0; i < i_word_length; i++) {
593 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw);
594 p_buf_32++;
595 i_write_length += sizeof(u32);
596 }
597
598 return i_write_length;
599 }
600
601 /*-------------------------------------------------------------------------*/
602 /* Endpoint 0 IN Transfer (PIO, OverBytes) */
ep0_in_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 i_remain_size)603 static int ep0_in_overbytes(struct nbu2ss_udc *udc,
604 u8 *p_buf,
605 u32 i_remain_size)
606 {
607 u32 i;
608 union usb_reg_access temp_32;
609 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
610
611 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) {
612 for (i = 0 ; i < i_remain_size ; i++)
613 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
614 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size);
615
616 return i_remain_size;
617 }
618
619 return 0;
620 }
621
622 /*-------------------------------------------------------------------------*/
623 /* Transfer NULL Packet (Epndoint 0) */
EP0_send_NULL(struct nbu2ss_udc * udc,bool pid_flag)624 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
625 {
626 u32 data;
627
628 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
629 data &= ~(u32)EP0_INAK;
630
631 if (pid_flag)
632 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
633 else
634 data |= (EP0_INAK_EN | EP0_DEND);
635
636 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
637
638 return 0;
639 }
640
641 /*-------------------------------------------------------------------------*/
642 /* Receive NULL Packet (Endpoint 0) */
EP0_receive_NULL(struct nbu2ss_udc * udc,bool pid_flag)643 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
644 {
645 u32 data;
646
647 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
648 data &= ~(u32)EP0_ONAK;
649
650 if (pid_flag)
651 data |= EP0_PIDCLR;
652
653 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
654
655 return 0;
656 }
657
658 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)659 static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc,
660 struct nbu2ss_req *req)
661 {
662 u8 *p_buffer; /* IN Data Buffer */
663 u32 data;
664 u32 i_remain_size = 0;
665 int result = 0;
666
667 /*-------------------------------------------------------------*/
668 /* End confirmation */
669 if (req->req.actual == req->req.length) {
670 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
671 if (req->zero) {
672 req->zero = false;
673 EP0_send_NULL(udc, false);
674 return 1;
675 }
676 }
677
678 return 0; /* Transfer End */
679 }
680
681 /*-------------------------------------------------------------*/
682 /* NAK release */
683 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
684 data |= EP0_INAK_EN;
685 data &= ~(u32)EP0_INAK;
686 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
687
688 i_remain_size = req->req.length - req->req.actual;
689 p_buffer = (u8 *)req->req.buf;
690 p_buffer += req->req.actual;
691
692 /*-------------------------------------------------------------*/
693 /* Data transfer */
694 result = EP0_in_PIO(udc, p_buffer, i_remain_size);
695
696 req->div_len = result;
697 i_remain_size -= result;
698
699 if (i_remain_size == 0) {
700 EP0_send_NULL(udc, false);
701 return result;
702 }
703
704 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
705 p_buffer += result;
706 result += ep0_in_overbytes(udc, p_buffer, i_remain_size);
707 req->div_len = result;
708 }
709
710 return result;
711 }
712
713 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)714 static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc,
715 struct nbu2ss_req *req)
716 {
717 u8 *p_buffer;
718 u32 i_remain_size;
719 u32 i_recv_length;
720 int result = 0;
721 int f_rcv_zero;
722
723 /*-------------------------------------------------------------*/
724 /* Receive data confirmation */
725 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
726 if (i_recv_length != 0) {
727 f_rcv_zero = 0;
728
729 i_remain_size = req->req.length - req->req.actual;
730 p_buffer = (u8 *)req->req.buf;
731 p_buffer += req->req.actual;
732
733 result = ep0_out_pio(udc, p_buffer
734 , min(i_remain_size, i_recv_length));
735 if (result < 0)
736 return result;
737
738 req->req.actual += result;
739 i_recv_length -= result;
740
741 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) {
742 p_buffer += result;
743 i_remain_size -= result;
744
745 result = ep0_out_overbytes(udc, p_buffer
746 , min(i_remain_size, i_recv_length));
747 req->req.actual += result;
748 }
749 } else {
750 f_rcv_zero = 1;
751 }
752
753 /*-------------------------------------------------------------*/
754 /* End confirmation */
755 if (req->req.actual == req->req.length) {
756 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
757 if (req->zero) {
758 req->zero = false;
759 EP0_receive_NULL(udc, false);
760 return 1;
761 }
762 }
763
764 return 0; /* Transfer End */
765 }
766
767 if ((req->req.actual % EP0_PACKETSIZE) != 0)
768 return 0; /* Short Packet Transfer End */
769
770 if (req->req.actual > req->req.length) {
771 dev_err(udc->dev, " *** Overrun Error\n");
772 return -EOVERFLOW;
773 }
774
775 if (f_rcv_zero != 0) {
776 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
777 if (i_remain_size & EP0_ONAK) {
778 /*---------------------------------------------------*/
779 /* NACK release */
780 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
781 }
782 result = 1;
783 }
784
785 return result;
786 }
787
788 /*-------------------------------------------------------------------------*/
_nbu2ss_out_dma(struct nbu2ss_udc * udc,struct nbu2ss_req * req,u32 num,u32 length)789 static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req,
790 u32 num, u32 length)
791 {
792 dma_addr_t p_buffer;
793 u32 mpkt;
794 u32 lmpkt;
795 u32 dmacnt;
796 u32 burst = 1;
797 u32 data;
798 int result;
799 struct fc_regs __iomem *preg = udc->p_regs;
800
801 if (req->dma_flag)
802 return 1; /* DMA is forwarded */
803
804 req->dma_flag = true;
805 p_buffer = req->req.dma;
806 p_buffer += req->req.actual;
807
808 /* DMA Address */
809 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
810
811 /* Number of transfer packets */
812 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
813 dmacnt = length / mpkt;
814 lmpkt = (length % mpkt) & ~(u32)0x03;
815
816 if (dmacnt > DMA_MAX_COUNT) {
817 dmacnt = DMA_MAX_COUNT;
818 lmpkt = 0;
819 } else if (lmpkt != 0) {
820 if (dmacnt == 0)
821 burst = 0; /* Burst OFF */
822 dmacnt++;
823 }
824
825 data = mpkt | (lmpkt << 16);
826 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
827
828 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN;
829 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
830
831 if (burst == 0) {
832 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
833 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
834 } else {
835 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
836 , (dmacnt << 16));
837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
838 }
839 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
840
841 result = length & ~(u32)0x03;
842 req->div_len = result;
843
844 return result;
845 }
846
847 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)848 static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
849 struct nbu2ss_req *req, u32 length)
850 {
851 u8 *p_buffer;
852 u32 i;
853 u32 data;
854 u32 i_word_length;
855 union usb_reg_access temp_32;
856 union usb_reg_access *p_buf_32;
857 int result = 0;
858 struct fc_regs __iomem *preg = udc->p_regs;
859
860 if (req->dma_flag)
861 return 1; /* DMA is forwarded */
862
863 if (length == 0)
864 return 0;
865
866 p_buffer = (u8 *)req->req.buf;
867 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
868
869 i_word_length = length / sizeof(u32);
870 if (i_word_length > 0) {
871 /*---------------------------------------------------------*/
872 /* Copy of every four bytes */
873 for (i = 0; i < i_word_length; i++) {
874 p_buf_32->dw =
875 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
876 p_buf_32++;
877 }
878 result = i_word_length * sizeof(u32);
879 }
880
881 data = length - result;
882 if (data > 0) {
883 /*---------------------------------------------------------*/
884 /* Copy of fraction byte */
885 temp_32.dw =
886 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
887 for (i = 0 ; i < data ; i++)
888 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
889 result += data;
890 }
891
892 req->req.actual += result;
893
894 if ((req->req.actual == req->req.length) ||
895 ((req->req.actual % ep->ep.maxpacket) != 0)) {
896 result = 0;
897 }
898
899 return result;
900 }
901
902 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)903 static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
904 struct nbu2ss_req *req, u32 data_size)
905 {
906 u32 num;
907 u32 i_buf_size;
908 int nret = 1;
909
910 if (ep->epnum == 0)
911 return -EINVAL;
912
913 num = ep->epnum - 1;
914
915 i_buf_size = min((req->req.length - req->req.actual), data_size);
916
917 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
918 (i_buf_size >= sizeof(u32))) {
919 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size);
920 } else {
921 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket);
922 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size);
923 }
924
925 return nret;
926 }
927
928 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)929 static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc,
930 struct nbu2ss_ep *ep,
931 struct nbu2ss_req *req)
932 {
933 u32 num;
934 u32 i_recv_length;
935 int result = 1;
936 struct fc_regs __iomem *preg = udc->p_regs;
937
938 if (ep->epnum == 0)
939 return -EINVAL;
940
941 num = ep->epnum - 1;
942
943 /*-------------------------------------------------------------*/
944 /* Receive Length */
945 i_recv_length =
946 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA;
947
948 if (i_recv_length != 0) {
949 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length);
950 if (i_recv_length < ep->ep.maxpacket) {
951 if (i_recv_length == result) {
952 req->req.actual += result;
953 result = 0;
954 }
955 }
956 } else {
957 if ((req->req.actual == req->req.length) ||
958 ((req->req.actual % ep->ep.maxpacket) != 0)) {
959 result = 0;
960 }
961 }
962
963 if (result == 0) {
964 if ((req->req.actual % ep->ep.maxpacket) == 0) {
965 if (req->zero) {
966 req->zero = false;
967 return 1;
968 }
969 }
970 }
971
972 if (req->req.actual > req->req.length) {
973 dev_err(udc->dev, " Overrun Error\n");
974 dev_err(udc->dev, " actual = %d, length = %d\n",
975 req->req.actual, req->req.length);
976 result = -EOVERFLOW;
977 }
978
979 return result;
980 }
981
982 /*-------------------------------------------------------------------------*/
_nbu2ss_in_dma(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 num,u32 length)983 static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
984 struct nbu2ss_req *req, u32 num, u32 length)
985 {
986 dma_addr_t p_buffer;
987 u32 mpkt; /* MaxPacketSize */
988 u32 lmpkt; /* Last Packet Data Size */
989 u32 dmacnt; /* IN Data Size */
990 u32 i_write_length;
991 u32 data;
992 int result = -EINVAL;
993 struct fc_regs __iomem *preg = udc->p_regs;
994
995 if (req->dma_flag)
996 return 1; /* DMA is forwarded */
997
998 #ifdef USE_DMA
999 if (req->req.actual == 0)
1000 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1001 #endif
1002 req->dma_flag = true;
1003
1004 /* MAX Packet Size */
1005 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
1006
1007 i_write_length = min(DMA_MAX_COUNT * mpkt, length);
1008
1009 /*------------------------------------------------------------*/
1010 /* Number of transmission packets */
1011 if (mpkt < i_write_length) {
1012 dmacnt = i_write_length / mpkt;
1013 lmpkt = (i_write_length % mpkt) & ~(u32)0x3;
1014 if (lmpkt != 0)
1015 dmacnt++;
1016 else
1017 lmpkt = mpkt & ~(u32)0x3;
1018
1019 } else {
1020 dmacnt = 1;
1021 lmpkt = i_write_length & ~(u32)0x3;
1022 }
1023
1024 /* Packet setting */
1025 data = mpkt | (lmpkt << 16);
1026 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1027
1028 /* Address setting */
1029 p_buffer = req->req.dma;
1030 p_buffer += req->req.actual;
1031 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
1032
1033 /* Packet and DMA setting */
1034 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN;
1035 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1036
1037 /* Packet setting of EPC */
1038 data = dmacnt << 16;
1039 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1040
1041 /*DMA setting of EPC */
1042 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
1043
1044 result = i_write_length & ~(u32)0x3;
1045 req->div_len = result;
1046
1047 return result;
1048 }
1049
1050 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)1051 static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1052 struct nbu2ss_req *req, u32 length)
1053 {
1054 u8 *p_buffer;
1055 u32 i;
1056 u32 data;
1057 u32 i_word_length;
1058 union usb_reg_access temp_32;
1059 union usb_reg_access *p_buf_32 = NULL;
1060 int result = 0;
1061 struct fc_regs __iomem *preg = udc->p_regs;
1062
1063 if (req->dma_flag)
1064 return 1; /* DMA is forwarded */
1065
1066 if (length > 0) {
1067 p_buffer = (u8 *)req->req.buf;
1068 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
1069
1070 i_word_length = length / sizeof(u32);
1071 if (i_word_length > 0) {
1072 for (i = 0; i < i_word_length; i++) {
1073 _nbu2ss_writel(&preg->EP_REGS[ep->epnum - 1].EP_WRITE,
1074 p_buf_32->dw);
1075
1076 p_buf_32++;
1077 }
1078 result = i_word_length * sizeof(u32);
1079 }
1080 }
1081
1082 if (result != ep->ep.maxpacket) {
1083 data = length - result;
1084 temp_32.dw = 0;
1085 for (i = 0 ; i < data ; i++)
1086 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
1087
1088 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data);
1089 result += data;
1090 }
1091
1092 req->div_len = result;
1093
1094 return result;
1095 }
1096
1097 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)1098 static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1099 struct nbu2ss_req *req, u32 data_size)
1100 {
1101 u32 num;
1102 int nret = 1;
1103
1104 if (ep->epnum == 0)
1105 return -EINVAL;
1106
1107 num = ep->epnum - 1;
1108
1109 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
1110 (data_size >= sizeof(u32))) {
1111 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1112 } else {
1113 data_size = min_t(u32, data_size, ep->ep.maxpacket);
1114 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1115 }
1116
1117 return nret;
1118 }
1119
1120 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1121 static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc,
1122 struct nbu2ss_ep *ep, struct nbu2ss_req *req)
1123 {
1124 u32 num;
1125 u32 i_buf_size;
1126 int result = 0;
1127 u32 status;
1128
1129 if (ep->epnum == 0)
1130 return -EINVAL;
1131
1132 num = ep->epnum - 1;
1133
1134 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1135
1136 /*-------------------------------------------------------------*/
1137 /* State confirmation of FIFO */
1138 if (req->req.actual == 0) {
1139 if ((status & EPN_IN_EMPTY) == 0)
1140 return 1; /* Not Empty */
1141
1142 } else {
1143 if ((status & EPN_IN_FULL) != 0)
1144 return 1; /* Not Empty */
1145 }
1146
1147 /*-------------------------------------------------------------*/
1148 /* Start transfer */
1149 i_buf_size = req->req.length - req->req.actual;
1150 if (i_buf_size > 0)
1151 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size);
1152 else if (req->req.length == 0)
1153 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1154
1155 return result;
1156 }
1157
1158 /*-------------------------------------------------------------------------*/
_nbu2ss_start_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,bool bflag)1159 static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc,
1160 struct nbu2ss_ep *ep,
1161 struct nbu2ss_req *req,
1162 bool bflag)
1163 {
1164 int nret = -EINVAL;
1165
1166 req->dma_flag = false;
1167 req->div_len = 0;
1168
1169 if (req->req.length == 0) {
1170 req->zero = false;
1171 } else {
1172 if ((req->req.length % ep->ep.maxpacket) == 0)
1173 req->zero = req->req.zero;
1174 else
1175 req->zero = false;
1176 }
1177
1178 if (ep->epnum == 0) {
1179 /* EP0 */
1180 switch (udc->ep0state) {
1181 case EP0_IN_DATA_PHASE:
1182 nret = _nbu2ss_ep0_in_transfer(udc, req);
1183 break;
1184
1185 case EP0_OUT_DATA_PHASE:
1186 nret = _nbu2ss_ep0_out_transfer(udc, req);
1187 break;
1188
1189 case EP0_IN_STATUS_PHASE:
1190 nret = EP0_send_NULL(udc, true);
1191 break;
1192
1193 default:
1194 break;
1195 }
1196
1197 } else {
1198 /* EPN */
1199 if (ep->direct == USB_DIR_OUT) {
1200 /* OUT */
1201 if (!bflag)
1202 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1203 } else {
1204 /* IN */
1205 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1206 }
1207 }
1208
1209 return nret;
1210 }
1211
1212 /*-------------------------------------------------------------------------*/
_nbu2ss_restert_transfer(struct nbu2ss_ep * ep)1213 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1214 {
1215 u32 length;
1216 bool bflag = false;
1217 struct nbu2ss_req *req;
1218
1219 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1220 if (!req)
1221 return;
1222
1223 if (ep->epnum > 0) {
1224 length = _nbu2ss_readl(&ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1225
1226 length &= EPN_LDATA;
1227 if (length < ep->ep.maxpacket)
1228 bflag = true;
1229 }
1230
1231 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1232 }
1233
1234 /*-------------------------------------------------------------------------*/
1235 /* Endpoint Toggle Reset */
_nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc * udc,u8 ep_adrs)1236 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs)
1237 {
1238 u8 num;
1239 u32 data;
1240
1241 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1242 return;
1243
1244 num = (ep_adrs & 0x7F) - 1;
1245
1246 if (ep_adrs & USB_DIR_IN)
1247 data = EPN_IPIDCLR;
1248 else
1249 data = EPN_BCLR | EPN_OPIDCLR;
1250
1251 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1252 }
1253
1254 /*-------------------------------------------------------------------------*/
1255 /* Endpoint STALL set */
_nbu2ss_set_endpoint_stall(struct nbu2ss_udc * udc,u8 ep_adrs,bool bstall)1256 static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc,
1257 u8 ep_adrs, bool bstall)
1258 {
1259 u8 num, epnum;
1260 u32 data;
1261 struct nbu2ss_ep *ep;
1262 struct fc_regs __iomem *preg = udc->p_regs;
1263
1264 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1265 if (bstall) {
1266 /* Set STALL */
1267 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1268 } else {
1269 /* Clear STALL */
1270 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1271 }
1272 } else {
1273 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1274 num = epnum - 1;
1275 ep = &udc->ep[epnum];
1276
1277 if (bstall) {
1278 /* Set STALL */
1279 ep->halted = true;
1280
1281 if (ep_adrs & USB_DIR_IN)
1282 data = EPN_BCLR | EPN_ISTL;
1283 else
1284 data = EPN_OSTL_EN | EPN_OSTL;
1285
1286 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1287 } else {
1288 if (ep_adrs & USB_DIR_IN) {
1289 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1290 , EPN_ISTL);
1291 } else {
1292 data =
1293 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1294
1295 data &= ~EPN_OSTL;
1296 data |= EPN_OSTL_EN;
1297
1298 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1299 , data);
1300 }
1301
1302 /* Clear STALL */
1303 ep->stalled = false;
1304 if (ep->halted) {
1305 ep->halted = false;
1306 _nbu2ss_restert_transfer(ep);
1307 }
1308 }
1309 }
1310 }
1311
1312 /*-------------------------------------------------------------------------*/
_nbu2ss_set_test_mode(struct nbu2ss_udc * udc,u32 mode)1313 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1314 {
1315 u32 data;
1316
1317 if (mode > MAX_TEST_MODE_NUM)
1318 return;
1319
1320 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1321
1322 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1323 data &= ~TEST_FORCE_ENABLE;
1324 data |= mode << TEST_MODE_SHIFT;
1325
1326 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1327 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1328 }
1329
1330 /*-------------------------------------------------------------------------*/
_nbu2ss_set_feature_device(struct nbu2ss_udc * udc,u16 selector,u16 wIndex)1331 static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc,
1332 u16 selector, u16 wIndex)
1333 {
1334 int result = -EOPNOTSUPP;
1335
1336 switch (selector) {
1337 case USB_DEVICE_REMOTE_WAKEUP:
1338 if (wIndex == 0x0000) {
1339 udc->remote_wakeup = U2F_ENABLE;
1340 result = 0;
1341 }
1342 break;
1343
1344 case USB_DEVICE_TEST_MODE:
1345 wIndex >>= 8;
1346 if (wIndex <= MAX_TEST_MODE_NUM)
1347 result = 0;
1348 break;
1349
1350 default:
1351 break;
1352 }
1353
1354 return result;
1355 }
1356
1357 /*-------------------------------------------------------------------------*/
_nbu2ss_get_ep_stall(struct nbu2ss_udc * udc,u8 ep_adrs)1358 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1359 {
1360 u8 epnum;
1361 u32 data = 0, bit_data;
1362 struct fc_regs __iomem *preg = udc->p_regs;
1363
1364 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1365 if (epnum == 0) {
1366 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1367 bit_data = EP0_STL;
1368
1369 } else {
1370 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1371 if ((data & EPN_EN) == 0)
1372 return -1;
1373
1374 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1375 bit_data = EPN_ISTL;
1376 else
1377 bit_data = EPN_OSTL;
1378 }
1379
1380 if ((data & bit_data) == 0)
1381 return 0;
1382 return 1;
1383 }
1384
1385 /*-------------------------------------------------------------------------*/
_nbu2ss_req_feature(struct nbu2ss_udc * udc,bool bset)1386 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1387 {
1388 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1389 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1390 u16 selector = le16_to_cpu(udc->ctrl.wValue);
1391 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex);
1392 u8 ep_adrs;
1393 int result = -EOPNOTSUPP;
1394
1395 if ((udc->ctrl.wLength != 0x0000) ||
1396 (direction != USB_DIR_OUT)) {
1397 return -EINVAL;
1398 }
1399
1400 switch (recipient) {
1401 case USB_RECIP_DEVICE:
1402 if (bset)
1403 result =
1404 _nbu2ss_set_feature_device(udc, selector, wIndex);
1405 break;
1406
1407 case USB_RECIP_ENDPOINT:
1408 if (0x0000 == (wIndex & 0xFF70)) {
1409 if (selector == USB_ENDPOINT_HALT) {
1410 ep_adrs = wIndex & 0xFF;
1411 if (!bset) {
1412 _nbu2ss_endpoint_toggle_reset(udc,
1413 ep_adrs);
1414 }
1415
1416 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset);
1417
1418 result = 0;
1419 }
1420 }
1421 break;
1422
1423 default:
1424 break;
1425 }
1426
1427 if (result >= 0)
1428 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1429
1430 return result;
1431 }
1432
1433 /*-------------------------------------------------------------------------*/
_nbu2ss_get_speed(struct nbu2ss_udc * udc)1434 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1435 {
1436 u32 data;
1437 enum usb_device_speed speed = USB_SPEED_FULL;
1438
1439 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1440 if (data & HIGH_SPEED)
1441 speed = USB_SPEED_HIGH;
1442
1443 return speed;
1444 }
1445
1446 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_set_stall(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)1447 static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc,
1448 struct nbu2ss_ep *ep)
1449 {
1450 u8 ep_adrs;
1451 u32 regdata;
1452 int limit_cnt = 0;
1453
1454 struct fc_regs __iomem *preg = udc->p_regs;
1455
1456 if (ep->direct == USB_DIR_IN) {
1457 for (limit_cnt = 0
1458 ; limit_cnt < IN_DATA_EMPTY_COUNT
1459 ; limit_cnt++) {
1460 regdata = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1461
1462 if ((regdata & EPN_IN_DATA) == 0)
1463 break;
1464
1465 mdelay(1);
1466 }
1467 }
1468
1469 ep_adrs = ep->epnum | ep->direct;
1470 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1471 }
1472
1473 /*-------------------------------------------------------------------------*/
std_req_get_status(struct nbu2ss_udc * udc)1474 static int std_req_get_status(struct nbu2ss_udc *udc)
1475 {
1476 u32 length;
1477 u16 status_data = 0;
1478 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1479 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1480 u8 ep_adrs;
1481 int result = -EINVAL;
1482
1483 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN))
1484 return result;
1485
1486 length =
1487 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data));
1488 switch (recipient) {
1489 case USB_RECIP_DEVICE:
1490 if (udc->ctrl.wIndex == 0x0000) {
1491 if (udc->gadget.is_selfpowered)
1492 status_data |= BIT(USB_DEVICE_SELF_POWERED);
1493
1494 if (udc->remote_wakeup)
1495 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
1496
1497 result = 0;
1498 }
1499 break;
1500
1501 case USB_RECIP_ENDPOINT:
1502 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) {
1503 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF);
1504 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1505
1506 if (result > 0)
1507 status_data |= BIT(USB_ENDPOINT_HALT);
1508 }
1509 break;
1510
1511 default:
1512 break;
1513 }
1514
1515 if (result >= 0) {
1516 memcpy(udc->ep0_buf, &status_data, length);
1517 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1518 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1519
1520 } else {
1521 dev_err(udc->dev, " Error GET_STATUS\n");
1522 }
1523
1524 return result;
1525 }
1526
1527 /*-------------------------------------------------------------------------*/
std_req_clear_feature(struct nbu2ss_udc * udc)1528 static int std_req_clear_feature(struct nbu2ss_udc *udc)
1529 {
1530 return _nbu2ss_req_feature(udc, false);
1531 }
1532
1533 /*-------------------------------------------------------------------------*/
std_req_set_feature(struct nbu2ss_udc * udc)1534 static int std_req_set_feature(struct nbu2ss_udc *udc)
1535 {
1536 return _nbu2ss_req_feature(udc, true);
1537 }
1538
1539 /*-------------------------------------------------------------------------*/
std_req_set_address(struct nbu2ss_udc * udc)1540 static int std_req_set_address(struct nbu2ss_udc *udc)
1541 {
1542 int result = 0;
1543 u32 wValue = le16_to_cpu(udc->ctrl.wValue);
1544
1545 if ((udc->ctrl.bRequestType != 0x00) ||
1546 (udc->ctrl.wIndex != 0x0000) ||
1547 (udc->ctrl.wLength != 0x0000)) {
1548 return -EINVAL;
1549 }
1550
1551 if (wValue != (wValue & 0x007F))
1552 return -EINVAL;
1553
1554 wValue <<= USB_ADRS_SHIFT;
1555
1556 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1557 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1558
1559 return result;
1560 }
1561
1562 /*-------------------------------------------------------------------------*/
std_req_set_configuration(struct nbu2ss_udc * udc)1563 static int std_req_set_configuration(struct nbu2ss_udc *udc)
1564 {
1565 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff);
1566
1567 if ((udc->ctrl.wIndex != 0x0000) ||
1568 (udc->ctrl.wLength != 0x0000) ||
1569 (udc->ctrl.bRequestType != 0x00)) {
1570 return -EINVAL;
1571 }
1572
1573 udc->curr_config = config_value;
1574
1575 if (config_value > 0) {
1576 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1577 udc->devstate = USB_STATE_CONFIGURED;
1578
1579 } else {
1580 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1581 udc->devstate = USB_STATE_ADDRESS;
1582 }
1583
1584 return 0;
1585 }
1586
1587 /*-------------------------------------------------------------------------*/
_nbu2ss_read_request_data(struct nbu2ss_udc * udc,u32 * pdata)1588 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1589 {
1590 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1591 pdata++;
1592 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1593 }
1594
1595 /*-------------------------------------------------------------------------*/
_nbu2ss_decode_request(struct nbu2ss_udc * udc)1596 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1597 {
1598 bool bcall_back = true;
1599 int nret = -EINVAL;
1600 struct usb_ctrlrequest *p_ctrl;
1601
1602 p_ctrl = &udc->ctrl;
1603 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1604
1605 /* ep0 state control */
1606 if (p_ctrl->wLength == 0) {
1607 udc->ep0state = EP0_IN_STATUS_PHASE;
1608
1609 } else {
1610 if (p_ctrl->bRequestType & USB_DIR_IN)
1611 udc->ep0state = EP0_IN_DATA_PHASE;
1612 else
1613 udc->ep0state = EP0_OUT_DATA_PHASE;
1614 }
1615
1616 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1617 switch (p_ctrl->bRequest) {
1618 case USB_REQ_GET_STATUS:
1619 nret = std_req_get_status(udc);
1620 bcall_back = false;
1621 break;
1622
1623 case USB_REQ_CLEAR_FEATURE:
1624 nret = std_req_clear_feature(udc);
1625 bcall_back = false;
1626 break;
1627
1628 case USB_REQ_SET_FEATURE:
1629 nret = std_req_set_feature(udc);
1630 bcall_back = false;
1631 break;
1632
1633 case USB_REQ_SET_ADDRESS:
1634 nret = std_req_set_address(udc);
1635 bcall_back = false;
1636 break;
1637
1638 case USB_REQ_SET_CONFIGURATION:
1639 nret = std_req_set_configuration(udc);
1640 break;
1641
1642 default:
1643 break;
1644 }
1645 }
1646
1647 if (!bcall_back) {
1648 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1649 if (nret >= 0) {
1650 /*--------------------------------------*/
1651 /* Status Stage */
1652 nret = EP0_send_NULL(udc, true);
1653 }
1654 }
1655
1656 } else {
1657 spin_unlock(&udc->lock);
1658 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1659 spin_lock(&udc->lock);
1660 }
1661
1662 if (nret < 0)
1663 udc->ep0state = EP0_IDLE;
1664
1665 return nret;
1666 }
1667
1668 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_data_stage(struct nbu2ss_udc * udc)1669 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1670 {
1671 int nret;
1672 struct nbu2ss_req *req;
1673 struct nbu2ss_ep *ep = &udc->ep[0];
1674
1675 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1676 if (!req)
1677 req = &udc->ep0_req;
1678
1679 req->req.actual += req->div_len;
1680 req->div_len = 0;
1681
1682 nret = _nbu2ss_ep0_in_transfer(udc, req);
1683 if (nret == 0) {
1684 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1685 EP0_receive_NULL(udc, true);
1686 }
1687
1688 return 0;
1689 }
1690
1691 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_data_stage(struct nbu2ss_udc * udc)1692 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1693 {
1694 int nret;
1695 struct nbu2ss_req *req;
1696 struct nbu2ss_ep *ep = &udc->ep[0];
1697
1698 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1699 if (!req)
1700 req = &udc->ep0_req;
1701
1702 nret = _nbu2ss_ep0_out_transfer(udc, req);
1703 if (nret == 0) {
1704 udc->ep0state = EP0_IN_STATUS_PHASE;
1705 EP0_send_NULL(udc, true);
1706
1707 } else if (nret < 0) {
1708 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1709 req->req.status = nret;
1710 }
1711
1712 return 0;
1713 }
1714
1715 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_status_stage(struct nbu2ss_udc * udc)1716 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1717 {
1718 struct nbu2ss_req *req;
1719 struct nbu2ss_ep *ep = &udc->ep[0];
1720
1721 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1722 if (!req) {
1723 req = &udc->ep0_req;
1724 if (req->req.complete)
1725 req->req.complete(&ep->ep, &req->req);
1726
1727 } else {
1728 if (req->req.complete)
1729 _nbu2ss_ep_done(ep, req, 0);
1730 }
1731
1732 udc->ep0state = EP0_IDLE;
1733
1734 return 0;
1735 }
1736
1737 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_int(struct nbu2ss_udc * udc)1738 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1739 {
1740 int i;
1741 u32 status;
1742 u32 intr;
1743 int nret = -1;
1744
1745 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1746 intr = status & EP0_STATUS_RW_BIT;
1747 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr);
1748
1749 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1750 | STG_END_INT | EP0_OUT_NULL_INT);
1751
1752 if (status == 0) {
1753 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1754 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1755 return;
1756 }
1757
1758 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1759 udc->gadget.speed = _nbu2ss_get_speed(udc);
1760
1761 for (i = 0; i < EP0_END_XFER; i++) {
1762 switch (udc->ep0state) {
1763 case EP0_IDLE:
1764 if (status & SETUP_INT) {
1765 status = 0;
1766 nret = _nbu2ss_decode_request(udc);
1767 }
1768 break;
1769
1770 case EP0_IN_DATA_PHASE:
1771 if (status & EP0_IN_INT) {
1772 status &= ~EP0_IN_INT;
1773 nret = _nbu2ss_ep0_in_data_stage(udc);
1774 }
1775 break;
1776
1777 case EP0_OUT_DATA_PHASE:
1778 if (status & EP0_OUT_INT) {
1779 status &= ~EP0_OUT_INT;
1780 nret = _nbu2ss_ep0_out_data_stage(udc);
1781 }
1782 break;
1783
1784 case EP0_IN_STATUS_PHASE:
1785 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1786 status &= ~(STG_END_INT | EP0_IN_INT);
1787 nret = _nbu2ss_ep0_status_stage(udc);
1788 }
1789 break;
1790
1791 case EP0_OUT_STATUS_PAHSE:
1792 if ((status & STG_END_INT) || (status & SETUP_INT) ||
1793 (status & EP0_OUT_NULL_INT)) {
1794 status &= ~(STG_END_INT
1795 | EP0_OUT_INT
1796 | EP0_OUT_NULL_INT);
1797
1798 nret = _nbu2ss_ep0_status_stage(udc);
1799 }
1800
1801 break;
1802
1803 default:
1804 status = 0;
1805 break;
1806 }
1807
1808 if (status == 0)
1809 break;
1810 }
1811
1812 if (nret < 0) {
1813 /* Send Stall */
1814 _nbu2ss_set_endpoint_stall(udc, 0, true);
1815 }
1816 }
1817
1818 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_done(struct nbu2ss_ep * ep,struct nbu2ss_req * req,int status)1819 static void _nbu2ss_ep_done(struct nbu2ss_ep *ep,
1820 struct nbu2ss_req *req,
1821 int status)
1822 {
1823 struct nbu2ss_udc *udc = ep->udc;
1824
1825 list_del_init(&req->queue);
1826
1827 if (status == -ECONNRESET)
1828 _nbu2ss_fifo_flush(udc, ep);
1829
1830 if (likely(req->req.status == -EINPROGRESS))
1831 req->req.status = status;
1832
1833 if (ep->stalled) {
1834 _nbu2ss_epn_set_stall(udc, ep);
1835 } else {
1836 if (!list_empty(&ep->queue))
1837 _nbu2ss_restert_transfer(ep);
1838 }
1839
1840 #ifdef USE_DMA
1841 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1842 (req->req.dma != 0))
1843 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1844 #endif
1845
1846 spin_unlock(&udc->lock);
1847 req->req.complete(&ep->ep, &req->req);
1848 spin_lock(&udc->lock);
1849 }
1850
1851 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1852 static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc,
1853 struct nbu2ss_ep *ep,
1854 struct nbu2ss_req *req)
1855 {
1856 int result = 0;
1857 u32 status;
1858
1859 struct fc_regs __iomem *preg = udc->p_regs;
1860
1861 if (req->dma_flag)
1862 return; /* DMA is forwarded */
1863
1864 req->req.actual += req->div_len;
1865 req->div_len = 0;
1866
1867 if (req->req.actual != req->req.length) {
1868 /*---------------------------------------------------------*/
1869 /* remainder of data */
1870 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1871
1872 } else {
1873 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1874 status =
1875 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1876
1877 if ((status & EPN_IN_FULL) == 0) {
1878 /*-----------------------------------------*/
1879 /* 0 Length Packet */
1880 req->zero = false;
1881 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1882 }
1883 return;
1884 }
1885 }
1886
1887 if (result <= 0) {
1888 /*---------------------------------------------------------*/
1889 /* Complete */
1890 _nbu2ss_ep_done(ep, req, result);
1891 }
1892 }
1893
1894 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1895 static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc,
1896 struct nbu2ss_ep *ep,
1897 struct nbu2ss_req *req)
1898 {
1899 int result;
1900
1901 result = _nbu2ss_epn_out_transfer(udc, ep, req);
1902 if (result <= 0)
1903 _nbu2ss_ep_done(ep, req, result);
1904 }
1905
1906 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1907 static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc,
1908 struct nbu2ss_ep *ep,
1909 struct nbu2ss_req *req)
1910 {
1911 u32 mpkt;
1912 u32 size;
1913 struct usb_request *preq;
1914
1915 preq = &req->req;
1916
1917 if (!req->dma_flag)
1918 return;
1919
1920 preq->actual += req->div_len;
1921 req->div_len = 0;
1922 req->dma_flag = false;
1923
1924 #ifdef USE_DMA
1925 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
1926 #endif
1927
1928 if (preq->actual != preq->length) {
1929 _nbu2ss_epn_in_transfer(udc, ep, req);
1930 } else {
1931 mpkt = ep->ep.maxpacket;
1932 size = preq->actual % mpkt;
1933 if (size > 0) {
1934 if (((preq->actual & 0x03) == 0) && (size < mpkt))
1935 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
1936 } else {
1937 _nbu2ss_epn_in_int(udc, ep, req);
1938 }
1939 }
1940 }
1941
1942 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1943 static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc,
1944 struct nbu2ss_ep *ep,
1945 struct nbu2ss_req *req)
1946 {
1947 int i;
1948 u32 num;
1949 u32 dmacnt, ep_dmacnt;
1950 u32 mpkt;
1951 struct fc_regs __iomem *preg = udc->p_regs;
1952
1953 num = ep->epnum - 1;
1954
1955 if (req->req.actual == req->req.length) {
1956 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
1957 req->div_len = 0;
1958 req->dma_flag = false;
1959 _nbu2ss_ep_done(ep, req, 0);
1960 return;
1961 }
1962 }
1963
1964 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
1965 & EPN_DMACNT;
1966 ep_dmacnt >>= 16;
1967
1968 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
1969 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
1970 & DCR1_EPN_DMACNT;
1971 dmacnt >>= 16;
1972 if (ep_dmacnt == dmacnt)
1973 break;
1974 }
1975
1976 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN);
1977
1978 if (dmacnt != 0) {
1979 mpkt = ep->ep.maxpacket;
1980 if ((req->div_len % mpkt) == 0)
1981 req->div_len -= mpkt * dmacnt;
1982 }
1983
1984 if ((req->req.actual % ep->ep.maxpacket) > 0) {
1985 if (req->req.actual == req->div_len) {
1986 req->div_len = 0;
1987 req->dma_flag = false;
1988 _nbu2ss_ep_done(ep, req, 0);
1989 return;
1990 }
1991 }
1992
1993 req->req.actual += req->div_len;
1994 req->div_len = 0;
1995 req->dma_flag = false;
1996
1997 _nbu2ss_epn_out_int(udc, ep, req);
1998 }
1999
2000 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_int(struct nbu2ss_udc * udc,u32 epnum)2001 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2002 {
2003 u32 num;
2004 u32 status;
2005
2006 struct nbu2ss_req *req;
2007 struct nbu2ss_ep *ep = &udc->ep[epnum];
2008
2009 num = epnum - 1;
2010
2011 /* Interrupt Status */
2012 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2013
2014 /* Interrupt Clear */
2015 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status);
2016
2017 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2018 if (!req) {
2019 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
2020 return;
2021 }
2022
2023 if (status & EPN_OUT_END_INT) {
2024 status &= ~EPN_OUT_INT;
2025 _nbu2ss_epn_out_dma_int(udc, ep, req);
2026 }
2027
2028 if (status & EPN_OUT_INT)
2029 _nbu2ss_epn_out_int(udc, ep, req);
2030
2031 if (status & EPN_IN_END_INT) {
2032 status &= ~EPN_IN_INT;
2033 _nbu2ss_epn_in_dma_int(udc, ep, req);
2034 }
2035
2036 if (status & EPN_IN_INT)
2037 _nbu2ss_epn_in_int(udc, ep, req);
2038 }
2039
2040 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_int(struct nbu2ss_udc * udc,u32 epnum)2041 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2042 {
2043 if (epnum == 0)
2044 _nbu2ss_ep0_int(udc);
2045 else
2046 _nbu2ss_epn_int(udc, epnum);
2047 }
2048
2049 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_enable(struct nbu2ss_udc * udc)2050 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2051 {
2052 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2053 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2054 }
2055
2056 /*-------------------------------------------------------------------------*/
_nbu2ss_nuke(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,int status)2057 static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2058 struct nbu2ss_ep *ep,
2059 int status)
2060 {
2061 struct nbu2ss_req *req, *n;
2062
2063 /* Endpoint Disable */
2064 _nbu2ss_epn_exit(udc, ep);
2065
2066 /* DMA Disable */
2067 _nbu2ss_ep_dma_exit(udc, ep);
2068
2069 if (list_empty(&ep->queue))
2070 return 0;
2071
2072 /* called with irqs blocked */
2073 list_for_each_entry_safe(req, n, &ep->queue, queue) {
2074 _nbu2ss_ep_done(ep, req, status);
2075 }
2076
2077 return 0;
2078 }
2079
2080 /*-------------------------------------------------------------------------*/
_nbu2ss_quiesce(struct nbu2ss_udc * udc)2081 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2082 {
2083 struct nbu2ss_ep *ep;
2084
2085 udc->gadget.speed = USB_SPEED_UNKNOWN;
2086
2087 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2088
2089 /* Endpoint n */
2090 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2091 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2092 }
2093 }
2094
2095 /*-------------------------------------------------------------------------*/
_nbu2ss_pullup(struct nbu2ss_udc * udc,int is_on)2096 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2097 {
2098 u32 reg_dt;
2099
2100 if (udc->vbus_active == 0)
2101 return -ESHUTDOWN;
2102
2103 if (is_on) {
2104 /* D+ Pullup */
2105 if (udc->driver) {
2106 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2107 | PUE2) & ~(u32)CONNECTB;
2108
2109 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2110 }
2111
2112 } else {
2113 /* D+ Pulldown */
2114 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2115 & ~(u32)PUE2;
2116
2117 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2118 udc->gadget.speed = USB_SPEED_UNKNOWN;
2119 }
2120
2121 return 0;
2122 }
2123
2124 /*-------------------------------------------------------------------------*/
_nbu2ss_fifo_flush(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)2125 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2126 {
2127 struct fc_regs __iomem *p = udc->p_regs;
2128
2129 if (udc->vbus_active == 0)
2130 return;
2131
2132 if (ep->epnum == 0) {
2133 /* EP0 */
2134 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2135
2136 } else {
2137 /* EPN */
2138 _nbu2ss_ep_dma_abort(udc, ep);
2139 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR);
2140 }
2141 }
2142
2143 /*-------------------------------------------------------------------------*/
_nbu2ss_enable_controller(struct nbu2ss_udc * udc)2144 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2145 {
2146 int waitcnt = 0;
2147
2148 if (udc->udc_enabled)
2149 return 0;
2150
2151 /* Reset */
2152 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2153 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2154
2155 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2156 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2157
2158 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2159
2160 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2161
2162 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2163 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2164
2165 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2166 waitcnt++;
2167 udelay(1); /* 1us wait */
2168 if (waitcnt == EPC_PLL_LOCK_COUNT) {
2169 dev_err(udc->dev, "*** Reset Cancel failed\n");
2170 return -EINVAL;
2171 }
2172 }
2173
2174 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2175
2176 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2177
2178 /* EP0 */
2179 _nbu2ss_ep0_enable(udc);
2180
2181 /* USB Interrupt Enable */
2182 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2183
2184 udc->udc_enabled = true;
2185
2186 return 0;
2187 }
2188
2189 /*-------------------------------------------------------------------------*/
_nbu2ss_reset_controller(struct nbu2ss_udc * udc)2190 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2191 {
2192 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2193 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2194 }
2195
2196 /*-------------------------------------------------------------------------*/
_nbu2ss_disable_controller(struct nbu2ss_udc * udc)2197 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2198 {
2199 if (udc->udc_enabled) {
2200 udc->udc_enabled = false;
2201 _nbu2ss_reset_controller(udc);
2202 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2203 }
2204 }
2205
2206 /*-------------------------------------------------------------------------*/
_nbu2ss_check_vbus(struct nbu2ss_udc * udc)2207 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2208 {
2209 int nret;
2210 u32 reg_dt;
2211
2212 /* chattering */
2213 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2214
2215 /* VBUS ON Check*/
2216 reg_dt = gpiod_get_value(vbus_gpio);
2217 if (reg_dt == 0) {
2218 udc->linux_suspended = 0;
2219
2220 _nbu2ss_reset_controller(udc);
2221 dev_info(udc->dev, " ----- VBUS OFF\n");
2222
2223 if (udc->vbus_active == 1) {
2224 /* VBUS OFF */
2225 udc->vbus_active = 0;
2226 if (udc->usb_suspended) {
2227 udc->usb_suspended = 0;
2228 /* _nbu2ss_reset_controller(udc); */
2229 }
2230 udc->devstate = USB_STATE_NOTATTACHED;
2231
2232 _nbu2ss_quiesce(udc);
2233 if (udc->driver) {
2234 spin_unlock(&udc->lock);
2235 udc->driver->disconnect(&udc->gadget);
2236 spin_lock(&udc->lock);
2237 }
2238
2239 _nbu2ss_disable_controller(udc);
2240 }
2241 } else {
2242 mdelay(5); /* wait (5ms) */
2243 reg_dt = gpiod_get_value(vbus_gpio);
2244 if (reg_dt == 0)
2245 return;
2246
2247 dev_info(udc->dev, " ----- VBUS ON\n");
2248
2249 if (udc->linux_suspended)
2250 return;
2251
2252 if (udc->vbus_active == 0) {
2253 /* VBUS ON */
2254 udc->vbus_active = 1;
2255 udc->devstate = USB_STATE_POWERED;
2256
2257 nret = _nbu2ss_enable_controller(udc);
2258 if (nret < 0) {
2259 _nbu2ss_disable_controller(udc);
2260 udc->vbus_active = 0;
2261 return;
2262 }
2263
2264 _nbu2ss_pullup(udc, 1);
2265
2266 #ifdef UDC_DEBUG_DUMP
2267 _nbu2ss_dump_register(udc);
2268 #endif /* UDC_DEBUG_DUMP */
2269
2270 } else {
2271 if (udc->devstate == USB_STATE_POWERED)
2272 _nbu2ss_pullup(udc, 1);
2273 }
2274 }
2275 }
2276
2277 /*-------------------------------------------------------------------------*/
_nbu2ss_int_bus_reset(struct nbu2ss_udc * udc)2278 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2279 {
2280 udc->devstate = USB_STATE_DEFAULT;
2281 udc->remote_wakeup = 0;
2282
2283 _nbu2ss_quiesce(udc);
2284
2285 udc->ep0state = EP0_IDLE;
2286 }
2287
2288 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_resume(struct nbu2ss_udc * udc)2289 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2290 {
2291 if (udc->usb_suspended == 1) {
2292 udc->usb_suspended = 0;
2293 if (udc->driver && udc->driver->resume) {
2294 spin_unlock(&udc->lock);
2295 udc->driver->resume(&udc->gadget);
2296 spin_lock(&udc->lock);
2297 }
2298 }
2299 }
2300
2301 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_suspend(struct nbu2ss_udc * udc)2302 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2303 {
2304 u32 reg_dt;
2305
2306 if (udc->usb_suspended == 0) {
2307 reg_dt = gpiod_get_value(vbus_gpio);
2308
2309 if (reg_dt == 0)
2310 return;
2311
2312 udc->usb_suspended = 1;
2313 if (udc->driver && udc->driver->suspend) {
2314 spin_unlock(&udc->lock);
2315 udc->driver->suspend(&udc->gadget);
2316 spin_lock(&udc->lock);
2317 }
2318
2319 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2320 }
2321 }
2322
2323 /*-------------------------------------------------------------------------*/
2324 /* VBUS (GPIO153) Interrupt */
_nbu2ss_vbus_irq(int irq,void * _udc)2325 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2326 {
2327 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2328
2329 spin_lock(&udc->lock);
2330 _nbu2ss_check_vbus(udc);
2331 spin_unlock(&udc->lock);
2332
2333 return IRQ_HANDLED;
2334 }
2335
2336 /*-------------------------------------------------------------------------*/
2337 /* Interrupt (udc) */
_nbu2ss_udc_irq(int irq,void * _udc)2338 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2339 {
2340 u8 suspend_flag = 0;
2341 u32 status;
2342 u32 epnum, int_bit;
2343
2344 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2345 struct fc_regs __iomem *preg = udc->p_regs;
2346
2347 if (gpiod_get_value(vbus_gpio) == 0) {
2348 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2349 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2350 return IRQ_HANDLED;
2351 }
2352
2353 spin_lock(&udc->lock);
2354
2355 for (;;) {
2356 if (gpiod_get_value(vbus_gpio) == 0) {
2357 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2358 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2359 status = 0;
2360 } else {
2361 status = _nbu2ss_readl(&preg->USB_INT_STA);
2362 }
2363
2364 if (status == 0)
2365 break;
2366
2367 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2368
2369 if (status & USB_RST_INT) {
2370 /* USB Reset */
2371 _nbu2ss_int_bus_reset(udc);
2372 }
2373
2374 if (status & RSUM_INT) {
2375 /* Resume */
2376 _nbu2ss_int_usb_resume(udc);
2377 }
2378
2379 if (status & SPND_INT) {
2380 /* Suspend */
2381 suspend_flag = 1;
2382 }
2383
2384 if (status & EPN_INT) {
2385 /* EP INT */
2386 int_bit = status >> 8;
2387
2388 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2389 if (0x01 & int_bit)
2390 _nbu2ss_ep_int(udc, epnum);
2391
2392 int_bit >>= 1;
2393
2394 if (int_bit == 0)
2395 break;
2396 }
2397 }
2398 }
2399
2400 if (suspend_flag)
2401 _nbu2ss_int_usb_suspend(udc);
2402
2403 spin_unlock(&udc->lock);
2404
2405 return IRQ_HANDLED;
2406 }
2407
2408 /*-------------------------------------------------------------------------*/
2409 /* usb_ep_ops */
nbu2ss_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)2410 static int nbu2ss_ep_enable(struct usb_ep *_ep,
2411 const struct usb_endpoint_descriptor *desc)
2412 {
2413 u8 ep_type;
2414 unsigned long flags;
2415
2416 struct nbu2ss_ep *ep;
2417 struct nbu2ss_udc *udc;
2418
2419 if (!_ep || !desc) {
2420 pr_err(" *** %s, bad param\n", __func__);
2421 return -EINVAL;
2422 }
2423
2424 ep = container_of(_ep, struct nbu2ss_ep, ep);
2425 if (!ep->udc) {
2426 pr_err(" *** %s, ep == NULL !!\n", __func__);
2427 return -EINVAL;
2428 }
2429
2430 ep_type = usb_endpoint_type(desc);
2431 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) ||
2432 (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2433 pr_err(" *** %s, bat bmAttributes\n", __func__);
2434 return -EINVAL;
2435 }
2436
2437 udc = ep->udc;
2438 if (udc->vbus_active == 0)
2439 return -ESHUTDOWN;
2440
2441 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2442 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2443 return -ESHUTDOWN;
2444 }
2445
2446 spin_lock_irqsave(&udc->lock, flags);
2447
2448 ep->desc = desc;
2449 ep->epnum = usb_endpoint_num(desc);
2450 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2451 ep->ep_type = ep_type;
2452 ep->wedged = 0;
2453 ep->halted = false;
2454 ep->stalled = false;
2455
2456 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2457
2458 /* DMA setting */
2459 _nbu2ss_ep_dma_init(udc, ep);
2460
2461 /* Endpoint setting */
2462 _nbu2ss_ep_init(udc, ep);
2463
2464 spin_unlock_irqrestore(&udc->lock, flags);
2465
2466 return 0;
2467 }
2468
2469 /*-------------------------------------------------------------------------*/
nbu2ss_ep_disable(struct usb_ep * _ep)2470 static int nbu2ss_ep_disable(struct usb_ep *_ep)
2471 {
2472 struct nbu2ss_ep *ep;
2473 struct nbu2ss_udc *udc;
2474 unsigned long flags;
2475
2476 if (!_ep) {
2477 pr_err(" *** %s, bad param\n", __func__);
2478 return -EINVAL;
2479 }
2480
2481 ep = container_of(_ep, struct nbu2ss_ep, ep);
2482 if (!ep->udc) {
2483 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2484 return -EINVAL;
2485 }
2486
2487 udc = ep->udc;
2488 if (udc->vbus_active == 0)
2489 return -ESHUTDOWN;
2490
2491 spin_lock_irqsave(&udc->lock, flags);
2492 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2493 spin_unlock_irqrestore(&udc->lock, flags);
2494
2495 return 0;
2496 }
2497
2498 /*-------------------------------------------------------------------------*/
nbu2ss_ep_alloc_request(struct usb_ep * ep,gfp_t gfp_flags)2499 static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep,
2500 gfp_t gfp_flags)
2501 {
2502 struct nbu2ss_req *req;
2503
2504 req = kzalloc(sizeof(*req), gfp_flags);
2505 if (!req)
2506 return NULL;
2507
2508 #ifdef USE_DMA
2509 req->req.dma = DMA_ADDR_INVALID;
2510 #endif
2511 INIT_LIST_HEAD(&req->queue);
2512
2513 return &req->req;
2514 }
2515
2516 /*-------------------------------------------------------------------------*/
nbu2ss_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)2517 static void nbu2ss_ep_free_request(struct usb_ep *_ep,
2518 struct usb_request *_req)
2519 {
2520 struct nbu2ss_req *req;
2521
2522 if (_req) {
2523 req = container_of(_req, struct nbu2ss_req, req);
2524
2525 kfree(req);
2526 }
2527 }
2528
2529 /*-------------------------------------------------------------------------*/
nbu2ss_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)2530 static int nbu2ss_ep_queue(struct usb_ep *_ep,
2531 struct usb_request *_req, gfp_t gfp_flags)
2532 {
2533 struct nbu2ss_req *req;
2534 struct nbu2ss_ep *ep;
2535 struct nbu2ss_udc *udc;
2536 unsigned long flags;
2537 bool bflag;
2538 int result = -EINVAL;
2539
2540 /* catch various bogus parameters */
2541 if (!_ep || !_req) {
2542 if (!_ep)
2543 pr_err("udc: %s --- _ep == NULL\n", __func__);
2544
2545 if (!_req)
2546 pr_err("udc: %s --- _req == NULL\n", __func__);
2547
2548 return -EINVAL;
2549 }
2550
2551 req = container_of(_req, struct nbu2ss_req, req);
2552 if (unlikely(!_req->complete ||
2553 !_req->buf ||
2554 !list_empty(&req->queue))) {
2555 if (!_req->complete)
2556 pr_err("udc: %s --- !_req->complete\n", __func__);
2557
2558 if (!_req->buf)
2559 pr_err("udc:%s --- !_req->buf\n", __func__);
2560
2561 if (!list_empty(&req->queue))
2562 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2563
2564 return -EINVAL;
2565 }
2566
2567 ep = container_of(_ep, struct nbu2ss_ep, ep);
2568 udc = ep->udc;
2569
2570 if (udc->vbus_active == 0) {
2571 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2572 return -ESHUTDOWN;
2573 }
2574
2575 if (unlikely(!udc->driver)) {
2576 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2577 udc->driver);
2578 return -ESHUTDOWN;
2579 }
2580
2581 spin_lock_irqsave(&udc->lock, flags);
2582
2583 #ifdef USE_DMA
2584 if ((uintptr_t)req->req.buf & 0x3)
2585 req->unaligned = true;
2586 else
2587 req->unaligned = false;
2588
2589 if (req->unaligned) {
2590 if (!ep->virt_buf) {
2591 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE,
2592 &ep->phys_buf,
2593 GFP_ATOMIC | GFP_DMA);
2594 if (!ep->virt_buf) {
2595 spin_unlock_irqrestore(&udc->lock, flags);
2596 return -ENOMEM;
2597 }
2598 }
2599 if (ep->epnum > 0) {
2600 if (ep->direct == USB_DIR_IN)
2601 memcpy(ep->virt_buf, req->req.buf,
2602 req->req.length);
2603 }
2604 }
2605
2606 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2607 (req->req.dma != 0))
2608 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2609 #endif
2610
2611 _req->status = -EINPROGRESS;
2612 _req->actual = 0;
2613
2614 bflag = list_empty(&ep->queue);
2615 list_add_tail(&req->queue, &ep->queue);
2616
2617 if (bflag && !ep->stalled) {
2618 result = _nbu2ss_start_transfer(udc, ep, req, false);
2619 if (result < 0) {
2620 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2621 result);
2622 list_del(&req->queue);
2623 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2624 #ifdef USE_DMA
2625 if (req->req.length < 4 &&
2626 req->req.length == req->req.actual)
2627 #else
2628 if (req->req.length == req->req.actual)
2629 #endif
2630 _nbu2ss_ep_done(ep, req, result);
2631 }
2632 }
2633
2634 spin_unlock_irqrestore(&udc->lock, flags);
2635
2636 return 0;
2637 }
2638
2639 /*-------------------------------------------------------------------------*/
nbu2ss_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)2640 static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2641 {
2642 struct nbu2ss_req *req;
2643 struct nbu2ss_ep *ep;
2644 struct nbu2ss_udc *udc;
2645 unsigned long flags;
2646
2647 /* catch various bogus parameters */
2648 if (!_ep || !_req) {
2649 /* pr_err("%s, bad param(1)\n", __func__); */
2650 return -EINVAL;
2651 }
2652
2653 ep = container_of(_ep, struct nbu2ss_ep, ep);
2654
2655 udc = ep->udc;
2656 if (!udc)
2657 return -EINVAL;
2658
2659 spin_lock_irqsave(&udc->lock, flags);
2660
2661 /* make sure it's actually queued on this endpoint */
2662 list_for_each_entry(req, &ep->queue, queue) {
2663 if (&req->req == _req) {
2664 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2665 spin_unlock_irqrestore(&udc->lock, flags);
2666 return 0;
2667 }
2668 }
2669
2670 spin_unlock_irqrestore(&udc->lock, flags);
2671
2672 pr_debug("%s no queue(EINVAL)\n", __func__);
2673
2674 return -EINVAL;
2675 }
2676
2677 /*-------------------------------------------------------------------------*/
nbu2ss_ep_set_halt(struct usb_ep * _ep,int value)2678 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2679 {
2680 u8 ep_adrs;
2681 unsigned long flags;
2682
2683 struct nbu2ss_ep *ep;
2684 struct nbu2ss_udc *udc;
2685
2686 if (!_ep) {
2687 pr_err("%s, bad param\n", __func__);
2688 return -EINVAL;
2689 }
2690
2691 ep = container_of(_ep, struct nbu2ss_ep, ep);
2692
2693 udc = ep->udc;
2694 if (!udc) {
2695 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2696 return -EINVAL;
2697 }
2698
2699 spin_lock_irqsave(&udc->lock, flags);
2700
2701 ep_adrs = ep->epnum | ep->direct;
2702 if (value == 0) {
2703 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2704 ep->stalled = false;
2705 } else {
2706 if (list_empty(&ep->queue))
2707 _nbu2ss_epn_set_stall(udc, ep);
2708 else
2709 ep->stalled = true;
2710 }
2711
2712 if (value == 0)
2713 ep->wedged = 0;
2714
2715 spin_unlock_irqrestore(&udc->lock, flags);
2716
2717 return 0;
2718 }
2719
nbu2ss_ep_set_wedge(struct usb_ep * _ep)2720 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2721 {
2722 return nbu2ss_ep_set_halt(_ep, 1);
2723 }
2724
2725 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_status(struct usb_ep * _ep)2726 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2727 {
2728 u32 data;
2729 struct nbu2ss_ep *ep;
2730 struct nbu2ss_udc *udc;
2731 unsigned long flags;
2732 struct fc_regs __iomem *preg;
2733
2734 if (!_ep) {
2735 pr_err("%s, bad param\n", __func__);
2736 return -EINVAL;
2737 }
2738
2739 ep = container_of(_ep, struct nbu2ss_ep, ep);
2740
2741 udc = ep->udc;
2742 if (!udc) {
2743 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2744 return -EINVAL;
2745 }
2746
2747 preg = udc->p_regs;
2748
2749 data = gpiod_get_value(vbus_gpio);
2750 if (data == 0)
2751 return -EINVAL;
2752
2753 spin_lock_irqsave(&udc->lock, flags);
2754
2755 if (ep->epnum == 0) {
2756 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2757
2758 } else {
2759 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2760 & EPN_LDATA;
2761 }
2762
2763 spin_unlock_irqrestore(&udc->lock, flags);
2764
2765 return 0;
2766 }
2767
2768 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_flush(struct usb_ep * _ep)2769 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2770 {
2771 u32 data;
2772 struct nbu2ss_ep *ep;
2773 struct nbu2ss_udc *udc;
2774 unsigned long flags;
2775
2776 if (!_ep) {
2777 pr_err("udc: %s, bad param\n", __func__);
2778 return;
2779 }
2780
2781 ep = container_of(_ep, struct nbu2ss_ep, ep);
2782
2783 udc = ep->udc;
2784 if (!udc) {
2785 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2786 return;
2787 }
2788
2789 data = gpiod_get_value(vbus_gpio);
2790 if (data == 0)
2791 return;
2792
2793 spin_lock_irqsave(&udc->lock, flags);
2794 _nbu2ss_fifo_flush(udc, ep);
2795 spin_unlock_irqrestore(&udc->lock, flags);
2796 }
2797
2798 /*-------------------------------------------------------------------------*/
2799 static const struct usb_ep_ops nbu2ss_ep_ops = {
2800 .enable = nbu2ss_ep_enable,
2801 .disable = nbu2ss_ep_disable,
2802
2803 .alloc_request = nbu2ss_ep_alloc_request,
2804 .free_request = nbu2ss_ep_free_request,
2805
2806 .queue = nbu2ss_ep_queue,
2807 .dequeue = nbu2ss_ep_dequeue,
2808
2809 .set_halt = nbu2ss_ep_set_halt,
2810 .set_wedge = nbu2ss_ep_set_wedge,
2811
2812 .fifo_status = nbu2ss_ep_fifo_status,
2813 .fifo_flush = nbu2ss_ep_fifo_flush,
2814 };
2815
2816 /*-------------------------------------------------------------------------*/
2817 /* usb_gadget_ops */
2818
2819 /*-------------------------------------------------------------------------*/
nbu2ss_gad_get_frame(struct usb_gadget * pgadget)2820 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2821 {
2822 u32 data;
2823 struct nbu2ss_udc *udc;
2824
2825 if (!pgadget) {
2826 pr_err("udc: %s, bad param\n", __func__);
2827 return -EINVAL;
2828 }
2829
2830 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2831 data = gpiod_get_value(vbus_gpio);
2832 if (data == 0)
2833 return -EINVAL;
2834
2835 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2836 }
2837
2838 /*-------------------------------------------------------------------------*/
nbu2ss_gad_wakeup(struct usb_gadget * pgadget)2839 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2840 {
2841 int i;
2842 u32 data;
2843
2844 struct nbu2ss_udc *udc;
2845
2846 if (!pgadget) {
2847 pr_err("%s, bad param\n", __func__);
2848 return -EINVAL;
2849 }
2850
2851 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2852
2853 data = gpiod_get_value(vbus_gpio);
2854 if (data == 0) {
2855 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
2856 return -EINVAL;
2857 }
2858
2859 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
2860
2861 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2862 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
2863
2864 if (data & PLL_LOCK)
2865 break;
2866 }
2867
2868 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
2869
2870 return 0;
2871 }
2872
2873 /*-------------------------------------------------------------------------*/
nbu2ss_gad_set_selfpowered(struct usb_gadget * pgadget,int is_selfpowered)2874 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
2875 int is_selfpowered)
2876 {
2877 struct nbu2ss_udc *udc;
2878 unsigned long flags;
2879
2880 if (!pgadget) {
2881 pr_err("%s, bad param\n", __func__);
2882 return -EINVAL;
2883 }
2884
2885 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2886
2887 spin_lock_irqsave(&udc->lock, flags);
2888 pgadget->is_selfpowered = (is_selfpowered != 0);
2889 spin_unlock_irqrestore(&udc->lock, flags);
2890
2891 return 0;
2892 }
2893
2894 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_session(struct usb_gadget * pgadget,int is_active)2895 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
2896 {
2897 return 0;
2898 }
2899
2900 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_draw(struct usb_gadget * pgadget,unsigned int mA)2901 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
2902 {
2903 struct nbu2ss_udc *udc;
2904 unsigned long flags;
2905
2906 if (!pgadget) {
2907 pr_err("%s, bad param\n", __func__);
2908 return -EINVAL;
2909 }
2910
2911 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2912
2913 spin_lock_irqsave(&udc->lock, flags);
2914 udc->mA = mA;
2915 spin_unlock_irqrestore(&udc->lock, flags);
2916
2917 return 0;
2918 }
2919
2920 /*-------------------------------------------------------------------------*/
nbu2ss_gad_pullup(struct usb_gadget * pgadget,int is_on)2921 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
2922 {
2923 struct nbu2ss_udc *udc;
2924 unsigned long flags;
2925
2926 if (!pgadget) {
2927 pr_err("%s, bad param\n", __func__);
2928 return -EINVAL;
2929 }
2930
2931 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2932
2933 if (!udc->driver) {
2934 pr_warn("%s, Not Regist Driver\n", __func__);
2935 return -EINVAL;
2936 }
2937
2938 if (udc->vbus_active == 0)
2939 return -ESHUTDOWN;
2940
2941 spin_lock_irqsave(&udc->lock, flags);
2942 _nbu2ss_pullup(udc, is_on);
2943 spin_unlock_irqrestore(&udc->lock, flags);
2944
2945 return 0;
2946 }
2947
2948 /*-------------------------------------------------------------------------*/
nbu2ss_gad_ioctl(struct usb_gadget * pgadget,unsigned int code,unsigned long param)2949 static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget,
2950 unsigned int code, unsigned long param)
2951 {
2952 return 0;
2953 }
2954
2955 static const struct usb_gadget_ops nbu2ss_gadget_ops = {
2956 .get_frame = nbu2ss_gad_get_frame,
2957 .wakeup = nbu2ss_gad_wakeup,
2958 .set_selfpowered = nbu2ss_gad_set_selfpowered,
2959 .vbus_session = nbu2ss_gad_vbus_session,
2960 .vbus_draw = nbu2ss_gad_vbus_draw,
2961 .pullup = nbu2ss_gad_pullup,
2962 .ioctl = nbu2ss_gad_ioctl,
2963 };
2964
2965 static const struct {
2966 const char *name;
2967 const struct usb_ep_caps caps;
2968 } ep_info[NUM_ENDPOINTS] = {
2969 #define EP_INFO(_name, _caps) \
2970 { \
2971 .name = _name, \
2972 .caps = _caps, \
2973 }
2974
2975 EP_INFO("ep0",
2976 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
2977 EP_INFO("ep1-bulk",
2978 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2979 EP_INFO("ep2-bulk",
2980 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2981 EP_INFO("ep3in-int",
2982 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2983 EP_INFO("ep4-iso",
2984 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2985 EP_INFO("ep5-iso",
2986 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2987 EP_INFO("ep6-bulk",
2988 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2989 EP_INFO("ep7-bulk",
2990 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2991 EP_INFO("ep8in-int",
2992 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2993 EP_INFO("ep9-iso",
2994 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2995 EP_INFO("epa-iso",
2996 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2997 EP_INFO("epb-bulk",
2998 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2999 EP_INFO("epc-bulk",
3000 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3001 EP_INFO("epdin-int",
3002 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3003
3004 #undef EP_INFO
3005 };
3006
3007 /*-------------------------------------------------------------------------*/
nbu2ss_drv_ep_init(struct nbu2ss_udc * udc)3008 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3009 {
3010 int i;
3011
3012 INIT_LIST_HEAD(&udc->gadget.ep_list);
3013 udc->gadget.ep0 = &udc->ep[0].ep;
3014
3015 for (i = 0; i < NUM_ENDPOINTS; i++) {
3016 struct nbu2ss_ep *ep = &udc->ep[i];
3017
3018 ep->udc = udc;
3019 ep->desc = NULL;
3020
3021 ep->ep.driver_data = NULL;
3022 ep->ep.name = ep_info[i].name;
3023 ep->ep.caps = ep_info[i].caps;
3024 ep->ep.ops = &nbu2ss_ep_ops;
3025
3026 usb_ep_set_maxpacket_limit(&ep->ep,
3027 i == 0 ? EP0_PACKETSIZE
3028 : EP_PACKETSIZE);
3029
3030 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3031 INIT_LIST_HEAD(&ep->queue);
3032 }
3033
3034 list_del_init(&udc->ep[0].ep.ep_list);
3035 }
3036
3037 /*-------------------------------------------------------------------------*/
3038 /* platform_driver */
nbu2ss_drv_contest_init(struct platform_device * pdev,struct nbu2ss_udc * udc)3039 static int nbu2ss_drv_contest_init(struct platform_device *pdev,
3040 struct nbu2ss_udc *udc)
3041 {
3042 spin_lock_init(&udc->lock);
3043 udc->dev = &pdev->dev;
3044
3045 udc->gadget.is_selfpowered = 1;
3046 udc->devstate = USB_STATE_NOTATTACHED;
3047 udc->pdev = pdev;
3048 udc->mA = 0;
3049
3050 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3051
3052 /* init Endpoint */
3053 nbu2ss_drv_ep_init(udc);
3054
3055 /* init Gadget */
3056 udc->gadget.ops = &nbu2ss_gadget_ops;
3057 udc->gadget.ep0 = &udc->ep[0].ep;
3058 udc->gadget.speed = USB_SPEED_UNKNOWN;
3059 udc->gadget.name = driver_name;
3060 /* udc->gadget.is_dualspeed = 1; */
3061
3062 device_initialize(&udc->gadget.dev);
3063
3064 dev_set_name(&udc->gadget.dev, "gadget");
3065 udc->gadget.dev.parent = &pdev->dev;
3066 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3067
3068 return 0;
3069 }
3070
3071 /*
3072 * probe - binds to the platform device
3073 */
nbu2ss_drv_probe(struct platform_device * pdev)3074 static int nbu2ss_drv_probe(struct platform_device *pdev)
3075 {
3076 int status;
3077 struct nbu2ss_udc *udc;
3078 int irq;
3079 void __iomem *mmio_base;
3080
3081 udc = &udc_controller;
3082 memset(udc, 0, sizeof(struct nbu2ss_udc));
3083
3084 platform_set_drvdata(pdev, udc);
3085
3086 /* require I/O memory and IRQ to be provided as resources */
3087 mmio_base = devm_platform_ioremap_resource(pdev, 0);
3088 if (IS_ERR(mmio_base))
3089 return PTR_ERR(mmio_base);
3090
3091 irq = platform_get_irq(pdev, 0);
3092 if (irq < 0)
3093 return irq;
3094 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3095 0, driver_name, udc);
3096
3097 /* IO Memory */
3098 udc->p_regs = (struct fc_regs __iomem *)mmio_base;
3099
3100 /* USB Function Controller Interrupt */
3101 if (status != 0) {
3102 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3103 return status;
3104 }
3105
3106 /* Driver Initialization */
3107 status = nbu2ss_drv_contest_init(pdev, udc);
3108 if (status < 0) {
3109 /* Error */
3110 return status;
3111 }
3112
3113 /* VBUS Interrupt */
3114 vbus_irq = gpiod_to_irq(vbus_gpio);
3115 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH);
3116 status = request_irq(vbus_irq,
3117 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3118
3119 if (status != 0) {
3120 dev_err(udc->dev, "request_irq(vbus_irq) failed\n");
3121 return status;
3122 }
3123
3124 return status;
3125 }
3126
3127 /*-------------------------------------------------------------------------*/
nbu2ss_drv_shutdown(struct platform_device * pdev)3128 static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3129 {
3130 struct nbu2ss_udc *udc;
3131
3132 udc = platform_get_drvdata(pdev);
3133 if (!udc)
3134 return;
3135
3136 _nbu2ss_disable_controller(udc);
3137 }
3138
3139 /*-------------------------------------------------------------------------*/
nbu2ss_drv_remove(struct platform_device * pdev)3140 static void nbu2ss_drv_remove(struct platform_device *pdev)
3141 {
3142 struct nbu2ss_udc *udc;
3143 struct nbu2ss_ep *ep;
3144 int i;
3145
3146 udc = &udc_controller;
3147
3148 for (i = 0; i < NUM_ENDPOINTS; i++) {
3149 ep = &udc->ep[i];
3150 if (ep->virt_buf)
3151 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf,
3152 ep->phys_buf);
3153 }
3154
3155 /* Interrupt Handler - Release */
3156 free_irq(vbus_irq, udc);
3157 }
3158
3159 /*-------------------------------------------------------------------------*/
nbu2ss_drv_suspend(struct platform_device * pdev,pm_message_t state)3160 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3161 {
3162 struct nbu2ss_udc *udc;
3163
3164 udc = platform_get_drvdata(pdev);
3165 if (!udc)
3166 return 0;
3167
3168 if (udc->vbus_active) {
3169 udc->vbus_active = 0;
3170 udc->devstate = USB_STATE_NOTATTACHED;
3171 udc->linux_suspended = 1;
3172
3173 if (udc->usb_suspended) {
3174 udc->usb_suspended = 0;
3175 _nbu2ss_reset_controller(udc);
3176 }
3177
3178 _nbu2ss_quiesce(udc);
3179 }
3180 _nbu2ss_disable_controller(udc);
3181
3182 return 0;
3183 }
3184
3185 /*-------------------------------------------------------------------------*/
nbu2ss_drv_resume(struct platform_device * pdev)3186 static int nbu2ss_drv_resume(struct platform_device *pdev)
3187 {
3188 u32 data;
3189 struct nbu2ss_udc *udc;
3190
3191 udc = platform_get_drvdata(pdev);
3192 if (!udc)
3193 return 0;
3194
3195 data = gpiod_get_value(vbus_gpio);
3196 if (data) {
3197 udc->vbus_active = 1;
3198 udc->devstate = USB_STATE_POWERED;
3199 _nbu2ss_enable_controller(udc);
3200 _nbu2ss_pullup(udc, 1);
3201 }
3202
3203 udc->linux_suspended = 0;
3204
3205 return 0;
3206 }
3207
3208 static struct platform_driver udc_driver = {
3209 .probe = nbu2ss_drv_probe,
3210 .shutdown = nbu2ss_drv_shutdown,
3211 .remove_new = nbu2ss_drv_remove,
3212 .suspend = nbu2ss_drv_suspend,
3213 .resume = nbu2ss_drv_resume,
3214 .driver = {
3215 .name = driver_name,
3216 },
3217 };
3218
3219 module_platform_driver(udc_driver);
3220
3221 MODULE_DESCRIPTION(DRIVER_DESC);
3222 MODULE_AUTHOR("Renesas Electronics Corporation");
3223 MODULE_LICENSE("GPL");
3224