xref: /openbmc/qemu/hw/xtensa/xtfpga.c (revision 47771d67)
1 /*
2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *     * Redistributions of source code must retain the above copyright
8  *       notice, this list of conditions and the following disclaimer.
9  *     * Redistributions in binary form must reproduce the above copyright
10  *       notice, this list of conditions and the following disclaimer in the
11  *       documentation and/or other materials provided with the distribution.
12  *     * Neither the name of the Open Source and Linux Lab nor the
13  *       names of its contributors may be used to endorse or promote products
14  *       derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "cpu.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
35 #include "hw/qdev-properties.h"
36 #include "elf.h"
37 #include "exec/memory.h"
38 #include "hw/char/serial.h"
39 #include "net/net.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "chardev/char.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/reset.h"
45 #include "sysemu/runstate.h"
46 #include "qemu/error-report.h"
47 #include "qemu/option.h"
48 #include "bootparam.h"
49 #include "xtensa_memory.h"
50 #include "hw/xtensa/mx_pic.h"
51 #include "migration/vmstate.h"
52 
53 typedef struct XtfpgaFlashDesc {
54     hwaddr base;
55     size_t size;
56     size_t boot_base;
57     size_t sector_size;
58 } XtfpgaFlashDesc;
59 
60 typedef struct XtfpgaBoardDesc {
61     const XtfpgaFlashDesc *flash;
62     size_t sram_size;
63     const hwaddr *io;
64 } XtfpgaBoardDesc;
65 
66 typedef struct XtfpgaFpgaState {
67     MemoryRegion iomem;
68     uint32_t freq;
69     uint32_t leds;
70     uint32_t switches;
71 } XtfpgaFpgaState;
72 
xtfpga_fpga_reset(void * opaque)73 static void xtfpga_fpga_reset(void *opaque)
74 {
75     XtfpgaFpgaState *s = opaque;
76 
77     s->leds = 0;
78     s->switches = 0;
79 }
80 
xtfpga_fpga_read(void * opaque,hwaddr addr,unsigned size)81 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
82         unsigned size)
83 {
84     XtfpgaFpgaState *s = opaque;
85 
86     switch (addr) {
87     case 0x0: /*build date code*/
88         return 0x09272011;
89 
90     case 0x4: /*processor clock frequency, Hz*/
91         return s->freq;
92 
93     case 0x8: /*LEDs (off = 0, on = 1)*/
94         return s->leds;
95 
96     case 0xc: /*DIP switches (off = 0, on = 1)*/
97         return s->switches;
98     }
99     return 0;
100 }
101 
xtfpga_fpga_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)102 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
103         uint64_t val, unsigned size)
104 {
105     XtfpgaFpgaState *s = opaque;
106 
107     switch (addr) {
108     case 0x8: /*LEDs (off = 0, on = 1)*/
109         s->leds = val;
110         break;
111 
112     case 0x10: /*board reset*/
113         if (val == 0xdead) {
114             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
115         }
116         break;
117     }
118 }
119 
120 static const MemoryRegionOps xtfpga_fpga_ops = {
121     .read = xtfpga_fpga_read,
122     .write = xtfpga_fpga_write,
123     .endianness = DEVICE_NATIVE_ENDIAN,
124 };
125 
xtfpga_fpga_init(MemoryRegion * address_space,hwaddr base,uint32_t freq)126 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
127                                          hwaddr base, uint32_t freq)
128 {
129     XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1);
130 
131     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
132                           "xtfpga.fpga", 0x10000);
133     memory_region_add_subregion(address_space, base, &s->iomem);
134     s->freq = freq;
135     xtfpga_fpga_reset(s);
136     qemu_register_reset(xtfpga_fpga_reset, s);
137     return s;
138 }
139 
xtfpga_net_init(MemoryRegion * address_space,hwaddr base,hwaddr descriptors,hwaddr buffers,qemu_irq irq)140 static void xtfpga_net_init(MemoryRegion *address_space,
141         hwaddr base,
142         hwaddr descriptors,
143         hwaddr buffers,
144         qemu_irq irq)
145 {
146     DeviceState *dev;
147     SysBusDevice *s;
148     MemoryRegion *ram;
149 
150     dev = qemu_create_nic_device("open_eth", true, NULL);
151     if (!dev) {
152         return;
153     }
154 
155     s = SYS_BUS_DEVICE(dev);
156     sysbus_realize_and_unref(s, &error_fatal);
157     sysbus_connect_irq(s, 0, irq);
158     memory_region_add_subregion(address_space, base,
159             sysbus_mmio_get_region(s, 0));
160     memory_region_add_subregion(address_space, descriptors,
161             sysbus_mmio_get_region(s, 1));
162 
163     ram = g_malloc(sizeof(*ram));
164     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
165                            &error_fatal);
166     vmstate_register_ram_global(ram);
167     memory_region_add_subregion(address_space, buffers, ram);
168 }
169 
xtfpga_flash_init(MemoryRegion * address_space,const XtfpgaBoardDesc * board,DriveInfo * dinfo,int be)170 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
171                                       const XtfpgaBoardDesc *board,
172                                       DriveInfo *dinfo, int be)
173 {
174     SysBusDevice *s;
175     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
176 
177     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
178     qdev_prop_set_uint32(dev, "num-blocks",
179                          board->flash->size / board->flash->sector_size);
180     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
181     qdev_prop_set_uint8(dev, "width", 2);
182     qdev_prop_set_bit(dev, "big-endian", be);
183     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
184     s = SYS_BUS_DEVICE(dev);
185     sysbus_realize_and_unref(s, &error_fatal);
186     memory_region_add_subregion(address_space, board->flash->base,
187                                 sysbus_mmio_get_region(s, 0));
188     return PFLASH_CFI01(dev);
189 }
190 
translate_phys_addr(void * opaque,uint64_t addr)191 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
192 {
193     XtensaCPU *cpu = opaque;
194 
195     return cpu_get_phys_page_debug(CPU(cpu), addr);
196 }
197 
xtfpga_reset(void * opaque)198 static void xtfpga_reset(void *opaque)
199 {
200     XtensaCPU *cpu = opaque;
201 
202     cpu_reset(CPU(cpu));
203 }
204 
xtfpga_io_read(void * opaque,hwaddr addr,unsigned size)205 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
206         unsigned size)
207 {
208     return 0;
209 }
210 
xtfpga_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)211 static void xtfpga_io_write(void *opaque, hwaddr addr,
212         uint64_t val, unsigned size)
213 {
214 }
215 
216 static const MemoryRegionOps xtfpga_io_ops = {
217     .read = xtfpga_io_read,
218     .write = xtfpga_io_write,
219     .endianness = DEVICE_NATIVE_ENDIAN,
220 };
221 
xtfpga_init(const XtfpgaBoardDesc * board,MachineState * machine)222 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
223 {
224     MemoryRegion *system_memory = get_system_memory();
225     XtensaCPU *cpu = NULL;
226     CPUXtensaState *env = NULL;
227     MemoryRegion *system_io;
228     XtensaMxPic *mx_pic = NULL;
229     qemu_irq *extints;
230     DriveInfo *dinfo;
231     PFlashCFI01 *flash = NULL;
232     const char *kernel_filename = machine->kernel_filename;
233     const char *kernel_cmdline = machine->kernel_cmdline;
234     const char *dtb_filename = machine->dtb;
235     const char *initrd_filename = machine->initrd_filename;
236     const unsigned system_io_size = 224 * MiB;
237     uint32_t freq = 10000000;
238     int n;
239     unsigned int smp_cpus = machine->smp.cpus;
240 
241     if (smp_cpus > 1) {
242         mx_pic = xtensa_mx_pic_init(31);
243         qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
244     }
245     for (n = 0; n < smp_cpus; n++) {
246         CPUXtensaState *cenv = NULL;
247 
248         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
249         cenv = &cpu->env;
250         if (!env) {
251             env = cenv;
252             freq = env->config->clock_freq_khz * 1000;
253         }
254 
255         if (mx_pic) {
256             MemoryRegion *mx_eri;
257 
258             mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
259                                                 xtensa_get_extints(cenv),
260                                                 xtensa_get_runstall(cenv));
261             memory_region_add_subregion(xtensa_get_er_region(cenv),
262                                         0, mx_eri);
263         }
264         cenv->sregs[PRID] = n;
265         xtensa_select_static_vectors(cenv, n != 0);
266         qemu_register_reset(xtfpga_reset, cpu);
267         /* Need MMU initialized prior to ELF loading,
268          * so that ELF gets loaded into virtual addresses
269          */
270         cpu_reset(CPU(cpu));
271     }
272     if (smp_cpus > 1) {
273         extints = xtensa_mx_pic_get_extints(mx_pic);
274     } else {
275         extints = xtensa_get_extints(env);
276     }
277 
278     if (env) {
279         XtensaMemory sysram = env->config->sysram;
280 
281         sysram.location[0].size = machine->ram_size;
282         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
283                                      system_memory);
284         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
285                                      system_memory);
286         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
287                                      system_memory);
288         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
289                                      system_memory);
290         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
291                                      system_memory);
292     }
293 
294     system_io = g_malloc(sizeof(*system_io));
295     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
296                           system_io_size);
297     memory_region_add_subregion(system_memory, board->io[0], system_io);
298     if (board->io[1]) {
299         MemoryRegion *io = g_malloc(sizeof(*io));
300 
301         memory_region_init_alias(io, NULL, "xtfpga.io.cached",
302                                  system_io, 0, system_io_size);
303         memory_region_add_subregion(system_memory, board->io[1], io);
304     }
305     xtfpga_fpga_init(system_io, 0x0d020000, freq);
306     xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]);
307 
308     serial_mm_init(system_io, 0x0d050020, 2, extints[0],
309                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
310 
311     dinfo = drive_get(IF_PFLASH, 0, 0);
312     if (dinfo) {
313         flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN);
314     }
315 
316     /* Use presence of kernel file name as 'boot from SRAM' switch. */
317     if (kernel_filename) {
318         uint32_t entry_point = env->pc;
319         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
320         uint32_t tagptr = env->config->sysrom.location[0].addr +
321             board->sram_size;
322         uint32_t cur_tagptr;
323         BpMemInfo memory_location = {
324             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
325             .start = tswap32(env->config->sysram.location[0].addr),
326             .end = tswap32(env->config->sysram.location[0].addr +
327                            machine->ram_size),
328         };
329         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
330             machine->ram_size : 0x08000000;
331         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
332 
333         lowmem_end += env->config->sysram.location[0].addr;
334         cur_lowmem += env->config->sysram.location[0].addr;
335 
336         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
337                                      system_memory);
338 
339         if (kernel_cmdline) {
340             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
341         }
342         if (dtb_filename) {
343             bp_size += get_tag_size(sizeof(uint32_t));
344         }
345         if (initrd_filename) {
346             bp_size += get_tag_size(sizeof(BpMemInfo));
347         }
348 
349         /* Put kernel bootparameters to the end of that SRAM */
350         tagptr = (tagptr - bp_size) & ~0xff;
351         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
352         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
353                              sizeof(memory_location), &memory_location);
354 
355         if (kernel_cmdline) {
356             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
357                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
358         }
359         if (dtb_filename) {
360             int fdt_size;
361             void *fdt = load_device_tree(dtb_filename, &fdt_size);
362             uint32_t dtb_addr = tswap32(cur_lowmem);
363 
364             if (!fdt) {
365                 error_report("could not load DTB '%s'", dtb_filename);
366                 exit(EXIT_FAILURE);
367             }
368 
369             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
370             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
371                                  sizeof(dtb_addr), &dtb_addr);
372             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
373             g_free(fdt);
374         }
375         if (initrd_filename) {
376             BpMemInfo initrd_location = { 0 };
377             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
378                                            lowmem_end - cur_lowmem);
379 
380             if (initrd_size < 0) {
381                 initrd_size = load_image_targphys(initrd_filename,
382                                                   cur_lowmem,
383                                                   lowmem_end - cur_lowmem);
384             }
385             if (initrd_size < 0) {
386                 error_report("could not load initrd '%s'", initrd_filename);
387                 exit(EXIT_FAILURE);
388             }
389             initrd_location.start = tswap32(cur_lowmem);
390             initrd_location.end = tswap32(cur_lowmem + initrd_size);
391             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
392                                  sizeof(initrd_location), &initrd_location);
393             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
394         }
395         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
396         env->regs[2] = tagptr;
397 
398         uint64_t elf_entry;
399         int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
400                                &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
401                                EM_XTENSA, 0, 0);
402         if (success > 0) {
403             entry_point = elf_entry;
404         } else {
405             hwaddr ep;
406             int is_linux;
407             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
408                                   translate_phys_addr, cpu);
409             if (success > 0 && is_linux) {
410                 entry_point = ep;
411             } else {
412                 error_report("could not load kernel '%s'",
413                              kernel_filename);
414                 exit(EXIT_FAILURE);
415             }
416         }
417         if (entry_point != env->pc) {
418             uint8_t boot[] = {
419 #if TARGET_BIG_ENDIAN
420                 0x60, 0x00, 0x08,       /* j    1f */
421                 0x00,                   /* .literal_position */
422                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
423                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
424                                         /* 1: */
425                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
426                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
427                 0x0a, 0x00, 0x00,       /* jx   a0 */
428 #else
429                 0x06, 0x02, 0x00,       /* j    1f */
430                 0x00,                   /* .literal_position */
431                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
432                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
433                                         /* 1: */
434                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
435                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
436                 0xa0, 0x00, 0x00,       /* jx   a0 */
437 #endif
438             };
439             uint32_t entry_pc = tswap32(entry_point);
440             uint32_t entry_a2 = tswap32(tagptr);
441 
442             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
443             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
444             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
445         }
446     } else {
447         if (flash) {
448             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
449             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
450             uint32_t size = env->config->sysrom.location[0].size;
451 
452             if (board->flash->size - board->flash->boot_base < size) {
453                 size = board->flash->size - board->flash->boot_base;
454             }
455 
456             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
457                                      flash_mr, board->flash->boot_base, size);
458             memory_region_add_subregion(system_memory,
459                                         env->config->sysrom.location[0].addr,
460                                         flash_io);
461         } else {
462             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
463                                          system_memory);
464         }
465     }
466 }
467 
468 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
469 
470 static const hwaddr xtfpga_mmu_io[2] = {
471     0xf0000000,
472 };
473 
474 static const hwaddr xtfpga_nommu_io[2] = {
475     0x90000000,
476     0x70000000,
477 };
478 
479 static const XtfpgaFlashDesc lx60_flash = {
480     .base = 0x08000000,
481     .size = 0x00400000,
482     .sector_size = 0x10000,
483 };
484 
xtfpga_lx60_init(MachineState * machine)485 static void xtfpga_lx60_init(MachineState *machine)
486 {
487     static const XtfpgaBoardDesc lx60_board = {
488         .flash = &lx60_flash,
489         .sram_size = 0x20000,
490         .io = xtfpga_mmu_io,
491     };
492     xtfpga_init(&lx60_board, machine);
493 }
494 
xtfpga_lx60_nommu_init(MachineState * machine)495 static void xtfpga_lx60_nommu_init(MachineState *machine)
496 {
497     static const XtfpgaBoardDesc lx60_board = {
498         .flash = &lx60_flash,
499         .sram_size = 0x20000,
500         .io = xtfpga_nommu_io,
501     };
502     xtfpga_init(&lx60_board, machine);
503 }
504 
505 static const XtfpgaFlashDesc lx200_flash = {
506     .base = 0x08000000,
507     .size = 0x01000000,
508     .sector_size = 0x20000,
509 };
510 
xtfpga_lx200_init(MachineState * machine)511 static void xtfpga_lx200_init(MachineState *machine)
512 {
513     static const XtfpgaBoardDesc lx200_board = {
514         .flash = &lx200_flash,
515         .sram_size = 0x2000000,
516         .io = xtfpga_mmu_io,
517     };
518     xtfpga_init(&lx200_board, machine);
519 }
520 
xtfpga_lx200_nommu_init(MachineState * machine)521 static void xtfpga_lx200_nommu_init(MachineState *machine)
522 {
523     static const XtfpgaBoardDesc lx200_board = {
524         .flash = &lx200_flash,
525         .sram_size = 0x2000000,
526         .io = xtfpga_nommu_io,
527     };
528     xtfpga_init(&lx200_board, machine);
529 }
530 
531 static const XtfpgaFlashDesc ml605_flash = {
532     .base = 0x08000000,
533     .size = 0x01000000,
534     .sector_size = 0x20000,
535 };
536 
xtfpga_ml605_init(MachineState * machine)537 static void xtfpga_ml605_init(MachineState *machine)
538 {
539     static const XtfpgaBoardDesc ml605_board = {
540         .flash = &ml605_flash,
541         .sram_size = 0x2000000,
542         .io = xtfpga_mmu_io,
543     };
544     xtfpga_init(&ml605_board, machine);
545 }
546 
xtfpga_ml605_nommu_init(MachineState * machine)547 static void xtfpga_ml605_nommu_init(MachineState *machine)
548 {
549     static const XtfpgaBoardDesc ml605_board = {
550         .flash = &ml605_flash,
551         .sram_size = 0x2000000,
552         .io = xtfpga_nommu_io,
553     };
554     xtfpga_init(&ml605_board, machine);
555 }
556 
557 static const XtfpgaFlashDesc kc705_flash = {
558     .base = 0x00000000,
559     .size = 0x08000000,
560     .boot_base = 0x06000000,
561     .sector_size = 0x20000,
562 };
563 
xtfpga_kc705_init(MachineState * machine)564 static void xtfpga_kc705_init(MachineState *machine)
565 {
566     static const XtfpgaBoardDesc kc705_board = {
567         .flash = &kc705_flash,
568         .sram_size = 0x2000000,
569         .io = xtfpga_mmu_io,
570     };
571     xtfpga_init(&kc705_board, machine);
572 }
573 
xtfpga_kc705_nommu_init(MachineState * machine)574 static void xtfpga_kc705_nommu_init(MachineState *machine)
575 {
576     static const XtfpgaBoardDesc kc705_board = {
577         .flash = &kc705_flash,
578         .sram_size = 0x2000000,
579         .io = xtfpga_nommu_io,
580     };
581     xtfpga_init(&kc705_board, machine);
582 }
583 
xtfpga_lx60_class_init(ObjectClass * oc,void * data)584 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
585 {
586     MachineClass *mc = MACHINE_CLASS(oc);
587 
588     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
589     mc->init = xtfpga_lx60_init;
590     mc->max_cpus = 32;
591     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
592     mc->default_ram_size = 64 * MiB;
593 }
594 
595 static const TypeInfo xtfpga_lx60_type = {
596     .name = MACHINE_TYPE_NAME("lx60"),
597     .parent = TYPE_MACHINE,
598     .class_init = xtfpga_lx60_class_init,
599 };
600 
xtfpga_lx60_nommu_class_init(ObjectClass * oc,void * data)601 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
602 {
603     MachineClass *mc = MACHINE_CLASS(oc);
604 
605     mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
606     mc->init = xtfpga_lx60_nommu_init;
607     mc->max_cpus = 32;
608     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
609     mc->default_ram_size = 64 * MiB;
610 }
611 
612 static const TypeInfo xtfpga_lx60_nommu_type = {
613     .name = MACHINE_TYPE_NAME("lx60-nommu"),
614     .parent = TYPE_MACHINE,
615     .class_init = xtfpga_lx60_nommu_class_init,
616 };
617 
xtfpga_lx200_class_init(ObjectClass * oc,void * data)618 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
619 {
620     MachineClass *mc = MACHINE_CLASS(oc);
621 
622     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
623     mc->init = xtfpga_lx200_init;
624     mc->max_cpus = 32;
625     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
626     mc->default_ram_size = 96 * MiB;
627 }
628 
629 static const TypeInfo xtfpga_lx200_type = {
630     .name = MACHINE_TYPE_NAME("lx200"),
631     .parent = TYPE_MACHINE,
632     .class_init = xtfpga_lx200_class_init,
633 };
634 
xtfpga_lx200_nommu_class_init(ObjectClass * oc,void * data)635 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
636 {
637     MachineClass *mc = MACHINE_CLASS(oc);
638 
639     mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
640     mc->init = xtfpga_lx200_nommu_init;
641     mc->max_cpus = 32;
642     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
643     mc->default_ram_size = 96 * MiB;
644 }
645 
646 static const TypeInfo xtfpga_lx200_nommu_type = {
647     .name = MACHINE_TYPE_NAME("lx200-nommu"),
648     .parent = TYPE_MACHINE,
649     .class_init = xtfpga_lx200_nommu_class_init,
650 };
651 
xtfpga_ml605_class_init(ObjectClass * oc,void * data)652 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
653 {
654     MachineClass *mc = MACHINE_CLASS(oc);
655 
656     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
657     mc->init = xtfpga_ml605_init;
658     mc->max_cpus = 32;
659     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
660     mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
661 }
662 
663 static const TypeInfo xtfpga_ml605_type = {
664     .name = MACHINE_TYPE_NAME("ml605"),
665     .parent = TYPE_MACHINE,
666     .class_init = xtfpga_ml605_class_init,
667 };
668 
xtfpga_ml605_nommu_class_init(ObjectClass * oc,void * data)669 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
670 {
671     MachineClass *mc = MACHINE_CLASS(oc);
672 
673     mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
674     mc->init = xtfpga_ml605_nommu_init;
675     mc->max_cpus = 32;
676     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
677     mc->default_ram_size = 256 * MiB;
678 }
679 
680 static const TypeInfo xtfpga_ml605_nommu_type = {
681     .name = MACHINE_TYPE_NAME("ml605-nommu"),
682     .parent = TYPE_MACHINE,
683     .class_init = xtfpga_ml605_nommu_class_init,
684 };
685 
xtfpga_kc705_class_init(ObjectClass * oc,void * data)686 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
687 {
688     MachineClass *mc = MACHINE_CLASS(oc);
689 
690     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
691     mc->init = xtfpga_kc705_init;
692     mc->max_cpus = 32;
693     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
694     mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
695 }
696 
697 static const TypeInfo xtfpga_kc705_type = {
698     .name = MACHINE_TYPE_NAME("kc705"),
699     .parent = TYPE_MACHINE,
700     .class_init = xtfpga_kc705_class_init,
701 };
702 
xtfpga_kc705_nommu_class_init(ObjectClass * oc,void * data)703 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
704 {
705     MachineClass *mc = MACHINE_CLASS(oc);
706 
707     mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
708     mc->init = xtfpga_kc705_nommu_init;
709     mc->max_cpus = 32;
710     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
711     mc->default_ram_size = 256 * MiB;
712 }
713 
714 static const TypeInfo xtfpga_kc705_nommu_type = {
715     .name = MACHINE_TYPE_NAME("kc705-nommu"),
716     .parent = TYPE_MACHINE,
717     .class_init = xtfpga_kc705_nommu_class_init,
718 };
719 
xtfpga_machines_init(void)720 static void xtfpga_machines_init(void)
721 {
722     type_register_static(&xtfpga_lx60_type);
723     type_register_static(&xtfpga_lx200_type);
724     type_register_static(&xtfpga_ml605_type);
725     type_register_static(&xtfpga_kc705_type);
726     type_register_static(&xtfpga_lx60_nommu_type);
727     type_register_static(&xtfpga_lx200_nommu_type);
728     type_register_static(&xtfpga_ml605_nommu_type);
729     type_register_static(&xtfpga_kc705_nommu_type);
730 }
731 
732 type_init(xtfpga_machines_init)
733