1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/machines-qom.h" 18 #include "hw/block/flash.h" 19 #include "hw/gpio/pca9552.h" 20 #include "hw/gpio/pca9554.h" 21 #include "system/block-backend.h" 22 #include "qemu/error-report.h" 23 #include "qemu/units.h" 24 #include "hw/qdev-clock.h" 25 #include "system/system.h" 26 27 static struct arm_boot_info aspeed_board_binfo = { 28 .board_id = -1, /* device-tree-only board */ 29 }; 30 31 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 32 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 33 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 34 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 35 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 36 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 37 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 38 39 static void aspeed_write_smpboot(ARMCPU *cpu, 40 const struct arm_boot_info *info) 41 { 42 AddressSpace *as = arm_boot_address_space(cpu, info); 43 static const ARMInsnFixup poll_mailbox_ready[] = { 44 /* 45 * r2 = per-cpu go sign value 46 * r1 = AST_SMP_MBOX_FIELD_ENTRY 47 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 48 */ 49 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 50 { 0xe21000ff }, /* ands r0, r0, #255 */ 51 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 52 { 0xe1822000 }, /* orr r2, r2, r0 */ 53 54 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 55 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 56 57 { 0xe320f002 }, /* wfe */ 58 { 0xe5904000 }, /* ldr r4, [r0] */ 59 { 0xe1520004 }, /* cmp r2, r4 */ 60 { 0x1afffffb }, /* bne <wfe> */ 61 { 0xe591f000 }, /* ldr pc, [r1] */ 62 { AST_SMP_MBOX_GOSIGN }, 63 { AST_SMP_MBOX_FIELD_ENTRY }, 64 { AST_SMP_MBOX_FIELD_GOSIGN }, 65 { 0, FIXUP_TERMINATOR } 66 }; 67 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 68 69 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 70 poll_mailbox_ready, fixupcontext); 71 } 72 73 static void aspeed_reset_secondary(ARMCPU *cpu, 74 const struct arm_boot_info *info) 75 { 76 AddressSpace *as = arm_boot_address_space(cpu, info); 77 CPUState *cs = CPU(cpu); 78 79 /* info->smp_bootreg_addr */ 80 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 81 MEMTXATTRS_UNSPECIFIED, NULL); 82 cpu_set_pc(cs, info->smp_loader_start); 83 } 84 85 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 86 bool boot_emmc) 87 { 88 DeviceState *card; 89 90 if (!dinfo) { 91 return; 92 } 93 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 94 95 /* 96 * Force the boot properties of the eMMC device only when the 97 * machine is strapped to boot from eMMC. Without these 98 * settings, the machine would not boot. 99 * 100 * This also allows the machine to use an eMMC device without 101 * boot areas when booting from the flash device (or -kernel) 102 * Ideally, the device and its properties should be defined on 103 * the command line. 104 */ 105 if (emmc && boot_emmc) { 106 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 107 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 108 } 109 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 110 &error_fatal); 111 qdev_realize_and_unref(card, 112 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 113 &error_fatal); 114 } 115 116 void aspeed_connect_serial_hds_to_uarts(AspeedMachineState *bmc) 117 { 118 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 119 AspeedSoCState *s = bmc->soc; 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 122 123 aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base, 124 sc->uarts_num, serial_hd(0)); 125 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 126 if (uart == uart_chosen) { 127 continue; 128 } 129 aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_num, 130 serial_hd(i++)); 131 } 132 } 133 134 static void aspeed_machine_init(MachineState *machine) 135 { 136 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 137 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 138 AspeedSoCClass *sc; 139 int i; 140 const char *bios_name = NULL; 141 DriveInfo *emmc0 = NULL; 142 bool boot_emmc; 143 144 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 145 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 146 object_unref(OBJECT(bmc->soc)); 147 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 148 149 /* 150 * This will error out if the RAM size is not supported by the 151 * memory controller of the SoC. 152 */ 153 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 154 &error_fatal); 155 156 for (i = 0; i < sc->macs_num; i++) { 157 if ((amc->macs_mask & (1 << i)) && 158 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 159 true, NULL)) { 160 break; /* No configs left; stop asking */ 161 } 162 } 163 164 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 165 &error_abort); 166 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 167 &error_abort); 168 object_property_set_link(OBJECT(bmc->soc), "memory", 169 OBJECT(get_system_memory()), &error_abort); 170 object_property_set_link(OBJECT(bmc->soc), "dram", 171 OBJECT(machine->ram), &error_abort); 172 if (amc->sdhci_wp_inverted) { 173 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 174 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 175 "wp-inverted", true, &error_abort); 176 } 177 } 178 if (machine->kernel_filename) { 179 /* 180 * When booting with a -kernel command line there is no u-boot 181 * that runs to unlock the SCU. In this case set the default to 182 * be unlocked as the kernel expects 183 */ 184 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 185 ASPEED_SCU_PROT_KEY, &error_abort); 186 } 187 aspeed_connect_serial_hds_to_uarts(bmc); 188 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 189 190 if (defaults_enabled()) { 191 aspeed_board_init_flashes(&bmc->soc->fmc, 192 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 193 amc->num_cs, 0); 194 aspeed_board_init_flashes(&bmc->soc->spi[0], 195 bmc->spi_model ? bmc->spi_model : amc->spi_model, 196 1, amc->num_cs); 197 aspeed_board_init_flashes(&bmc->soc->spi[1], 198 amc->spi2_model, 1, amc->num_cs2); 199 } 200 201 if (machine->kernel_filename && sc->num_cpus > 1) { 202 /* With no u-boot we must set up a boot stub for the secondary CPU */ 203 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 204 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 205 0x80, &error_abort); 206 memory_region_add_subregion(get_system_memory(), 207 AST_SMP_MAILBOX_BASE, smpboot); 208 209 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 210 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 211 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 212 } 213 214 aspeed_board_binfo.ram_size = machine->ram_size; 215 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 216 217 if (amc->i2c_init) { 218 amc->i2c_init(bmc); 219 } 220 221 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 222 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 223 drive_get(IF_SD, 0, i), false, false); 224 } 225 226 boot_emmc = sc->boot_from_emmc(bmc->soc); 227 228 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 229 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 230 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 231 } 232 233 if (!bmc->mmio_exec) { 234 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 235 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 236 237 if (fmc0 && !boot_emmc) { 238 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 239 aspeed_install_boot_rom(bmc->soc, fmc0, &bmc->boot_rom, rom_size); 240 } else if (emmc0) { 241 aspeed_install_boot_rom(bmc->soc, blk_by_legacy_dinfo(emmc0), 242 &bmc->boot_rom, 64 * KiB); 243 } 244 } 245 246 if (amc->vbootrom) { 247 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; 248 aspeed_load_vbootrom(bmc->soc, bios_name, &error_abort); 249 } 250 251 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 252 } 253 254 void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 255 { 256 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 257 TYPE_PCA9552, addr); 258 } 259 260 I2CSlave *aspeed_create_pca9554(AspeedSoCState *soc, int bus_id, int addr) 261 { 262 return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 263 TYPE_PCA9554, addr); 264 } 265 266 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 267 { 268 return ASPEED_MACHINE(obj)->mmio_exec; 269 } 270 271 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 272 { 273 ASPEED_MACHINE(obj)->mmio_exec = value; 274 } 275 276 static void aspeed_machine_instance_init(Object *obj) 277 { 278 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 279 280 ASPEED_MACHINE(obj)->mmio_exec = false; 281 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 282 } 283 284 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 285 { 286 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 287 return g_strdup(bmc->fmc_model); 288 } 289 290 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 291 { 292 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 293 294 g_free(bmc->fmc_model); 295 bmc->fmc_model = g_strdup(value); 296 } 297 298 static char *aspeed_get_spi_model(Object *obj, Error **errp) 299 { 300 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 301 return g_strdup(bmc->spi_model); 302 } 303 304 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 305 { 306 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 307 308 g_free(bmc->spi_model); 309 bmc->spi_model = g_strdup(value); 310 } 311 312 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 313 { 314 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 315 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 316 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 317 318 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 319 } 320 321 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 322 { 323 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 324 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 325 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 326 int val; 327 int uart_first = aspeed_uart_first(sc->uarts_base); 328 int uart_last = aspeed_uart_last(sc->uarts_base, sc->uarts_num); 329 330 if (sscanf(value, "uart%u", &val) != 1) { 331 error_setg(errp, "Bad value for \"uart\" property"); 332 return; 333 } 334 335 /* The number of UART depends on the SoC */ 336 if (val < uart_first || val > uart_last) { 337 error_setg(errp, "\"uart\" should be in range [%d - %d]", 338 uart_first, uart_last); 339 return; 340 } 341 bmc->uart_chosen = val + ASPEED_DEV_UART0; 342 } 343 344 static void aspeed_machine_class_props_init(ObjectClass *oc) 345 { 346 object_class_property_add_bool(oc, "execute-in-place", 347 aspeed_get_mmio_exec, 348 aspeed_set_mmio_exec); 349 object_class_property_set_description(oc, "execute-in-place", 350 "boot directly from CE0 flash device"); 351 352 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 353 aspeed_set_bmc_console); 354 object_class_property_set_description(oc, "bmc-console", 355 "Change the default UART to \"uartX\""); 356 357 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 358 aspeed_set_fmc_model); 359 object_class_property_set_description(oc, "fmc-model", 360 "Change the FMC Flash model"); 361 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 362 aspeed_set_spi_model); 363 object_class_property_set_description(oc, "spi-model", 364 "Change the SPI Flash model"); 365 } 366 367 void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 368 { 369 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 370 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 371 372 mc->default_cpus = sc->num_cpus; 373 mc->min_cpus = sc->num_cpus; 374 mc->max_cpus = sc->num_cpus; 375 mc->valid_cpu_types = sc->valid_cpu_types; 376 } 377 378 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 379 { 380 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 381 382 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 383 } 384 385 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 386 Error **errp) 387 { 388 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 389 390 if (value) { 391 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 392 } else { 393 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 394 } 395 } 396 397 void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 398 { 399 object_class_property_add_bool(oc, "boot-emmc", 400 aspeed_machine_ast2600_get_boot_from_emmc, 401 aspeed_machine_ast2600_set_boot_from_emmc); 402 object_class_property_set_description(oc, "boot-emmc", 403 "Set or unset boot from EMMC"); 404 } 405 406 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 407 { 408 MachineClass *mc = MACHINE_CLASS(oc); 409 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 410 411 mc->init = aspeed_machine_init; 412 mc->no_floppy = 1; 413 mc->no_cdrom = 1; 414 mc->no_parallel = 1; 415 mc->default_ram_id = "ram"; 416 amc->macs_mask = ASPEED_MAC0_ON; 417 amc->uart_default = ASPEED_DEV_UART5; 418 419 aspeed_machine_class_props_init(oc); 420 } 421 422 static const TypeInfo aspeed_machine_types[] = { 423 { 424 .name = TYPE_ASPEED_MACHINE, 425 .parent = TYPE_MACHINE, 426 .instance_size = sizeof(AspeedMachineState), 427 .instance_init = aspeed_machine_instance_init, 428 .class_size = sizeof(AspeedMachineClass), 429 .class_init = aspeed_machine_class_init, 430 .abstract = true, 431 } 432 }; 433 434 DEFINE_TYPES(aspeed_machine_types) 435