1 /*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 /*
14 * fuloong 2e mini pc has a bonito north bridge.
15 */
16
17 /*
18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
19 *
20 * devfn pci_slot<<3 + funno
21 * one pci bus can have 32 devices and each device can have 8 functions.
22 *
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
24 * For example, PCI_IDSEL_VIA686B = 17,
25 * pci slot = 17-12=5
26 *
27 * so
28 * VT686B_FUN0's devfn = (5<<3)+0
29 * VT686B_FUN1's devfn = (5<<3)+1
30 *
31 * qemu also uses pci address for north bridge to access pci config register.
32 * bus_no [23:16]
33 * dev_no [15:11]
34 * fun_no [10:8]
35 * reg_no [7:2]
36 *
37 * so function bonito_sbridge_pciaddr for the translation from
38 * north bridge address to pci address.
39 */
40
41 #include "qemu/osdep.h"
42 #include "qemu/units.h"
43 #include "qapi/error.h"
44 #include "qemu/error-report.h"
45 #include "hw/pci/pci_device.h"
46 #include "hw/irq.h"
47 #include "hw/mips/mips.h"
48 #include "hw/pci-host/bonito.h"
49 #include "hw/pci/pci_host.h"
50 #include "migration/vmstate.h"
51 #include "sysemu/runstate.h"
52 #include "hw/misc/unimp.h"
53 #include "hw/registerfields.h"
54 #include "qom/object.h"
55 #include "trace.h"
56
57 /* #define DEBUG_BONITO */
58
59 #ifdef DEBUG_BONITO
60 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
61 #else
62 #define DPRINTF(fmt, ...)
63 #endif
64
65 /* from linux source code. include/asm-mips/mips-boards/bonito64.h*/
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
68 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
71 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
74 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
77 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
78 #define BONITO_DEV_BASE 0x1ff00000
79 #define BONITO_DEV_SIZE 0x00100000
80 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
81 #define BONITO_PCILO_BASE 0x10000000
82 #define BONITO_PCILO_BASE_VA 0xb0000000
83 #define BONITO_PCILO_SIZE 0x0c000000
84 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
85 #define BONITO_PCILO0_BASE 0x10000000
86 #define BONITO_PCILO1_BASE 0x14000000
87 #define BONITO_PCILO2_BASE 0x18000000
88 #define BONITO_PCIHI_BASE 0x20000000
89 #define BONITO_PCIHI_SIZE 0x60000000
90 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
91 #define BONITO_PCIIO_BASE 0x1fd00000
92 #define BONITO_PCIIO_BASE_VA 0xbfd00000
93 #define BONITO_PCIIO_SIZE 0x00010000
94 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
95 #define BONITO_PCICFG_BASE 0x1fe80000
96 #define BONITO_PCICFG_SIZE 0x00080000
97 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
98
99
100 #define BONITO_PCICONFIGBASE 0x00
101 #define BONITO_REGBASE 0x100
102
103 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
104 #define BONITO_PCICONFIG_SIZE (0x100)
105
106 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
107 #define BONITO_INTERNAL_REG_SIZE (0x70)
108
109 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
110 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
111
112
113
114 /* 1. Bonito h/w Configuration */
115 /* Power on register */
116
117 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
118
119 /* PCI configuration register */
120 #define BONITO_BONGENCFG_OFFSET 0x4
121 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
122 REG32(BONGENCFG, 0x104)
123 FIELD(BONGENCFG, DEBUGMODE, 0, 1)
124 FIELD(BONGENCFG, SNOOP, 1, 1)
125 FIELD(BONGENCFG, CPUSELFRESET, 2, 1)
126 FIELD(BONGENCFG, BYTESWAP, 6, 1)
127 FIELD(BONGENCFG, UNCACHED, 7, 1)
128 FIELD(BONGENCFG, PREFETCH, 8, 1)
129 FIELD(BONGENCFG, WRITEBEHIND, 9, 1)
130 FIELD(BONGENCFG, PCIQUEUE, 12, 1)
131
132 /* 2. IO & IDE configuration */
133 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
134
135 /* 3. IO & IDE configuration */
136 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
137
138 /* 4. PCI address map control */
139 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
140 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
141 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
142
143 /* 5. ICU & GPIO regs */
144 /* GPIO Regs - r/w */
145 #define BONITO_GPIODATA_OFFSET 0x1c
146 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
147 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
148
149 /* ICU Configuration Regs - r/w */
150 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
151 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
152 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
153
154 /* ICU Enable Regs - IntEn & IntISR are r/o. */
155 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
156 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
157 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
158 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
159
160 /* PCI mail boxes */
161 #define BONITO_PCIMAIL0_OFFSET 0x40
162 #define BONITO_PCIMAIL1_OFFSET 0x44
163 #define BONITO_PCIMAIL2_OFFSET 0x48
164 #define BONITO_PCIMAIL3_OFFSET 0x4c
165 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
166 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
167 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
168 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
169
170 /* 6. PCI cache */
171 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
172 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
173 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
174 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
175
176 /* 7. other*/
177 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
178 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
179 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
180 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
181
182 #define BONITO_REGS (0x70 >> 2)
183
184 /* PCI config for south bridge. type 0 */
185 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
186 #define BONITO_PCICONF_IDSEL_OFFSET 11
187 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
188 #define BONITO_PCICONF_FUN_OFFSET 8
189 #define BONITO_PCICONF_REG_MASK_DS (~3) /* Per datasheet */
190 #define BONITO_PCICONF_REG_MASK_HW 0xff /* As seen running PMON */
191 #define BONITO_PCICONF_REG_OFFSET 0
192
193
194 /* idsel BIT = pci slot number +12 */
195 #define PCI_SLOT_BASE 12
196 #define PCI_IDSEL_VIA686B_BIT (17)
197 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
198
199 #define PCI_ADDR(busno , devno , funno , regno) \
200 ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
201
202 typedef struct BonitoState BonitoState;
203
204 struct PCIBonitoState {
205 PCIDevice dev;
206
207 BonitoState *pcihost;
208 uint32_t regs[BONITO_REGS];
209
210 struct bonldma {
211 uint32_t ldmactrl;
212 uint32_t ldmastat;
213 uint32_t ldmaaddr;
214 uint32_t ldmago;
215 } bonldma;
216
217 /* Based at 1fe00300, bonito Copier */
218 struct boncop {
219 uint32_t copctrl;
220 uint32_t copstat;
221 uint32_t coppaddr;
222 uint32_t copgo;
223 } boncop;
224
225 /* Bonito registers */
226 MemoryRegion iomem;
227 MemoryRegion iomem_ldma;
228 MemoryRegion iomem_cop;
229 MemoryRegion bonito_pciio;
230 MemoryRegion bonito_localio;
231
232 };
233 typedef struct PCIBonitoState PCIBonitoState;
234
235 struct BonitoState {
236 PCIHostState parent_obj;
237 qemu_irq *pic;
238 PCIBonitoState *pci_dev;
239 MemoryRegion pci_mem;
240 };
241
242 #define TYPE_PCI_BONITO "Bonito"
OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState,PCI_BONITO)243 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
244
245 static void bonito_writel(void *opaque, hwaddr addr,
246 uint64_t val, unsigned size)
247 {
248 PCIBonitoState *s = opaque;
249 uint32_t saddr;
250 int reset = 0;
251
252 saddr = addr >> 2;
253
254 DPRINTF("bonito_writel "HWADDR_FMT_plx" val %lx saddr %x\n",
255 addr, val, saddr);
256 switch (saddr) {
257 case BONITO_BONPONCFG:
258 case BONITO_IODEVCFG:
259 case BONITO_SDCFG:
260 case BONITO_PCIMAP:
261 case BONITO_PCIMEMBASECFG:
262 case BONITO_PCIMAP_CFG:
263 case BONITO_GPIODATA:
264 case BONITO_GPIOIE:
265 case BONITO_INTEDGE:
266 case BONITO_INTSTEER:
267 case BONITO_INTPOL:
268 case BONITO_PCIMAIL0:
269 case BONITO_PCIMAIL1:
270 case BONITO_PCIMAIL2:
271 case BONITO_PCIMAIL3:
272 case BONITO_PCICACHECTRL:
273 case BONITO_PCICACHETAG:
274 case BONITO_PCIBADADDR:
275 case BONITO_PCIMSTAT:
276 case BONITO_TIMECFG:
277 case BONITO_CPUCFG:
278 case BONITO_DQCFG:
279 case BONITO_MEMSIZE:
280 s->regs[saddr] = val;
281 break;
282 case BONITO_BONGENCFG:
283 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
284 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
285 }
286 s->regs[saddr] = val;
287 if (reset) {
288 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
289 }
290 break;
291 case BONITO_INTENSET:
292 s->regs[BONITO_INTENSET] = val;
293 s->regs[BONITO_INTEN] |= val;
294 break;
295 case BONITO_INTENCLR:
296 s->regs[BONITO_INTENCLR] = val;
297 s->regs[BONITO_INTEN] &= ~val;
298 break;
299 case BONITO_INTEN:
300 case BONITO_INTISR:
301 DPRINTF("write to readonly bonito register %x\n", saddr);
302 break;
303 default:
304 DPRINTF("write to unknown bonito register %x\n", saddr);
305 break;
306 }
307 }
308
bonito_readl(void * opaque,hwaddr addr,unsigned size)309 static uint64_t bonito_readl(void *opaque, hwaddr addr,
310 unsigned size)
311 {
312 PCIBonitoState *s = opaque;
313 uint32_t saddr;
314
315 saddr = addr >> 2;
316
317 DPRINTF("bonito_readl "HWADDR_FMT_plx"\n", addr);
318 switch (saddr) {
319 case BONITO_INTISR:
320 return s->regs[saddr];
321 default:
322 return s->regs[saddr];
323 }
324 }
325
326 static const MemoryRegionOps bonito_ops = {
327 .read = bonito_readl,
328 .write = bonito_writel,
329 .endianness = DEVICE_NATIVE_ENDIAN,
330 .valid = {
331 .min_access_size = 4,
332 .max_access_size = 4,
333 },
334 };
335
bonito_pciconf_writel(void * opaque,hwaddr addr,uint64_t val,unsigned size)336 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
337 uint64_t val, unsigned size)
338 {
339 PCIBonitoState *s = opaque;
340 PCIDevice *d = PCI_DEVICE(s);
341
342 DPRINTF("bonito_pciconf_writel "HWADDR_FMT_plx" val %lx\n", addr, val);
343 d->config_write(d, addr, val, 4);
344 }
345
bonito_pciconf_readl(void * opaque,hwaddr addr,unsigned size)346 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
347 unsigned size)
348 {
349
350 PCIBonitoState *s = opaque;
351 PCIDevice *d = PCI_DEVICE(s);
352
353 DPRINTF("bonito_pciconf_readl "HWADDR_FMT_plx"\n", addr);
354 return d->config_read(d, addr, 4);
355 }
356
357 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
358
359 static const MemoryRegionOps bonito_pciconf_ops = {
360 .read = bonito_pciconf_readl,
361 .write = bonito_pciconf_writel,
362 .endianness = DEVICE_NATIVE_ENDIAN,
363 .valid = {
364 .min_access_size = 4,
365 .max_access_size = 4,
366 },
367 };
368
bonito_ldma_readl(void * opaque,hwaddr addr,unsigned size)369 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
370 unsigned size)
371 {
372 uint32_t val;
373 PCIBonitoState *s = opaque;
374
375 if (addr >= sizeof(s->bonldma)) {
376 return 0;
377 }
378
379 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
380
381 return val;
382 }
383
bonito_ldma_writel(void * opaque,hwaddr addr,uint64_t val,unsigned size)384 static void bonito_ldma_writel(void *opaque, hwaddr addr,
385 uint64_t val, unsigned size)
386 {
387 PCIBonitoState *s = opaque;
388
389 if (addr >= sizeof(s->bonldma)) {
390 return;
391 }
392
393 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
394 }
395
396 static const MemoryRegionOps bonito_ldma_ops = {
397 .read = bonito_ldma_readl,
398 .write = bonito_ldma_writel,
399 .endianness = DEVICE_NATIVE_ENDIAN,
400 .valid = {
401 .min_access_size = 4,
402 .max_access_size = 4,
403 },
404 };
405
bonito_cop_readl(void * opaque,hwaddr addr,unsigned size)406 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
407 unsigned size)
408 {
409 uint32_t val;
410 PCIBonitoState *s = opaque;
411
412 if (addr >= sizeof(s->boncop)) {
413 return 0;
414 }
415
416 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
417
418 return val;
419 }
420
bonito_cop_writel(void * opaque,hwaddr addr,uint64_t val,unsigned size)421 static void bonito_cop_writel(void *opaque, hwaddr addr,
422 uint64_t val, unsigned size)
423 {
424 PCIBonitoState *s = opaque;
425
426 if (addr >= sizeof(s->boncop)) {
427 return;
428 }
429
430 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
431 }
432
433 static const MemoryRegionOps bonito_cop_ops = {
434 .read = bonito_cop_readl,
435 .write = bonito_cop_writel,
436 .endianness = DEVICE_NATIVE_ENDIAN,
437 .valid = {
438 .min_access_size = 4,
439 .max_access_size = 4,
440 },
441 };
442
bonito_sbridge_pciaddr(void * opaque,hwaddr addr)443 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
444 {
445 PCIBonitoState *s = opaque;
446 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
447 uint32_t cfgaddr;
448 uint32_t idsel;
449 uint32_t devno;
450 uint32_t funno;
451 uint32_t regno;
452 uint32_t pciaddr;
453
454 /* support type0 pci config */
455 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
456 return 0xffffffff;
457 }
458
459 cfgaddr = addr & 0xffff;
460 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
461
462 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
463 BONITO_PCICONF_IDSEL_OFFSET;
464 devno = ctz32(idsel);
465 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
466 regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
467
468 if (idsel == 0) {
469 error_report("error in bonito pci config address 0x" HWADDR_FMT_plx
470 ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
471 exit(1);
472 }
473 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
474 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
475 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
476
477 return pciaddr;
478 }
479
bonito_spciconf_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)480 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
481 unsigned size)
482 {
483 PCIBonitoState *s = opaque;
484 PCIDevice *d = PCI_DEVICE(s);
485 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
486 uint32_t pciaddr;
487 uint16_t status;
488
489 DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n",
490 addr, size, val);
491
492 pciaddr = bonito_sbridge_pciaddr(s, addr);
493
494 if (pciaddr == 0xffffffff) {
495 return;
496 }
497 if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
498 trace_bonito_spciconf_small_access(addr, size);
499 }
500
501 /* set the pci address in s->config_reg */
502 phb->config_reg = (pciaddr) | (1u << 31);
503 pci_data_write(phb->bus, phb->config_reg, val, size);
504
505 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
506 status = pci_get_word(d->config + PCI_STATUS);
507 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
508 pci_set_word(d->config + PCI_STATUS, status);
509 }
510
bonito_spciconf_read(void * opaque,hwaddr addr,unsigned size)511 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
512 {
513 PCIBonitoState *s = opaque;
514 PCIDevice *d = PCI_DEVICE(s);
515 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
516 uint32_t pciaddr;
517 uint16_t status;
518
519 DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size);
520
521 pciaddr = bonito_sbridge_pciaddr(s, addr);
522
523 if (pciaddr == 0xffffffff) {
524 return MAKE_64BIT_MASK(0, size * 8);
525 }
526 if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
527 trace_bonito_spciconf_small_access(addr, size);
528 }
529
530 /* set the pci address in s->config_reg */
531 phb->config_reg = (pciaddr) | (1u << 31);
532
533 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
534 status = pci_get_word(d->config + PCI_STATUS);
535 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
536 pci_set_word(d->config + PCI_STATUS, status);
537
538 return pci_data_read(phb->bus, phb->config_reg, size);
539 }
540
541 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
542 static const MemoryRegionOps bonito_spciconf_ops = {
543 .read = bonito_spciconf_read,
544 .write = bonito_spciconf_write,
545 .valid.min_access_size = 1,
546 .valid.max_access_size = 4,
547 .impl.min_access_size = 1,
548 .impl.max_access_size = 4,
549 .endianness = DEVICE_NATIVE_ENDIAN,
550 };
551
552 #define BONITO_IRQ_BASE 32
553
pci_bonito_set_irq(void * opaque,int irq_num,int level)554 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
555 {
556 BonitoState *s = opaque;
557 qemu_irq *pic = s->pic;
558 PCIBonitoState *bonito_state = s->pci_dev;
559 int internal_irq = irq_num - BONITO_IRQ_BASE;
560
561 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
562 qemu_irq_pulse(*pic);
563 } else { /* level triggered */
564 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
565 qemu_irq_raise(*pic);
566 } else {
567 qemu_irq_lower(*pic);
568 }
569 }
570 }
571
572 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
pci_bonito_map_irq(PCIDevice * pci_dev,int irq_num)573 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
574 {
575 int slot;
576
577 slot = PCI_SLOT(pci_dev->devfn);
578
579 switch (slot) {
580 case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
581 return irq_num % 4 + BONITO_IRQ_BASE;
582 case 6: /* FULOONG2E_ATI_SLOT, VGA */
583 return 4 + BONITO_IRQ_BASE;
584 case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */
585 return 5 + BONITO_IRQ_BASE;
586 case 8 ... 12: /* PCI slot 1 to 4 */
587 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
588 default: /* Unknown device, don't do any translation */
589 return irq_num;
590 }
591 }
592
bonito_reset_hold(Object * obj,ResetType type)593 static void bonito_reset_hold(Object *obj, ResetType type)
594 {
595 PCIBonitoState *s = PCI_BONITO(obj);
596 uint32_t val = 0;
597
598 /* set the default value of north bridge registers */
599
600 s->regs[BONITO_BONPONCFG] = 0xc40;
601 val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
602 val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
603 val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
604 val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
605 val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
606 s->regs[BONITO_BONGENCFG] = val;
607
608 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
609 s->regs[BONITO_SDCFG] = 0x255e0091;
610
611 s->regs[BONITO_GPIODATA] = 0x1ff;
612 s->regs[BONITO_GPIOIE] = 0x1ff;
613 s->regs[BONITO_DQCFG] = 0x8;
614 s->regs[BONITO_MEMSIZE] = 0x10000000;
615 s->regs[BONITO_PCIMAP] = 0x6140;
616 }
617
618 static const VMStateDescription vmstate_bonito = {
619 .name = "Bonito",
620 .version_id = 1,
621 .minimum_version_id = 1,
622 .fields = (const VMStateField[]) {
623 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
624 VMSTATE_END_OF_LIST()
625 }
626 };
627
bonito_host_realize(DeviceState * dev,Error ** errp)628 static void bonito_host_realize(DeviceState *dev, Error **errp)
629 {
630 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
631 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
632 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
633
634 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
635 phb->bus = pci_register_root_bus(dev, "pci",
636 pci_bonito_set_irq, pci_bonito_map_irq,
637 dev, &bs->pci_mem, get_system_io(),
638 PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
639
640 for (size_t i = 0; i < 3; i++) {
641 char *name = g_strdup_printf("pci.lomem%zu", i);
642
643 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
644 &bs->pci_mem, i * 64 * MiB, 64 * MiB);
645 memory_region_add_subregion(get_system_memory(),
646 BONITO_PCILO_BASE + i * 64 * MiB,
647 &pcimem_lo_alias[i]);
648 g_free(name);
649 }
650
651 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
652 }
653
bonito_pci_realize(PCIDevice * dev,Error ** errp)654 static void bonito_pci_realize(PCIDevice *dev, Error **errp)
655 {
656 PCIBonitoState *s = PCI_BONITO(dev);
657 MemoryRegion *host_mem = get_system_memory();
658 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
659 BonitoState *bs = s->pcihost;
660 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
661
662 /*
663 * Bonito North Bridge, built on FPGA,
664 * VENDOR_ID/DEVICE_ID are "undefined"
665 */
666 pci_config_set_prog_interface(dev->config, 0x00);
667
668 /* set the north bridge register mapping */
669 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
670 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
671 memory_region_add_subregion(host_mem, BONITO_INTERNAL_REG_BASE, &s->iomem);
672
673 /* set the north bridge pci configure mapping */
674 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
675 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
676 memory_region_add_subregion(host_mem, BONITO_PCICONFIG_BASE,
677 &phb->conf_mem);
678
679 /* set the south bridge pci configure mapping */
680 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
681 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
682 memory_region_add_subregion(host_mem, BONITO_SPCICONFIG_BASE,
683 &phb->data_mem);
684
685 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
686
687 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
688 "ldma", 0x100);
689 memory_region_add_subregion(host_mem, 0x1fe00200, &s->iomem_ldma);
690
691 /* PCI copier */
692 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
693 "cop", 0x100);
694 memory_region_add_subregion(host_mem, 0x1fe00300, &s->iomem_cop);
695
696 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
697
698 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
699 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
700 get_system_io(), 0, BONITO_PCIIO_SIZE);
701 memory_region_add_subregion(host_mem, BONITO_PCIIO_BASE,
702 &s->bonito_pciio);
703
704 /* add pci local io mapping */
705
706 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
707 get_system_io(), 0, 256 * KiB);
708 memory_region_add_subregion(host_mem, BONITO_DEV_BASE,
709 &s->bonito_localio);
710 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
711 256 * KiB);
712 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
713 256 * KiB);
714 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
715 256 * KiB);
716
717 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
718 &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
719 memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_alias);
720 create_unimplemented_device("PCI_2",
721 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
722 2 * GiB);
723
724 /* set the default value of north bridge pci config */
725 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
726 pci_set_word(dev->config + PCI_STATUS, 0x0000);
727 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
728 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
729
730 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
731 pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */
732
733 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
734 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
735 }
736
bonito_init(qemu_irq * pic)737 PCIBus *bonito_init(qemu_irq *pic)
738 {
739 DeviceState *dev;
740 BonitoState *pcihost;
741 PCIHostState *phb;
742 PCIBonitoState *s;
743 PCIDevice *d;
744
745 dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
746 phb = PCI_HOST_BRIDGE(dev);
747 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
748 pcihost->pic = pic;
749 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
750
751 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
752 s = PCI_BONITO(d);
753 s->pcihost = pcihost;
754 pcihost->pci_dev = s;
755 pci_realize_and_unref(d, phb->bus, &error_fatal);
756
757 return phb->bus;
758 }
759
bonito_pci_class_init(ObjectClass * klass,void * data)760 static void bonito_pci_class_init(ObjectClass *klass, void *data)
761 {
762 DeviceClass *dc = DEVICE_CLASS(klass);
763 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
764 ResettableClass *rc = RESETTABLE_CLASS(klass);
765
766 rc->phases.hold = bonito_reset_hold;
767 k->realize = bonito_pci_realize;
768 k->vendor_id = 0xdf53;
769 k->device_id = 0x00d5;
770 k->revision = 0x01;
771 k->class_id = PCI_CLASS_BRIDGE_HOST;
772 dc->desc = "Host bridge";
773 dc->vmsd = &vmstate_bonito;
774 /*
775 * PCI-facing part of the host bridge, not usable without the
776 * host-facing part, which can't be device_add'ed, yet.
777 */
778 dc->user_creatable = false;
779 }
780
781 static const TypeInfo bonito_pci_info = {
782 .name = TYPE_PCI_BONITO,
783 .parent = TYPE_PCI_DEVICE,
784 .instance_size = sizeof(PCIBonitoState),
785 .class_init = bonito_pci_class_init,
786 .interfaces = (InterfaceInfo[]) {
787 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
788 { },
789 },
790 };
791
bonito_host_class_init(ObjectClass * klass,void * data)792 static void bonito_host_class_init(ObjectClass *klass, void *data)
793 {
794 DeviceClass *dc = DEVICE_CLASS(klass);
795
796 dc->realize = bonito_host_realize;
797 }
798
799 static const TypeInfo bonito_host_info = {
800 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
801 .parent = TYPE_PCI_HOST_BRIDGE,
802 .instance_size = sizeof(BonitoState),
803 .class_init = bonito_host_class_init,
804 };
805
bonito_register_types(void)806 static void bonito_register_types(void)
807 {
808 type_register_static(&bonito_host_info);
809 type_register_static(&bonito_pci_info);
810 }
811
812 type_init(bonito_register_types)
813