1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 }; 68 }; 69 70 CPU1: cpu@101 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x0 0x101>; 74 enable-method = "psci"; 75 cpu-idle-states = <&PERF_CPU_SLEEP_0 76 &PERF_CPU_SLEEP_1 77 &PERF_CLUSTER_SLEEP_0 78 &PERF_CLUSTER_SLEEP_1 79 &PERF_CLUSTER_SLEEP_2>; 80 capacity-dmips-mhz = <1126>; 81 #cooling-cells = <2>; 82 next-level-cache = <&L2_1>; 83 }; 84 85 CPU2: cpu@102 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x0 0x102>; 89 enable-method = "psci"; 90 cpu-idle-states = <&PERF_CPU_SLEEP_0 91 &PERF_CPU_SLEEP_1 92 &PERF_CLUSTER_SLEEP_0 93 &PERF_CLUSTER_SLEEP_1 94 &PERF_CLUSTER_SLEEP_2>; 95 capacity-dmips-mhz = <1126>; 96 #cooling-cells = <2>; 97 next-level-cache = <&L2_1>; 98 }; 99 100 CPU3: cpu@103 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x0 0x103>; 104 enable-method = "psci"; 105 cpu-idle-states = <&PERF_CPU_SLEEP_0 106 &PERF_CPU_SLEEP_1 107 &PERF_CLUSTER_SLEEP_0 108 &PERF_CLUSTER_SLEEP_1 109 &PERF_CLUSTER_SLEEP_2>; 110 capacity-dmips-mhz = <1126>; 111 #cooling-cells = <2>; 112 next-level-cache = <&L2_1>; 113 }; 114 115 CPU4: cpu@0 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x0 0x0>; 119 enable-method = "psci"; 120 cpu-idle-states = <&PWR_CPU_SLEEP_0 121 &PWR_CPU_SLEEP_1 122 &PWR_CLUSTER_SLEEP_0 123 &PWR_CLUSTER_SLEEP_1 124 &PWR_CLUSTER_SLEEP_2>; 125 capacity-dmips-mhz = <1024>; 126 #cooling-cells = <2>; 127 next-level-cache = <&L2_0>; 128 L2_0: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 CPU5: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x0 0x1>; 139 enable-method = "psci"; 140 cpu-idle-states = <&PWR_CPU_SLEEP_0 141 &PWR_CPU_SLEEP_1 142 &PWR_CLUSTER_SLEEP_0 143 &PWR_CLUSTER_SLEEP_1 144 &PWR_CLUSTER_SLEEP_2>; 145 capacity-dmips-mhz = <1024>; 146 #cooling-cells = <2>; 147 next-level-cache = <&L2_0>; 148 }; 149 150 CPU6: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x0 0x2>; 154 enable-method = "psci"; 155 cpu-idle-states = <&PWR_CPU_SLEEP_0 156 &PWR_CPU_SLEEP_1 157 &PWR_CLUSTER_SLEEP_0 158 &PWR_CLUSTER_SLEEP_1 159 &PWR_CLUSTER_SLEEP_2>; 160 capacity-dmips-mhz = <1024>; 161 #cooling-cells = <2>; 162 next-level-cache = <&L2_0>; 163 }; 164 165 CPU7: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x0 0x3>; 169 enable-method = "psci"; 170 cpu-idle-states = <&PWR_CPU_SLEEP_0 171 &PWR_CPU_SLEEP_1 172 &PWR_CLUSTER_SLEEP_0 173 &PWR_CLUSTER_SLEEP_1 174 &PWR_CLUSTER_SLEEP_2>; 175 capacity-dmips-mhz = <1024>; 176 #cooling-cells = <2>; 177 next-level-cache = <&L2_0>; 178 }; 179 180 cpu-map { 181 cluster0 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 199 cluster1 { 200 core0 { 201 cpu = <&CPU0>; 202 }; 203 204 core1 { 205 cpu = <&CPU1>; 206 }; 207 208 core2 { 209 cpu = <&CPU2>; 210 }; 211 212 core3 { 213 cpu = <&CPU3>; 214 }; 215 }; 216 }; 217 218 idle-states { 219 entry-method = "psci"; 220 221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 222 compatible = "arm,idle-state"; 223 idle-state-name = "pwr-retention"; 224 arm,psci-suspend-param = <0x40000002>; 225 entry-latency-us = <338>; 226 exit-latency-us = <423>; 227 min-residency-us = <200>; 228 }; 229 230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "pwr-power-collapse"; 233 arm,psci-suspend-param = <0x40000003>; 234 entry-latency-us = <515>; 235 exit-latency-us = <1821>; 236 min-residency-us = <1000>; 237 local-timer-stop; 238 }; 239 240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "perf-retention"; 243 arm,psci-suspend-param = <0x40000002>; 244 entry-latency-us = <154>; 245 exit-latency-us = <87>; 246 min-residency-us = <200>; 247 }; 248 249 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "perf-power-collapse"; 252 arm,psci-suspend-param = <0x40000003>; 253 entry-latency-us = <262>; 254 exit-latency-us = <301>; 255 min-residency-us = <1000>; 256 local-timer-stop; 257 }; 258 259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "pwr-cluster-dynamic-retention"; 262 arm,psci-suspend-param = <0x400000F2>; 263 entry-latency-us = <284>; 264 exit-latency-us = <384>; 265 min-residency-us = <9987>; 266 local-timer-stop; 267 }; 268 269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "pwr-cluster-retention"; 272 arm,psci-suspend-param = <0x400000F3>; 273 entry-latency-us = <338>; 274 exit-latency-us = <423>; 275 min-residency-us = <9987>; 276 local-timer-stop; 277 }; 278 279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "pwr-cluster-retention"; 282 arm,psci-suspend-param = <0x400000F4>; 283 entry-latency-us = <515>; 284 exit-latency-us = <1821>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 idle-state-name = "perf-cluster-dynamic-retention"; 292 arm,psci-suspend-param = <0x400000F2>; 293 entry-latency-us = <272>; 294 exit-latency-us = <329>; 295 min-residency-us = <9987>; 296 local-timer-stop; 297 }; 298 299 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 300 compatible = "arm,idle-state"; 301 idle-state-name = "perf-cluster-retention"; 302 arm,psci-suspend-param = <0x400000F3>; 303 entry-latency-us = <332>; 304 exit-latency-us = <368>; 305 min-residency-us = <9987>; 306 local-timer-stop; 307 }; 308 309 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "perf-cluster-retention"; 312 arm,psci-suspend-param = <0x400000F4>; 313 entry-latency-us = <545>; 314 exit-latency-us = <1609>; 315 min-residency-us = <9987>; 316 local-timer-stop; 317 }; 318 }; 319 }; 320 321 firmware { 322 scm { 323 compatible = "qcom,scm-msm8998", "qcom,scm"; 324 }; 325 }; 326 327 memory@80000000 { 328 device_type = "memory"; 329 /* We expect the bootloader to fill in the reg */ 330 reg = <0x0 0x80000000 0x0 0x0>; 331 }; 332 333 dsi_opp_table: opp-table-dsi { 334 compatible = "operating-points-v2"; 335 336 opp-131250000 { 337 opp-hz = /bits/ 64 <131250000>; 338 required-opps = <&rpmpd_opp_svs>; 339 }; 340 341 opp-210000000 { 342 opp-hz = /bits/ 64 <210000000>; 343 required-opps = <&rpmpd_opp_svs_plus>; 344 }; 345 346 opp-262500000 { 347 opp-hz = /bits/ 64 <262500000>; 348 required-opps = <&rpmpd_opp_nom>; 349 }; 350 }; 351 352 pmu { 353 compatible = "arm,armv8-pmuv3"; 354 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 355 }; 356 357 psci { 358 compatible = "arm,psci-1.0"; 359 method = "smc"; 360 }; 361 362 rpm: remoteproc { 363 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; 364 365 glink-edge { 366 compatible = "qcom,glink-rpm"; 367 368 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 369 qcom,rpm-msg-ram = <&rpm_msg_ram>; 370 mboxes = <&apcs_glb 0>; 371 372 rpm_requests: rpm-requests { 373 compatible = "qcom,rpm-sdm660"; 374 qcom,glink-channels = "rpm_requests"; 375 376 rpmcc: clock-controller { 377 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 378 #clock-cells = <1>; 379 }; 380 381 rpmpd: power-controller { 382 compatible = "qcom,sdm660-rpmpd"; 383 #power-domain-cells = <1>; 384 operating-points-v2 = <&rpmpd_opp_table>; 385 386 rpmpd_opp_table: opp-table { 387 compatible = "operating-points-v2"; 388 389 rpmpd_opp_ret: opp1 { 390 opp-level = <RPM_SMD_LEVEL_RETENTION>; 391 }; 392 393 rpmpd_opp_ret_plus: opp2 { 394 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 395 }; 396 397 rpmpd_opp_min_svs: opp3 { 398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 399 }; 400 401 rpmpd_opp_low_svs: opp4 { 402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 403 }; 404 405 rpmpd_opp_svs: opp5 { 406 opp-level = <RPM_SMD_LEVEL_SVS>; 407 }; 408 409 rpmpd_opp_svs_plus: opp6 { 410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 411 }; 412 413 rpmpd_opp_nom: opp7 { 414 opp-level = <RPM_SMD_LEVEL_NOM>; 415 }; 416 417 rpmpd_opp_nom_plus: opp8 { 418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 419 }; 420 421 rpmpd_opp_turbo: opp9 { 422 opp-level = <RPM_SMD_LEVEL_TURBO>; 423 }; 424 }; 425 }; 426 }; 427 }; 428 }; 429 430 reserved-memory { 431 #address-cells = <2>; 432 #size-cells = <2>; 433 ranges; 434 435 wlan_msa_guard: wlan-msa-guard@85600000 { 436 reg = <0x0 0x85600000 0x0 0x100000>; 437 no-map; 438 }; 439 440 wlan_msa_mem: wlan-msa-mem@85700000 { 441 reg = <0x0 0x85700000 0x0 0x100000>; 442 no-map; 443 }; 444 445 qhee_code: qhee-code@85800000 { 446 reg = <0x0 0x85800000 0x0 0x600000>; 447 no-map; 448 }; 449 450 rmtfs_mem: memory@85e00000 { 451 compatible = "qcom,rmtfs-mem"; 452 reg = <0x0 0x85e00000 0x0 0x200000>; 453 no-map; 454 455 qcom,client-id = <1>; 456 qcom,vmid = <15>; 457 }; 458 459 smem_region: smem-mem@86000000 { 460 reg = <0 0x86000000 0 0x200000>; 461 no-map; 462 }; 463 464 tz_mem: memory@86200000 { 465 reg = <0x0 0x86200000 0x0 0x3300000>; 466 no-map; 467 }; 468 469 mpss_region: mpss@8ac00000 { 470 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 471 no-map; 472 }; 473 474 adsp_region: adsp@92a00000 { 475 reg = <0x0 0x92a00000 0x0 0x1e00000>; 476 no-map; 477 }; 478 479 mba_region: mba@94800000 { 480 reg = <0x0 0x94800000 0x0 0x200000>; 481 no-map; 482 }; 483 484 buffer_mem: tzbuffer@94a00000 { 485 reg = <0x0 0x94a00000 0x0 0x100000>; 486 no-map; 487 }; 488 489 venus_region: venus@9f800000 { 490 reg = <0x0 0x9f800000 0x0 0x800000>; 491 no-map; 492 }; 493 494 adsp_mem: adsp-region@f6000000 { 495 reg = <0x0 0xf6000000 0x0 0x800000>; 496 no-map; 497 }; 498 499 qseecom_mem: qseecom-region@f6800000 { 500 reg = <0x0 0xf6800000 0x0 0x1400000>; 501 no-map; 502 }; 503 504 zap_shader_region: gpu@fed00000 { 505 compatible = "shared-dma-pool"; 506 reg = <0x0 0xfed00000 0x0 0xa00000>; 507 no-map; 508 }; 509 }; 510 511 smem: smem { 512 compatible = "qcom,smem"; 513 memory-region = <&smem_region>; 514 hwlocks = <&tcsr_mutex 3>; 515 }; 516 517 smp2p-adsp { 518 compatible = "qcom,smp2p"; 519 qcom,smem = <443>, <429>; 520 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 521 mboxes = <&apcs_glb 10>; 522 qcom,local-pid = <0>; 523 qcom,remote-pid = <2>; 524 525 adsp_smp2p_out: master-kernel { 526 qcom,entry-name = "master-kernel"; 527 #qcom,smem-state-cells = <1>; 528 }; 529 530 adsp_smp2p_in: slave-kernel { 531 qcom,entry-name = "slave-kernel"; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 }; 536 537 smp2p-mpss { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <435>, <428>; 540 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 541 mboxes = <&apcs_glb 14>; 542 qcom,local-pid = <0>; 543 qcom,remote-pid = <1>; 544 545 modem_smp2p_out: master-kernel { 546 qcom,entry-name = "master-kernel"; 547 #qcom,smem-state-cells = <1>; 548 }; 549 550 modem_smp2p_in: slave-kernel { 551 qcom,entry-name = "slave-kernel"; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 soc@0 { 558 #address-cells = <1>; 559 #size-cells = <1>; 560 ranges = <0 0 0 0xffffffff>; 561 compatible = "simple-bus"; 562 563 gcc: clock-controller@100000 { 564 compatible = "qcom,gcc-sdm630"; 565 #clock-cells = <1>; 566 #reset-cells = <1>; 567 #power-domain-cells = <1>; 568 reg = <0x00100000 0x94000>; 569 570 clock-names = "xo", "sleep_clk"; 571 clocks = <&xo_board>, 572 <&sleep_clk>; 573 }; 574 575 rpm_msg_ram: sram@778000 { 576 compatible = "qcom,rpm-msg-ram"; 577 reg = <0x00778000 0x7000>; 578 }; 579 580 qfprom: qfprom@780000 { 581 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 582 reg = <0x00780000 0x621c>; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 586 qusb2_hstx_trim: hstx-trim@240 { 587 reg = <0x243 0x1>; 588 bits = <1 3>; 589 }; 590 591 gpu_speed_bin: gpu-speed-bin@41a0 { 592 reg = <0x41a2 0x1>; 593 bits = <5 7>; 594 }; 595 }; 596 597 rng: rng@793000 { 598 compatible = "qcom,prng-ee"; 599 reg = <0x00793000 0x1000>; 600 clocks = <&gcc GCC_PRNG_AHB_CLK>; 601 clock-names = "core"; 602 }; 603 604 bimc: interconnect@1008000 { 605 compatible = "qcom,sdm660-bimc"; 606 reg = <0x01008000 0x78000>; 607 #interconnect-cells = <1>; 608 clock-names = "bus", "bus_a"; 609 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 610 <&rpmcc RPM_SMD_BIMC_A_CLK>; 611 }; 612 613 restart@10ac000 { 614 compatible = "qcom,pshold"; 615 reg = <0x010ac000 0x4>; 616 }; 617 618 cnoc: interconnect@1500000 { 619 compatible = "qcom,sdm660-cnoc"; 620 reg = <0x01500000 0x10000>; 621 #interconnect-cells = <1>; 622 clock-names = "bus", "bus_a"; 623 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 624 <&rpmcc RPM_SMD_CNOC_A_CLK>; 625 }; 626 627 snoc: interconnect@1626000 { 628 compatible = "qcom,sdm660-snoc"; 629 reg = <0x01626000 0x7090>; 630 #interconnect-cells = <1>; 631 clock-names = "bus", "bus_a"; 632 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 633 <&rpmcc RPM_SMD_SNOC_A_CLK>; 634 }; 635 636 anoc2_smmu: iommu@16c0000 { 637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 638 reg = <0x016c0000 0x40000>; 639 640 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 641 assigned-clock-rates = <1000>; 642 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 643 clock-names = "bus"; 644 #global-interrupts = <2>; 645 #iommu-cells = <1>; 646 647 interrupts = 648 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 650 651 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 653 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 654 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 655 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 656 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 657 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 680 681 status = "disabled"; 682 }; 683 684 a2noc: interconnect@1704000 { 685 compatible = "qcom,sdm660-a2noc"; 686 reg = <0x01704000 0xc100>; 687 #interconnect-cells = <1>; 688 clock-names = "bus", 689 "bus_a", 690 "ipa", 691 "ufs_axi", 692 "aggre2_ufs_axi", 693 "aggre2_usb3_axi", 694 "cfg_noc_usb2_axi"; 695 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 696 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 697 <&rpmcc RPM_SMD_IPA_CLK>, 698 <&gcc GCC_UFS_AXI_CLK>, 699 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 700 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 701 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 702 }; 703 704 mnoc: interconnect@1745000 { 705 compatible = "qcom,sdm660-mnoc"; 706 reg = <0x01745000 0xa010>; 707 #interconnect-cells = <1>; 708 clock-names = "bus", "bus_a", "iface"; 709 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 710 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 711 <&mmcc AHB_CLK_SRC>; 712 }; 713 714 tsens: thermal-sensor@10ae000 { 715 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 716 reg = <0x010ae000 0x1000>, /* TM */ 717 <0x010ad000 0x1000>; /* SROT */ 718 #qcom,sensors = <12>; 719 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 721 interrupt-names = "uplow", "critical"; 722 #thermal-sensor-cells = <1>; 723 }; 724 725 tcsr_mutex: hwlock@1f40000 { 726 compatible = "qcom,tcsr-mutex"; 727 reg = <0x01f40000 0x20000>; 728 #hwlock-cells = <1>; 729 }; 730 731 tcsr_regs_1: syscon@1f60000 { 732 compatible = "qcom,sdm630-tcsr", "syscon"; 733 reg = <0x01f60000 0x20000>; 734 }; 735 736 tlmm: pinctrl@3100000 { 737 compatible = "qcom,sdm630-pinctrl"; 738 reg = <0x03100000 0x400000>, 739 <0x03500000 0x400000>, 740 <0x03900000 0x400000>; 741 reg-names = "south", "center", "north"; 742 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 743 gpio-controller; 744 gpio-ranges = <&tlmm 0 0 114>; 745 #gpio-cells = <2>; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 749 blsp1_uart1_default: blsp1-uart1-default-state { 750 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 751 function = "blsp_uart1"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 757 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 758 function = "gpio"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 blsp1_uart2_default: blsp1-uart2-default-state { 764 pins = "gpio4", "gpio5"; 765 function = "blsp_uart2"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 blsp2_uart1_default: blsp2-uart1-active-state { 771 tx-rts-pins { 772 pins = "gpio16", "gpio19"; 773 function = "blsp_uart5"; 774 drive-strength = <2>; 775 bias-disable; 776 }; 777 778 rx-pins { 779 /* 780 * Avoid garbage data while BT module 781 * is powered off or not driving signal 782 */ 783 pins = "gpio17"; 784 function = "blsp_uart5"; 785 drive-strength = <2>; 786 bias-pull-up; 787 }; 788 789 cts-pins { 790 /* Match the pull of the BT module */ 791 pins = "gpio18"; 792 function = "blsp_uart5"; 793 drive-strength = <2>; 794 bias-pull-down; 795 }; 796 }; 797 798 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 799 tx-pins { 800 pins = "gpio16"; 801 function = "gpio"; 802 drive-strength = <2>; 803 bias-pull-up; 804 }; 805 806 rx-cts-rts-pins { 807 pins = "gpio17", "gpio18", "gpio19"; 808 function = "gpio"; 809 drive-strength = <2>; 810 bias-disable; 811 }; 812 }; 813 814 i2c1_default: i2c1-default-state { 815 pins = "gpio2", "gpio3"; 816 function = "blsp_i2c1"; 817 drive-strength = <2>; 818 bias-disable; 819 }; 820 821 i2c1_sleep: i2c1-sleep-state { 822 pins = "gpio2", "gpio3"; 823 function = "blsp_i2c1"; 824 drive-strength = <2>; 825 bias-pull-up; 826 }; 827 828 i2c2_default: i2c2-default-state { 829 pins = "gpio6", "gpio7"; 830 function = "blsp_i2c2"; 831 drive-strength = <2>; 832 bias-disable; 833 }; 834 835 i2c2_sleep: i2c2-sleep-state { 836 pins = "gpio6", "gpio7"; 837 function = "blsp_i2c2"; 838 drive-strength = <2>; 839 bias-pull-up; 840 }; 841 842 i2c3_default: i2c3-default-state { 843 pins = "gpio10", "gpio11"; 844 function = "blsp_i2c3"; 845 drive-strength = <2>; 846 bias-disable; 847 }; 848 849 i2c3_sleep: i2c3-sleep-state { 850 pins = "gpio10", "gpio11"; 851 function = "blsp_i2c3"; 852 drive-strength = <2>; 853 bias-pull-up; 854 }; 855 856 i2c4_default: i2c4-default-state { 857 pins = "gpio14", "gpio15"; 858 function = "blsp_i2c4"; 859 drive-strength = <2>; 860 bias-disable; 861 }; 862 863 i2c4_sleep: i2c4-sleep-state { 864 pins = "gpio14", "gpio15"; 865 function = "blsp_i2c4"; 866 drive-strength = <2>; 867 bias-pull-up; 868 }; 869 870 i2c5_default: i2c5-default-state { 871 pins = "gpio18", "gpio19"; 872 function = "blsp_i2c5"; 873 drive-strength = <2>; 874 bias-disable; 875 }; 876 877 i2c5_sleep: i2c5-sleep-state { 878 pins = "gpio18", "gpio19"; 879 function = "blsp_i2c5"; 880 drive-strength = <2>; 881 bias-pull-up; 882 }; 883 884 i2c6_default: i2c6-default-state { 885 pins = "gpio22", "gpio23"; 886 function = "blsp_i2c6"; 887 drive-strength = <2>; 888 bias-disable; 889 }; 890 891 i2c6_sleep: i2c6-sleep-state { 892 pins = "gpio22", "gpio23"; 893 function = "blsp_i2c6"; 894 drive-strength = <2>; 895 bias-pull-up; 896 }; 897 898 i2c7_default: i2c7-default-state { 899 pins = "gpio26", "gpio27"; 900 function = "blsp_i2c7"; 901 drive-strength = <2>; 902 bias-disable; 903 }; 904 905 i2c7_sleep: i2c7-sleep-state { 906 pins = "gpio26", "gpio27"; 907 function = "blsp_i2c7"; 908 drive-strength = <2>; 909 bias-pull-up; 910 }; 911 912 i2c8_default: i2c8-default-state { 913 pins = "gpio30", "gpio31"; 914 function = "blsp_i2c8_a"; 915 drive-strength = <2>; 916 bias-disable; 917 }; 918 919 i2c8_sleep: i2c8-sleep-state { 920 pins = "gpio30", "gpio31"; 921 function = "blsp_i2c8_a"; 922 drive-strength = <2>; 923 bias-pull-up; 924 }; 925 926 cci0_default: cci0-default-state { 927 pins = "gpio36","gpio37"; 928 function = "cci_i2c"; 929 bias-pull-up; 930 drive-strength = <2>; 931 }; 932 933 cci1_default: cci1-default-state { 934 pins = "gpio38","gpio39"; 935 function = "cci_i2c"; 936 bias-pull-up; 937 drive-strength = <2>; 938 }; 939 940 sdc1_state_on: sdc1-on-state { 941 clk-pins { 942 pins = "sdc1_clk"; 943 bias-disable; 944 drive-strength = <16>; 945 }; 946 947 cmd-pins { 948 pins = "sdc1_cmd"; 949 bias-pull-up; 950 drive-strength = <10>; 951 }; 952 953 data-pins { 954 pins = "sdc1_data"; 955 bias-pull-up; 956 drive-strength = <10>; 957 }; 958 959 rclk-pins { 960 pins = "sdc1_rclk"; 961 bias-pull-down; 962 }; 963 }; 964 965 sdc1_state_off: sdc1-off-state { 966 clk-pins { 967 pins = "sdc1_clk"; 968 bias-disable; 969 drive-strength = <2>; 970 }; 971 972 cmd-pins { 973 pins = "sdc1_cmd"; 974 bias-pull-up; 975 drive-strength = <2>; 976 }; 977 978 data-pins { 979 pins = "sdc1_data"; 980 bias-pull-up; 981 drive-strength = <2>; 982 }; 983 984 rclk-pins { 985 pins = "sdc1_rclk"; 986 bias-pull-down; 987 }; 988 }; 989 990 sdc2_state_on: sdc2-on-state { 991 clk-pins { 992 pins = "sdc2_clk"; 993 bias-disable; 994 drive-strength = <16>; 995 }; 996 997 cmd-pins { 998 pins = "sdc2_cmd"; 999 bias-pull-up; 1000 drive-strength = <10>; 1001 }; 1002 1003 data-pins { 1004 pins = "sdc2_data"; 1005 bias-pull-up; 1006 drive-strength = <10>; 1007 }; 1008 }; 1009 1010 sdc2_state_off: sdc2-off-state { 1011 clk-pins { 1012 pins = "sdc2_clk"; 1013 bias-disable; 1014 drive-strength = <2>; 1015 }; 1016 1017 cmd-pins { 1018 pins = "sdc2_cmd"; 1019 bias-pull-up; 1020 drive-strength = <2>; 1021 }; 1022 1023 data-pins { 1024 pins = "sdc2_data"; 1025 bias-pull-up; 1026 drive-strength = <2>; 1027 }; 1028 }; 1029 }; 1030 1031 adreno_gpu: gpu@5000000 { 1032 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1033 1034 reg = <0x05000000 0x40000>; 1035 reg-names = "kgsl_3d0_reg_memory"; 1036 1037 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1038 1039 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1040 <&gpucc GPUCC_RBBMTIMER_CLK>, 1041 <&gcc GCC_BIMC_GFX_CLK>, 1042 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1043 <&gpucc GPUCC_RBCPR_CLK>, 1044 <&gpucc GPUCC_GFX3D_CLK>; 1045 1046 clock-names = "iface", 1047 "rbbmtimer", 1048 "mem", 1049 "mem_iface", 1050 "rbcpr", 1051 "core"; 1052 1053 power-domains = <&rpmpd SDM660_VDDMX>; 1054 iommus = <&kgsl_smmu 0>; 1055 1056 nvmem-cells = <&gpu_speed_bin>; 1057 nvmem-cell-names = "speed_bin"; 1058 1059 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1060 interconnect-names = "gfx-mem"; 1061 1062 operating-points-v2 = <&gpu_sdm630_opp_table>; 1063 1064 status = "disabled"; 1065 1066 gpu_sdm630_opp_table: opp-table { 1067 compatible = "operating-points-v2"; 1068 opp-775000000 { 1069 opp-hz = /bits/ 64 <775000000>; 1070 opp-level = <RPM_SMD_LEVEL_TURBO>; 1071 opp-peak-kBps = <5412000>; 1072 opp-supported-hw = <0xa2>; 1073 }; 1074 opp-647000000 { 1075 opp-hz = /bits/ 64 <647000000>; 1076 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1077 opp-peak-kBps = <4068000>; 1078 opp-supported-hw = <0xff>; 1079 }; 1080 opp-588000000 { 1081 opp-hz = /bits/ 64 <588000000>; 1082 opp-level = <RPM_SMD_LEVEL_NOM>; 1083 opp-peak-kBps = <3072000>; 1084 opp-supported-hw = <0xff>; 1085 }; 1086 opp-465000000 { 1087 opp-hz = /bits/ 64 <465000000>; 1088 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1089 opp-peak-kBps = <2724000>; 1090 opp-supported-hw = <0xff>; 1091 }; 1092 opp-370000000 { 1093 opp-hz = /bits/ 64 <370000000>; 1094 opp-level = <RPM_SMD_LEVEL_SVS>; 1095 opp-peak-kBps = <2188000>; 1096 opp-supported-hw = <0xff>; 1097 }; 1098 opp-240000000 { 1099 opp-hz = /bits/ 64 <240000000>; 1100 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1101 opp-peak-kBps = <1648000>; 1102 opp-supported-hw = <0xff>; 1103 }; 1104 opp-160000000 { 1105 opp-hz = /bits/ 64 <160000000>; 1106 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1107 opp-peak-kBps = <1200000>; 1108 opp-supported-hw = <0xff>; 1109 }; 1110 }; 1111 }; 1112 1113 kgsl_smmu: iommu@5040000 { 1114 compatible = "qcom,sdm630-smmu-v2", 1115 "qcom,adreno-smmu", "qcom,smmu-v2"; 1116 reg = <0x05040000 0x10000>; 1117 1118 /* 1119 * GX GDSC parent is CX. We need to bring up CX for SMMU 1120 * but we need both up for Adreno. On the other hand, we 1121 * need to manage the GX rpmpd domain in the adreno driver. 1122 * Enable CX/GX GDSCs here so that we can manage just the GX 1123 * RPM Power Domain in the Adreno driver. 1124 */ 1125 power-domains = <&gpucc GPU_GX_GDSC>; 1126 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1127 <&gcc GCC_BIMC_GFX_CLK>, 1128 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1129 clock-names = "iface", "mem", "mem_iface"; 1130 #global-interrupts = <2>; 1131 #iommu-cells = <1>; 1132 1133 interrupts = 1134 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1136 1137 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1145 1146 status = "disabled"; 1147 }; 1148 1149 gpucc: clock-controller@5065000 { 1150 compatible = "qcom,gpucc-sdm630"; 1151 #clock-cells = <1>; 1152 #reset-cells = <1>; 1153 #power-domain-cells = <1>; 1154 reg = <0x05065000 0x9038>; 1155 1156 clocks = <&xo_board>, 1157 <&gcc GCC_GPU_GPLL0_CLK>, 1158 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1159 clock-names = "xo", 1160 "gcc_gpu_gpll0_clk", 1161 "gcc_gpu_gpll0_div_clk"; 1162 status = "disabled"; 1163 }; 1164 1165 lpass_smmu: iommu@5100000 { 1166 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1167 reg = <0x05100000 0x40000>; 1168 #iommu-cells = <1>; 1169 1170 #global-interrupts = <2>; 1171 interrupts = 1172 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1174 1175 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1192 1193 status = "disabled"; 1194 }; 1195 1196 sram@290000 { 1197 compatible = "qcom,rpm-stats"; 1198 reg = <0x00290000 0x10000>; 1199 }; 1200 1201 spmi_bus: spmi@800f000 { 1202 compatible = "qcom,spmi-pmic-arb"; 1203 reg = <0x0800f000 0x1000>, 1204 <0x08400000 0x1000000>, 1205 <0x09400000 0x1000000>, 1206 <0x0a400000 0x220000>, 1207 <0x0800a000 0x3000>; 1208 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1209 interrupt-names = "periph_irq"; 1210 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1211 qcom,ee = <0>; 1212 qcom,channel = <0>; 1213 #address-cells = <2>; 1214 #size-cells = <0>; 1215 interrupt-controller; 1216 #interrupt-cells = <4>; 1217 }; 1218 1219 usb3: usb@a8f8800 { 1220 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1221 reg = <0x0a8f8800 0x400>; 1222 status = "disabled"; 1223 #address-cells = <1>; 1224 #size-cells = <1>; 1225 ranges; 1226 1227 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1228 <&gcc GCC_USB30_MASTER_CLK>, 1229 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1230 <&gcc GCC_USB30_SLEEP_CLK>, 1231 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1232 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1233 clock-names = "cfg_noc", 1234 "core", 1235 "iface", 1236 "sleep", 1237 "mock_utmi", 1238 "bus"; 1239 1240 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1241 <&gcc GCC_USB30_MASTER_CLK>, 1242 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1243 assigned-clock-rates = <19200000>, <120000000>, 1244 <19200000>; 1245 1246 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1248 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1249 1250 power-domains = <&gcc USB_30_GDSC>; 1251 qcom,select-utmi-as-pipe-clk; 1252 1253 resets = <&gcc GCC_USB_30_BCR>; 1254 1255 usb3_dwc3: usb@a800000 { 1256 compatible = "snps,dwc3"; 1257 reg = <0x0a800000 0xc8d0>; 1258 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1259 snps,dis_u2_susphy_quirk; 1260 snps,dis_enblslpm_quirk; 1261 snps,parkmode-disable-ss-quirk; 1262 1263 /* 1264 * SDM630 technically supports USB3 but I 1265 * haven't seen any devices making use of it. 1266 */ 1267 maximum-speed = "high-speed"; 1268 phys = <&qusb2phy0>; 1269 phy-names = "usb2-phy"; 1270 snps,hird-threshold = /bits/ 8 <0>; 1271 }; 1272 }; 1273 1274 qusb2phy0: phy@c012000 { 1275 compatible = "qcom,sdm660-qusb2-phy"; 1276 reg = <0x0c012000 0x180>; 1277 #phy-cells = <0>; 1278 1279 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1280 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1281 clock-names = "cfg_ahb", "ref"; 1282 1283 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1284 nvmem-cells = <&qusb2_hstx_trim>; 1285 status = "disabled"; 1286 }; 1287 1288 qusb2phy1: phy@c014000 { 1289 compatible = "qcom,sdm660-qusb2-phy"; 1290 reg = <0x0c014000 0x180>; 1291 #phy-cells = <0>; 1292 1293 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1294 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1295 clock-names = "cfg_ahb", "ref"; 1296 1297 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1298 nvmem-cells = <&qusb2_hstx_trim>; 1299 status = "disabled"; 1300 }; 1301 1302 sdhc_2: mmc@c084000 { 1303 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1304 reg = <0x0c084000 0x1000>; 1305 reg-names = "hc"; 1306 1307 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1309 interrupt-names = "hc_irq", "pwr_irq"; 1310 1311 bus-width = <4>; 1312 1313 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1314 <&gcc GCC_SDCC2_APPS_CLK>, 1315 <&xo_board>; 1316 clock-names = "iface", "core", "xo"; 1317 1318 1319 interconnects = <&a2noc 3 &a2noc 10>, 1320 <&gnoc 0 &cnoc 28>; 1321 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1322 operating-points-v2 = <&sdhc2_opp_table>; 1323 1324 pinctrl-names = "default", "sleep"; 1325 pinctrl-0 = <&sdc2_state_on>; 1326 pinctrl-1 = <&sdc2_state_off>; 1327 power-domains = <&rpmpd SDM660_VDDCX>; 1328 1329 status = "disabled"; 1330 1331 sdhc2_opp_table: opp-table { 1332 compatible = "operating-points-v2"; 1333 1334 opp-50000000 { 1335 opp-hz = /bits/ 64 <50000000>; 1336 required-opps = <&rpmpd_opp_low_svs>; 1337 opp-peak-kBps = <200000 140000>; 1338 opp-avg-kBps = <130718 133320>; 1339 }; 1340 opp-100000000 { 1341 opp-hz = /bits/ 64 <100000000>; 1342 required-opps = <&rpmpd_opp_svs>; 1343 opp-peak-kBps = <250000 160000>; 1344 opp-avg-kBps = <196078 150000>; 1345 }; 1346 opp-200000000 { 1347 opp-hz = /bits/ 64 <200000000>; 1348 required-opps = <&rpmpd_opp_nom>; 1349 opp-peak-kBps = <4096000 4096000>; 1350 opp-avg-kBps = <1338562 1338562>; 1351 }; 1352 }; 1353 }; 1354 1355 sdhc_1: mmc@c0c4000 { 1356 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1357 reg = <0x0c0c4000 0x1000>, 1358 <0x0c0c5000 0x1000>, 1359 <0x0c0c8000 0x8000>; 1360 reg-names = "hc", "cqhci", "ice"; 1361 1362 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "hc_irq", "pwr_irq"; 1365 1366 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1367 <&gcc GCC_SDCC1_APPS_CLK>, 1368 <&xo_board>, 1369 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1370 clock-names = "iface", "core", "xo", "ice"; 1371 1372 interconnects = <&a2noc 2 &a2noc 10>, 1373 <&gnoc 0 &cnoc 27>; 1374 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1375 operating-points-v2 = <&sdhc1_opp_table>; 1376 pinctrl-names = "default", "sleep"; 1377 pinctrl-0 = <&sdc1_state_on>; 1378 pinctrl-1 = <&sdc1_state_off>; 1379 power-domains = <&rpmpd SDM660_VDDCX>; 1380 1381 bus-width = <8>; 1382 non-removable; 1383 1384 status = "disabled"; 1385 1386 sdhc1_opp_table: opp-table { 1387 compatible = "operating-points-v2"; 1388 1389 opp-50000000 { 1390 opp-hz = /bits/ 64 <50000000>; 1391 required-opps = <&rpmpd_opp_low_svs>; 1392 opp-peak-kBps = <200000 140000>; 1393 opp-avg-kBps = <130718 133320>; 1394 }; 1395 opp-100000000 { 1396 opp-hz = /bits/ 64 <100000000>; 1397 required-opps = <&rpmpd_opp_svs>; 1398 opp-peak-kBps = <250000 160000>; 1399 opp-avg-kBps = <196078 150000>; 1400 }; 1401 opp-384000000 { 1402 opp-hz = /bits/ 64 <384000000>; 1403 required-opps = <&rpmpd_opp_nom>; 1404 opp-peak-kBps = <4096000 4096000>; 1405 opp-avg-kBps = <1338562 1338562>; 1406 }; 1407 }; 1408 }; 1409 1410 usb2: usb@c2f8800 { 1411 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1412 reg = <0x0c2f8800 0x400>; 1413 status = "disabled"; 1414 #address-cells = <1>; 1415 #size-cells = <1>; 1416 ranges; 1417 1418 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1419 <&gcc GCC_USB20_MASTER_CLK>, 1420 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1421 <&gcc GCC_USB20_SLEEP_CLK>; 1422 clock-names = "cfg_noc", "core", 1423 "mock_utmi", "sleep"; 1424 1425 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1426 <&gcc GCC_USB20_MASTER_CLK>; 1427 assigned-clock-rates = <19200000>, <60000000>; 1428 1429 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1430 interrupt-names = "hs_phy_irq"; 1431 1432 qcom,select-utmi-as-pipe-clk; 1433 1434 resets = <&gcc GCC_USB_20_BCR>; 1435 1436 usb2_dwc3: usb@c200000 { 1437 compatible = "snps,dwc3"; 1438 reg = <0x0c200000 0xc8d0>; 1439 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1440 snps,dis_u2_susphy_quirk; 1441 snps,dis_enblslpm_quirk; 1442 1443 /* This is the HS-only host */ 1444 maximum-speed = "high-speed"; 1445 phys = <&qusb2phy1>; 1446 phy-names = "usb2-phy"; 1447 snps,hird-threshold = /bits/ 8 <0>; 1448 }; 1449 }; 1450 1451 mmcc: clock-controller@c8c0000 { 1452 compatible = "qcom,mmcc-sdm630"; 1453 reg = <0x0c8c0000 0x40000>; 1454 #clock-cells = <1>; 1455 #reset-cells = <1>; 1456 #power-domain-cells = <1>; 1457 clock-names = "xo", 1458 "sleep_clk", 1459 "gpll0", 1460 "gpll0_div", 1461 "dsi0pll", 1462 "dsi0pllbyte", 1463 "dsi1pll", 1464 "dsi1pllbyte", 1465 "dp_link_2x_clk_divsel_five", 1466 "dp_vco_divided_clk_src_mux"; 1467 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1468 <&sleep_clk>, 1469 <&gcc GCC_MMSS_GPLL0_CLK>, 1470 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1471 <&mdss_dsi0_phy 1>, 1472 <&mdss_dsi0_phy 0>, 1473 <0>, 1474 <0>, 1475 <0>, 1476 <0>; 1477 }; 1478 1479 mdss: display-subsystem@c900000 { 1480 compatible = "qcom,mdss"; 1481 reg = <0x0c900000 0x1000>, 1482 <0x0c9b0000 0x1040>; 1483 reg-names = "mdss_phys", "vbif_phys"; 1484 1485 power-domains = <&mmcc MDSS_GDSC>; 1486 1487 clocks = <&mmcc MDSS_AHB_CLK>, 1488 <&mmcc MDSS_AXI_CLK>, 1489 <&mmcc MDSS_VSYNC_CLK>, 1490 <&mmcc MDSS_MDP_CLK>; 1491 clock-names = "iface", 1492 "bus", 1493 "vsync", 1494 "core"; 1495 1496 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1497 1498 interrupt-controller; 1499 #interrupt-cells = <1>; 1500 1501 #address-cells = <1>; 1502 #size-cells = <1>; 1503 ranges; 1504 status = "disabled"; 1505 1506 mdp: display-controller@c901000 { 1507 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1508 reg = <0x0c901000 0x89000>; 1509 reg-names = "mdp_phys"; 1510 1511 interrupt-parent = <&mdss>; 1512 interrupts = <0>; 1513 1514 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1515 <&mmcc MDSS_VSYNC_CLK>; 1516 assigned-clock-rates = <300000000>, 1517 <19200000>; 1518 clocks = <&mmcc MDSS_AHB_CLK>, 1519 <&mmcc MDSS_AXI_CLK>, 1520 <&mmcc MDSS_MDP_CLK>, 1521 <&mmcc MDSS_VSYNC_CLK>; 1522 clock-names = "iface", 1523 "bus", 1524 "core", 1525 "vsync"; 1526 1527 interconnects = <&mnoc 2 &bimc 5>, 1528 <&mnoc 3 &bimc 5>, 1529 <&gnoc 0 &mnoc 17>; 1530 interconnect-names = "mdp0-mem", 1531 "mdp1-mem", 1532 "rotator-mem"; 1533 iommus = <&mmss_smmu 0>; 1534 operating-points-v2 = <&mdp_opp_table>; 1535 power-domains = <&rpmpd SDM660_VDDCX>; 1536 1537 ports { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 port@0 { 1542 reg = <0>; 1543 mdp5_intf1_out: endpoint { 1544 remote-endpoint = <&mdss_dsi0_in>; 1545 }; 1546 }; 1547 }; 1548 1549 mdp_opp_table: opp-table { 1550 compatible = "operating-points-v2"; 1551 1552 opp-150000000 { 1553 opp-hz = /bits/ 64 <150000000>; 1554 opp-peak-kBps = <320000 320000 76800>; 1555 required-opps = <&rpmpd_opp_low_svs>; 1556 }; 1557 opp-275000000 { 1558 opp-hz = /bits/ 64 <275000000>; 1559 opp-peak-kBps = <6400000 6400000 160000>; 1560 required-opps = <&rpmpd_opp_svs>; 1561 }; 1562 opp-300000000 { 1563 opp-hz = /bits/ 64 <300000000>; 1564 opp-peak-kBps = <6400000 6400000 190000>; 1565 required-opps = <&rpmpd_opp_svs_plus>; 1566 }; 1567 opp-330000000 { 1568 opp-hz = /bits/ 64 <330000000>; 1569 opp-peak-kBps = <6400000 6400000 240000>; 1570 required-opps = <&rpmpd_opp_nom>; 1571 }; 1572 opp-412500000 { 1573 opp-hz = /bits/ 64 <412500000>; 1574 opp-peak-kBps = <6400000 6400000 320000>; 1575 required-opps = <&rpmpd_opp_turbo>; 1576 }; 1577 }; 1578 }; 1579 1580 mdss_dsi0: dsi@c994000 { 1581 compatible = "qcom,sdm660-dsi-ctrl", 1582 "qcom,mdss-dsi-ctrl"; 1583 reg = <0x0c994000 0x400>; 1584 reg-names = "dsi_ctrl"; 1585 1586 operating-points-v2 = <&dsi_opp_table>; 1587 power-domains = <&rpmpd SDM660_VDDCX>; 1588 1589 interrupt-parent = <&mdss>; 1590 interrupts = <4>; 1591 1592 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1593 <&mmcc PCLK0_CLK_SRC>; 1594 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1595 <&mdss_dsi0_phy 1>; 1596 1597 clocks = <&mmcc MDSS_MDP_CLK>, 1598 <&mmcc MDSS_BYTE0_CLK>, 1599 <&mmcc MDSS_BYTE0_INTF_CLK>, 1600 <&mmcc MNOC_AHB_CLK>, 1601 <&mmcc MDSS_AHB_CLK>, 1602 <&mmcc MDSS_AXI_CLK>, 1603 <&mmcc MISC_AHB_CLK>, 1604 <&mmcc MDSS_PCLK0_CLK>, 1605 <&mmcc MDSS_ESC0_CLK>; 1606 clock-names = "mdp_core", 1607 "byte", 1608 "byte_intf", 1609 "mnoc", 1610 "iface", 1611 "bus", 1612 "core_mmss", 1613 "pixel", 1614 "core"; 1615 1616 phys = <&mdss_dsi0_phy>; 1617 1618 status = "disabled"; 1619 1620 ports { 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 1624 port@0 { 1625 reg = <0>; 1626 mdss_dsi0_in: endpoint { 1627 remote-endpoint = <&mdp5_intf1_out>; 1628 }; 1629 }; 1630 1631 port@1 { 1632 reg = <1>; 1633 mdss_dsi0_out: endpoint { 1634 }; 1635 }; 1636 }; 1637 }; 1638 1639 mdss_dsi0_phy: phy@c994400 { 1640 compatible = "qcom,dsi-phy-14nm-660"; 1641 reg = <0x0c994400 0x100>, 1642 <0x0c994500 0x300>, 1643 <0x0c994800 0x188>; 1644 reg-names = "dsi_phy", 1645 "dsi_phy_lane", 1646 "dsi_pll"; 1647 1648 #clock-cells = <1>; 1649 #phy-cells = <0>; 1650 1651 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1652 clock-names = "iface", "ref"; 1653 status = "disabled"; 1654 }; 1655 }; 1656 1657 blsp1_dma: dma-controller@c144000 { 1658 compatible = "qcom,bam-v1.7.0"; 1659 reg = <0x0c144000 0x1f000>; 1660 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1661 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1662 clock-names = "bam_clk"; 1663 #dma-cells = <1>; 1664 qcom,ee = <0>; 1665 qcom,controlled-remotely; 1666 num-channels = <18>; 1667 qcom,num-ees = <4>; 1668 }; 1669 1670 blsp1_uart1: serial@c16f000 { 1671 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1672 reg = <0x0c16f000 0x200>; 1673 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1674 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1675 <&gcc GCC_BLSP1_AHB_CLK>; 1676 clock-names = "core", "iface"; 1677 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1678 dma-names = "tx", "rx"; 1679 pinctrl-names = "default", "sleep"; 1680 pinctrl-0 = <&blsp1_uart1_default>; 1681 pinctrl-1 = <&blsp1_uart1_sleep>; 1682 status = "disabled"; 1683 }; 1684 1685 blsp1_uart2: serial@c170000 { 1686 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1687 reg = <0x0c170000 0x1000>; 1688 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1689 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1690 <&gcc GCC_BLSP1_AHB_CLK>; 1691 clock-names = "core", "iface"; 1692 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1693 dma-names = "tx", "rx"; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&blsp1_uart2_default>; 1696 status = "disabled"; 1697 }; 1698 1699 blsp_i2c1: i2c@c175000 { 1700 compatible = "qcom,i2c-qup-v2.2.1"; 1701 reg = <0x0c175000 0x600>; 1702 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1703 1704 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1705 <&gcc GCC_BLSP1_AHB_CLK>; 1706 clock-names = "core", "iface"; 1707 clock-frequency = <400000>; 1708 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1709 dma-names = "tx", "rx"; 1710 1711 pinctrl-names = "default", "sleep"; 1712 pinctrl-0 = <&i2c1_default>; 1713 pinctrl-1 = <&i2c1_sleep>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 status = "disabled"; 1717 }; 1718 1719 blsp_i2c2: i2c@c176000 { 1720 compatible = "qcom,i2c-qup-v2.2.1"; 1721 reg = <0x0c176000 0x600>; 1722 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1723 1724 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1725 <&gcc GCC_BLSP1_AHB_CLK>; 1726 clock-names = "core", "iface"; 1727 clock-frequency = <400000>; 1728 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1729 dma-names = "tx", "rx"; 1730 1731 pinctrl-names = "default", "sleep"; 1732 pinctrl-0 = <&i2c2_default>; 1733 pinctrl-1 = <&i2c2_sleep>; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 status = "disabled"; 1737 }; 1738 1739 blsp_i2c3: i2c@c177000 { 1740 compatible = "qcom,i2c-qup-v2.2.1"; 1741 reg = <0x0c177000 0x600>; 1742 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1745 <&gcc GCC_BLSP1_AHB_CLK>; 1746 clock-names = "core", "iface"; 1747 clock-frequency = <400000>; 1748 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1749 dma-names = "tx", "rx"; 1750 1751 pinctrl-names = "default", "sleep"; 1752 pinctrl-0 = <&i2c3_default>; 1753 pinctrl-1 = <&i2c3_sleep>; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 status = "disabled"; 1757 }; 1758 1759 blsp_i2c4: i2c@c178000 { 1760 compatible = "qcom,i2c-qup-v2.2.1"; 1761 reg = <0x0c178000 0x600>; 1762 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1763 1764 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1765 <&gcc GCC_BLSP1_AHB_CLK>; 1766 clock-names = "core", "iface"; 1767 clock-frequency = <400000>; 1768 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1769 dma-names = "tx", "rx"; 1770 1771 pinctrl-names = "default", "sleep"; 1772 pinctrl-0 = <&i2c4_default>; 1773 pinctrl-1 = <&i2c4_sleep>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 status = "disabled"; 1777 }; 1778 1779 blsp2_dma: dma-controller@c184000 { 1780 compatible = "qcom,bam-v1.7.0"; 1781 reg = <0x0c184000 0x1f000>; 1782 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1784 clock-names = "bam_clk"; 1785 #dma-cells = <1>; 1786 qcom,ee = <0>; 1787 qcom,controlled-remotely; 1788 num-channels = <18>; 1789 qcom,num-ees = <4>; 1790 }; 1791 1792 blsp2_uart1: serial@c1af000 { 1793 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1794 reg = <0x0c1af000 0x200>; 1795 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1796 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1797 <&gcc GCC_BLSP2_AHB_CLK>; 1798 clock-names = "core", "iface"; 1799 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1800 dma-names = "tx", "rx"; 1801 pinctrl-names = "default", "sleep"; 1802 pinctrl-0 = <&blsp2_uart1_default>; 1803 pinctrl-1 = <&blsp2_uart1_sleep>; 1804 status = "disabled"; 1805 }; 1806 1807 blsp_i2c5: i2c@c1b5000 { 1808 compatible = "qcom,i2c-qup-v2.2.1"; 1809 reg = <0x0c1b5000 0x600>; 1810 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1811 1812 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1813 <&gcc GCC_BLSP2_AHB_CLK>; 1814 clock-names = "core", "iface"; 1815 clock-frequency = <400000>; 1816 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1817 dma-names = "tx", "rx"; 1818 1819 pinctrl-names = "default", "sleep"; 1820 pinctrl-0 = <&i2c5_default>; 1821 pinctrl-1 = <&i2c5_sleep>; 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 status = "disabled"; 1825 }; 1826 1827 blsp_i2c6: i2c@c1b6000 { 1828 compatible = "qcom,i2c-qup-v2.2.1"; 1829 reg = <0x0c1b6000 0x600>; 1830 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1831 1832 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1833 <&gcc GCC_BLSP2_AHB_CLK>; 1834 clock-names = "core", "iface"; 1835 clock-frequency = <400000>; 1836 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1837 dma-names = "tx", "rx"; 1838 1839 pinctrl-names = "default", "sleep"; 1840 pinctrl-0 = <&i2c6_default>; 1841 pinctrl-1 = <&i2c6_sleep>; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 status = "disabled"; 1845 }; 1846 1847 blsp_i2c7: i2c@c1b7000 { 1848 compatible = "qcom,i2c-qup-v2.2.1"; 1849 reg = <0x0c1b7000 0x600>; 1850 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1851 1852 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1853 <&gcc GCC_BLSP2_AHB_CLK>; 1854 clock-names = "core", "iface"; 1855 clock-frequency = <400000>; 1856 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1857 dma-names = "tx", "rx"; 1858 1859 pinctrl-names = "default", "sleep"; 1860 pinctrl-0 = <&i2c7_default>; 1861 pinctrl-1 = <&i2c7_sleep>; 1862 #address-cells = <1>; 1863 #size-cells = <0>; 1864 status = "disabled"; 1865 }; 1866 1867 blsp_i2c8: i2c@c1b8000 { 1868 compatible = "qcom,i2c-qup-v2.2.1"; 1869 reg = <0x0c1b8000 0x600>; 1870 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1871 1872 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1873 <&gcc GCC_BLSP2_AHB_CLK>; 1874 clock-names = "core", "iface"; 1875 clock-frequency = <400000>; 1876 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1877 dma-names = "tx", "rx"; 1878 1879 pinctrl-names = "default", "sleep"; 1880 pinctrl-0 = <&i2c8_default>; 1881 pinctrl-1 = <&i2c8_sleep>; 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 status = "disabled"; 1885 }; 1886 1887 sram@146bf000 { 1888 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1889 reg = <0x146bf000 0x1000>; 1890 1891 #address-cells = <1>; 1892 #size-cells = <1>; 1893 1894 ranges = <0 0x146bf000 0x1000>; 1895 1896 pil-reloc@94c { 1897 compatible = "qcom,pil-reloc-info"; 1898 reg = <0x94c 0xc8>; 1899 }; 1900 }; 1901 1902 camss: camss@ca00020 { 1903 compatible = "qcom,sdm660-camss"; 1904 reg = <0x0ca00020 0x10>, 1905 <0x0ca30000 0x100>, 1906 <0x0ca30400 0x100>, 1907 <0x0ca30800 0x100>, 1908 <0x0ca30c00 0x100>, 1909 <0x0c824000 0x1000>, 1910 <0x0ca00120 0x4>, 1911 <0x0c825000 0x1000>, 1912 <0x0ca00124 0x4>, 1913 <0x0c826000 0x1000>, 1914 <0x0ca00128 0x4>, 1915 <0x0ca31000 0x500>, 1916 <0x0ca10000 0x1000>, 1917 <0x0ca14000 0x1000>; 1918 reg-names = "csi_clk_mux", 1919 "csid0", 1920 "csid1", 1921 "csid2", 1922 "csid3", 1923 "csiphy0", 1924 "csiphy0_clk_mux", 1925 "csiphy1", 1926 "csiphy1_clk_mux", 1927 "csiphy2", 1928 "csiphy2_clk_mux", 1929 "ispif", 1930 "vfe0", 1931 "vfe1"; 1932 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1933 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1934 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1935 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1936 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1937 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1938 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1939 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1940 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1941 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1942 interrupt-names = "csid0", 1943 "csid1", 1944 "csid2", 1945 "csid3", 1946 "csiphy0", 1947 "csiphy1", 1948 "csiphy2", 1949 "ispif", 1950 "vfe0", 1951 "vfe1"; 1952 clocks = <&mmcc CAMSS_AHB_CLK>, 1953 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1954 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1955 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1956 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1957 <&mmcc CAMSS_CSI0_AHB_CLK>, 1958 <&mmcc CAMSS_CSI0_CLK>, 1959 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1960 <&mmcc CAMSS_CSI0PIX_CLK>, 1961 <&mmcc CAMSS_CSI0RDI_CLK>, 1962 <&mmcc CAMSS_CSI1_AHB_CLK>, 1963 <&mmcc CAMSS_CSI1_CLK>, 1964 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1965 <&mmcc CAMSS_CSI1PIX_CLK>, 1966 <&mmcc CAMSS_CSI1RDI_CLK>, 1967 <&mmcc CAMSS_CSI2_AHB_CLK>, 1968 <&mmcc CAMSS_CSI2_CLK>, 1969 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1970 <&mmcc CAMSS_CSI2PIX_CLK>, 1971 <&mmcc CAMSS_CSI2RDI_CLK>, 1972 <&mmcc CAMSS_CSI3_AHB_CLK>, 1973 <&mmcc CAMSS_CSI3_CLK>, 1974 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1975 <&mmcc CAMSS_CSI3PIX_CLK>, 1976 <&mmcc CAMSS_CSI3RDI_CLK>, 1977 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1978 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1979 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1980 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1981 <&mmcc CAMSS_CSI_VFE0_CLK>, 1982 <&mmcc CAMSS_CSI_VFE1_CLK>, 1983 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1984 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1985 <&mmcc CAMSS_TOP_AHB_CLK>, 1986 <&mmcc CAMSS_VFE0_AHB_CLK>, 1987 <&mmcc CAMSS_VFE0_CLK>, 1988 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1989 <&mmcc CAMSS_VFE1_AHB_CLK>, 1990 <&mmcc CAMSS_VFE1_CLK>, 1991 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1992 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1993 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1994 clock-names = "ahb", 1995 "cphy_csid0", 1996 "cphy_csid1", 1997 "cphy_csid2", 1998 "cphy_csid3", 1999 "csi0_ahb", 2000 "csi0", 2001 "csi0_phy", 2002 "csi0_pix", 2003 "csi0_rdi", 2004 "csi1_ahb", 2005 "csi1", 2006 "csi1_phy", 2007 "csi1_pix", 2008 "csi1_rdi", 2009 "csi2_ahb", 2010 "csi2", 2011 "csi2_phy", 2012 "csi2_pix", 2013 "csi2_rdi", 2014 "csi3_ahb", 2015 "csi3", 2016 "csi3_phy", 2017 "csi3_pix", 2018 "csi3_rdi", 2019 "csiphy0_timer", 2020 "csiphy1_timer", 2021 "csiphy2_timer", 2022 "csiphy_ahb2crif", 2023 "csi_vfe0", 2024 "csi_vfe1", 2025 "ispif_ahb", 2026 "throttle_axi", 2027 "top_ahb", 2028 "vfe0_ahb", 2029 "vfe0", 2030 "vfe0_stream", 2031 "vfe1_ahb", 2032 "vfe1", 2033 "vfe1_stream", 2034 "vfe_ahb", 2035 "vfe_axi"; 2036 interconnects = <&mnoc 5 &bimc 5>; 2037 interconnect-names = "vfe-mem"; 2038 iommus = <&mmss_smmu 0xc00>, 2039 <&mmss_smmu 0xc01>, 2040 <&mmss_smmu 0xc02>, 2041 <&mmss_smmu 0xc03>; 2042 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2043 <&mmcc CAMSS_VFE1_GDSC>; 2044 status = "disabled"; 2045 2046 ports { 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 }; 2050 }; 2051 2052 cci: cci@ca0c000 { 2053 compatible = "qcom,msm8996-cci"; 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 reg = <0x0ca0c000 0x1000>; 2057 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2058 2059 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2060 <&mmcc CAMSS_CCI_CLK>; 2061 assigned-clock-rates = <80800000>, <37500000>; 2062 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2063 <&mmcc CAMSS_CCI_AHB_CLK>, 2064 <&mmcc CAMSS_CCI_CLK>, 2065 <&mmcc CAMSS_AHB_CLK>; 2066 clock-names = "camss_top_ahb", 2067 "cci_ahb", 2068 "cci", 2069 "camss_ahb"; 2070 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&cci0_default &cci1_default>; 2073 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2074 status = "disabled"; 2075 2076 cci_i2c0: i2c-bus@0 { 2077 reg = <0>; 2078 clock-frequency = <400000>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 }; 2082 2083 cci_i2c1: i2c-bus@1 { 2084 reg = <1>; 2085 clock-frequency = <400000>; 2086 #address-cells = <1>; 2087 #size-cells = <0>; 2088 }; 2089 }; 2090 2091 venus: video-codec@cc00000 { 2092 compatible = "qcom,sdm660-venus"; 2093 reg = <0x0cc00000 0xff000>; 2094 clocks = <&mmcc VIDEO_CORE_CLK>, 2095 <&mmcc VIDEO_AHB_CLK>, 2096 <&mmcc VIDEO_AXI_CLK>, 2097 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2098 clock-names = "core", "iface", "bus", "bus_throttle"; 2099 interconnects = <&gnoc 0 &mnoc 13>, 2100 <&mnoc 4 &bimc 5>; 2101 interconnect-names = "cpu-cfg", "video-mem"; 2102 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2103 iommus = <&mmss_smmu 0x400>, 2104 <&mmss_smmu 0x401>, 2105 <&mmss_smmu 0x40a>, 2106 <&mmss_smmu 0x407>, 2107 <&mmss_smmu 0x40e>, 2108 <&mmss_smmu 0x40f>, 2109 <&mmss_smmu 0x408>, 2110 <&mmss_smmu 0x409>, 2111 <&mmss_smmu 0x40b>, 2112 <&mmss_smmu 0x40c>, 2113 <&mmss_smmu 0x40d>, 2114 <&mmss_smmu 0x410>, 2115 <&mmss_smmu 0x421>, 2116 <&mmss_smmu 0x428>, 2117 <&mmss_smmu 0x429>, 2118 <&mmss_smmu 0x42b>, 2119 <&mmss_smmu 0x42c>, 2120 <&mmss_smmu 0x42d>, 2121 <&mmss_smmu 0x411>, 2122 <&mmss_smmu 0x431>; 2123 memory-region = <&venus_region>; 2124 power-domains = <&mmcc VENUS_GDSC>; 2125 status = "disabled"; 2126 2127 video-decoder { 2128 compatible = "venus-decoder"; 2129 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2130 clock-names = "vcodec0_core"; 2131 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2132 }; 2133 2134 video-encoder { 2135 compatible = "venus-encoder"; 2136 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2137 clock-names = "vcodec0_core"; 2138 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2139 }; 2140 }; 2141 2142 mmss_smmu: iommu@cd00000 { 2143 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2144 reg = <0x0cd00000 0x40000>; 2145 2146 clocks = <&mmcc MNOC_AHB_CLK>, 2147 <&mmcc BIMC_SMMU_AHB_CLK>, 2148 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2149 <&mmcc BIMC_SMMU_AXI_CLK>; 2150 clock-names = "iface-mm", "iface-smmu", 2151 "bus-mm", "bus-smmu"; 2152 #global-interrupts = <2>; 2153 #iommu-cells = <1>; 2154 2155 interrupts = 2156 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2158 2159 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2183 2184 status = "disabled"; 2185 }; 2186 2187 adsp_pil: remoteproc@15700000 { 2188 compatible = "qcom,sdm660-adsp-pas"; 2189 reg = <0x15700000 0x4040>; 2190 2191 interrupts-extended = 2192 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2193 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2194 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2195 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2196 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2197 interrupt-names = "wdog", "fatal", "ready", 2198 "handover", "stop-ack"; 2199 2200 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2201 clock-names = "xo"; 2202 2203 memory-region = <&adsp_region>; 2204 power-domains = <&rpmpd SDM660_VDDCX>; 2205 power-domain-names = "cx"; 2206 2207 qcom,smem-states = <&adsp_smp2p_out 0>; 2208 qcom,smem-state-names = "stop"; 2209 2210 glink-edge { 2211 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2212 2213 label = "lpass"; 2214 mboxes = <&apcs_glb 9>; 2215 qcom,remote-pid = <2>; 2216 2217 apr { 2218 compatible = "qcom,apr-v2"; 2219 qcom,glink-channels = "apr_audio_svc"; 2220 qcom,domain = <APR_DOMAIN_ADSP>; 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 2224 service@3 { 2225 reg = <APR_SVC_ADSP_CORE>; 2226 compatible = "qcom,q6core"; 2227 }; 2228 2229 q6afe: service@4 { 2230 compatible = "qcom,q6afe"; 2231 reg = <APR_SVC_AFE>; 2232 q6afedai: dais { 2233 compatible = "qcom,q6afe-dais"; 2234 #address-cells = <1>; 2235 #size-cells = <0>; 2236 #sound-dai-cells = <1>; 2237 }; 2238 }; 2239 2240 q6asm: service@7 { 2241 compatible = "qcom,q6asm"; 2242 reg = <APR_SVC_ASM>; 2243 q6asmdai: dais { 2244 compatible = "qcom,q6asm-dais"; 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 #sound-dai-cells = <1>; 2248 iommus = <&lpass_smmu 1>; 2249 }; 2250 }; 2251 2252 q6adm: service@8 { 2253 compatible = "qcom,q6adm"; 2254 reg = <APR_SVC_ADM>; 2255 q6routing: routing { 2256 compatible = "qcom,q6adm-routing"; 2257 #sound-dai-cells = <0>; 2258 }; 2259 }; 2260 }; 2261 }; 2262 }; 2263 2264 gnoc: interconnect@17900000 { 2265 compatible = "qcom,sdm660-gnoc"; 2266 reg = <0x17900000 0xe000>; 2267 #interconnect-cells = <1>; 2268 /* 2269 * This one apparently features no clocks, 2270 * so let's not mess with the driver needlessly 2271 */ 2272 clock-names = "bus", "bus_a"; 2273 clocks = <&xo_board>, <&xo_board>; 2274 }; 2275 2276 apcs_glb: mailbox@17911000 { 2277 compatible = "qcom,sdm660-apcs-hmss-global", 2278 "qcom,msm8994-apcs-kpss-global"; 2279 reg = <0x17911000 0x1000>; 2280 2281 #mbox-cells = <1>; 2282 }; 2283 2284 timer@17920000 { 2285 #address-cells = <1>; 2286 #size-cells = <1>; 2287 ranges; 2288 compatible = "arm,armv7-timer-mem"; 2289 reg = <0x17920000 0x1000>; 2290 clock-frequency = <19200000>; 2291 2292 frame@17921000 { 2293 frame-number = <0>; 2294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2296 reg = <0x17921000 0x1000>, 2297 <0x17922000 0x1000>; 2298 }; 2299 2300 frame@17923000 { 2301 frame-number = <1>; 2302 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2303 reg = <0x17923000 0x1000>; 2304 status = "disabled"; 2305 }; 2306 2307 frame@17924000 { 2308 frame-number = <2>; 2309 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2310 reg = <0x17924000 0x1000>; 2311 status = "disabled"; 2312 }; 2313 2314 frame@17925000 { 2315 frame-number = <3>; 2316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2317 reg = <0x17925000 0x1000>; 2318 status = "disabled"; 2319 }; 2320 2321 frame@17926000 { 2322 frame-number = <4>; 2323 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2324 reg = <0x17926000 0x1000>; 2325 status = "disabled"; 2326 }; 2327 2328 frame@17927000 { 2329 frame-number = <5>; 2330 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2331 reg = <0x17927000 0x1000>; 2332 status = "disabled"; 2333 }; 2334 2335 frame@17928000 { 2336 frame-number = <6>; 2337 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2338 reg = <0x17928000 0x1000>; 2339 status = "disabled"; 2340 }; 2341 }; 2342 2343 intc: interrupt-controller@17a00000 { 2344 compatible = "arm,gic-v3"; 2345 reg = <0x17a00000 0x10000>, /* GICD */ 2346 <0x17b00000 0x100000>; /* GICR * 8 */ 2347 #interrupt-cells = <3>; 2348 #address-cells = <1>; 2349 #size-cells = <1>; 2350 ranges; 2351 interrupt-controller; 2352 #redistributor-regions = <1>; 2353 redistributor-stride = <0x0 0x20000>; 2354 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2355 }; 2356 }; 2357 2358 sound: sound { 2359 }; 2360 2361 thermal-zones { 2362 aoss-thermal { 2363 polling-delay-passive = <250>; 2364 polling-delay = <1000>; 2365 2366 thermal-sensors = <&tsens 0>; 2367 2368 trips { 2369 aoss_alert0: trip-point0 { 2370 temperature = <105000>; 2371 hysteresis = <1000>; 2372 type = "hot"; 2373 }; 2374 }; 2375 }; 2376 2377 cpuss0-thermal { 2378 polling-delay-passive = <250>; 2379 polling-delay = <1000>; 2380 2381 thermal-sensors = <&tsens 1>; 2382 2383 trips { 2384 cpuss0_alert0: trip-point0 { 2385 temperature = <125000>; 2386 hysteresis = <1000>; 2387 type = "hot"; 2388 }; 2389 }; 2390 }; 2391 2392 cpuss1-thermal { 2393 polling-delay-passive = <250>; 2394 polling-delay = <1000>; 2395 2396 thermal-sensors = <&tsens 2>; 2397 2398 trips { 2399 cpuss1_alert0: trip-point0 { 2400 temperature = <125000>; 2401 hysteresis = <1000>; 2402 type = "hot"; 2403 }; 2404 }; 2405 }; 2406 2407 cpu0-thermal { 2408 polling-delay-passive = <250>; 2409 polling-delay = <1000>; 2410 2411 thermal-sensors = <&tsens 3>; 2412 2413 trips { 2414 cpu0_alert0: trip-point0 { 2415 temperature = <70000>; 2416 hysteresis = <1000>; 2417 type = "passive"; 2418 }; 2419 2420 cpu0_crit: cpu-crit { 2421 temperature = <110000>; 2422 hysteresis = <1000>; 2423 type = "critical"; 2424 }; 2425 }; 2426 }; 2427 2428 cpu1-thermal { 2429 polling-delay-passive = <250>; 2430 polling-delay = <1000>; 2431 2432 thermal-sensors = <&tsens 4>; 2433 2434 trips { 2435 cpu1_alert0: trip-point0 { 2436 temperature = <70000>; 2437 hysteresis = <1000>; 2438 type = "passive"; 2439 }; 2440 2441 cpu1_crit: cpu-crit { 2442 temperature = <110000>; 2443 hysteresis = <1000>; 2444 type = "critical"; 2445 }; 2446 }; 2447 }; 2448 2449 cpu2-thermal { 2450 polling-delay-passive = <250>; 2451 polling-delay = <1000>; 2452 2453 thermal-sensors = <&tsens 5>; 2454 2455 trips { 2456 cpu2_alert0: trip-point0 { 2457 temperature = <70000>; 2458 hysteresis = <1000>; 2459 type = "passive"; 2460 }; 2461 2462 cpu2_crit: cpu-crit { 2463 temperature = <110000>; 2464 hysteresis = <1000>; 2465 type = "critical"; 2466 }; 2467 }; 2468 }; 2469 2470 cpu3-thermal { 2471 polling-delay-passive = <250>; 2472 polling-delay = <1000>; 2473 2474 thermal-sensors = <&tsens 6>; 2475 2476 trips { 2477 cpu3_alert0: trip-point0 { 2478 temperature = <70000>; 2479 hysteresis = <1000>; 2480 type = "passive"; 2481 }; 2482 2483 cpu3_crit: cpu-crit { 2484 temperature = <110000>; 2485 hysteresis = <1000>; 2486 type = "critical"; 2487 }; 2488 }; 2489 }; 2490 2491 /* 2492 * According to what downstream DTS says, 2493 * the entire power efficient cluster has 2494 * only a single thermal sensor. 2495 */ 2496 2497 pwr-cluster-thermal { 2498 polling-delay-passive = <250>; 2499 polling-delay = <1000>; 2500 2501 thermal-sensors = <&tsens 7>; 2502 2503 trips { 2504 pwr_cluster_alert0: trip-point0 { 2505 temperature = <70000>; 2506 hysteresis = <1000>; 2507 type = "passive"; 2508 }; 2509 2510 pwr_cluster_crit: cpu-crit { 2511 temperature = <110000>; 2512 hysteresis = <1000>; 2513 type = "critical"; 2514 }; 2515 }; 2516 }; 2517 2518 gpu-thermal { 2519 polling-delay-passive = <250>; 2520 polling-delay = <1000>; 2521 2522 thermal-sensors = <&tsens 8>; 2523 2524 trips { 2525 gpu_alert0: trip-point0 { 2526 temperature = <90000>; 2527 hysteresis = <1000>; 2528 type = "hot"; 2529 }; 2530 }; 2531 }; 2532 }; 2533 2534 timer { 2535 compatible = "arm,armv8-timer"; 2536 interrupts = <GIC_PPI 1 0xf08>, 2537 <GIC_PPI 2 0xf08>, 2538 <GIC_PPI 3 0xf08>, 2539 <GIC_PPI 0 0xf08>; 2540 }; 2541}; 2542 2543