xref: /openbmc/linux/drivers/gpio/gpio-mmio.c (revision dee87316)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Generic driver for memory-mapped GPIO controllers.
4  *
5  * Copyright 2008 MontaVista Software, Inc.
6  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7  *
8  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
9  * ...``                                                         ```````..
10  * ..The simplest form of a GPIO controller that the driver supports is``
11  *  `.just a single "data" register, where GPIO state can be read and/or `
12  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
13  *        `````````
14                                     ___
15 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
16 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
17 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
18                                                  `....trivial..'~`.```.```
19  *                                                    ```````
20  *  .```````~~~~`..`.``.``.
21  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
22  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
23  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
24  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
25  *     ``.`.``...```                  ```.. output pins are also supported.`
26  *                        ^^             `````.`````````.,``~``~``~~``````
27  *                                                   .                  ^^
28  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29  * .. The expectation is that in at least some cases .    ,-~~~-,
30  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
31  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
32  *  ..````````......```````````                             \o_
33  *                                                           |
34  *                              ^^                          / \
35  *
36  *           ...`````~~`.....``.`..........``````.`.``.```........``.
37  *            `  8, 16, 32 and 64 bits registers are supported, and``.
38  *            . the number of GPIOs is determined by the width of   ~
39  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
40  *               `.......````.```
41  */
42 
43 #include <linux/init.h>
44 #include <linux/err.h>
45 #include <linux/bug.h>
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/spinlock.h>
49 #include <linux/compiler.h>
50 #include <linux/types.h>
51 #include <linux/errno.h>
52 #include <linux/log2.h>
53 #include <linux/ioport.h>
54 #include <linux/io.h>
55 #include <linux/gpio/driver.h>
56 #include <linux/slab.h>
57 #include <linux/bitops.h>
58 #include <linux/platform_device.h>
59 #include <linux/mod_devicetable.h>
60 #include <linux/of.h>
61 #include <linux/of_device.h>
62 
63 #include "gpiolib.h"
64 
bgpio_write8(void __iomem * reg,unsigned long data)65 static void bgpio_write8(void __iomem *reg, unsigned long data)
66 {
67 	writeb(data, reg);
68 }
69 
bgpio_read8(void __iomem * reg)70 static unsigned long bgpio_read8(void __iomem *reg)
71 {
72 	return readb(reg);
73 }
74 
bgpio_write16(void __iomem * reg,unsigned long data)75 static void bgpio_write16(void __iomem *reg, unsigned long data)
76 {
77 	writew(data, reg);
78 }
79 
bgpio_read16(void __iomem * reg)80 static unsigned long bgpio_read16(void __iomem *reg)
81 {
82 	return readw(reg);
83 }
84 
bgpio_write32(void __iomem * reg,unsigned long data)85 static void bgpio_write32(void __iomem *reg, unsigned long data)
86 {
87 	writel(data, reg);
88 }
89 
bgpio_read32(void __iomem * reg)90 static unsigned long bgpio_read32(void __iomem *reg)
91 {
92 	return readl(reg);
93 }
94 
95 #if BITS_PER_LONG >= 64
bgpio_write64(void __iomem * reg,unsigned long data)96 static void bgpio_write64(void __iomem *reg, unsigned long data)
97 {
98 	writeq(data, reg);
99 }
100 
bgpio_read64(void __iomem * reg)101 static unsigned long bgpio_read64(void __iomem *reg)
102 {
103 	return readq(reg);
104 }
105 #endif /* BITS_PER_LONG >= 64 */
106 
bgpio_write16be(void __iomem * reg,unsigned long data)107 static void bgpio_write16be(void __iomem *reg, unsigned long data)
108 {
109 	iowrite16be(data, reg);
110 }
111 
bgpio_read16be(void __iomem * reg)112 static unsigned long bgpio_read16be(void __iomem *reg)
113 {
114 	return ioread16be(reg);
115 }
116 
bgpio_write32be(void __iomem * reg,unsigned long data)117 static void bgpio_write32be(void __iomem *reg, unsigned long data)
118 {
119 	iowrite32be(data, reg);
120 }
121 
bgpio_read32be(void __iomem * reg)122 static unsigned long bgpio_read32be(void __iomem *reg)
123 {
124 	return ioread32be(reg);
125 }
126 
bgpio_line2mask(struct gpio_chip * gc,unsigned int line)127 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
128 {
129 	if (gc->be_bits)
130 		return BIT(gc->bgpio_bits - 1 - line);
131 	return BIT(line);
132 }
133 
bgpio_get_set(struct gpio_chip * gc,unsigned int gpio)134 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
135 {
136 	unsigned long pinmask = bgpio_line2mask(gc, gpio);
137 	bool dir = !!(gc->bgpio_dir & pinmask);
138 
139 	if (dir)
140 		return !!(gc->read_reg(gc->reg_set) & pinmask);
141 	else
142 		return !!(gc->read_reg(gc->reg_dat) & pinmask);
143 }
144 
145 /*
146  * This assumes that the bits in the GPIO register are in native endianness.
147  * We only assign the function pointer if we have that.
148  */
bgpio_get_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)149 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
150 				  unsigned long *bits)
151 {
152 	unsigned long get_mask = 0;
153 	unsigned long set_mask = 0;
154 
155 	/* Make sure we first clear any bits that are zero when we read the register */
156 	*bits &= ~*mask;
157 
158 	set_mask = *mask & gc->bgpio_dir;
159 	get_mask = *mask & ~gc->bgpio_dir;
160 
161 	if (set_mask)
162 		*bits |= gc->read_reg(gc->reg_set) & set_mask;
163 	if (get_mask)
164 		*bits |= gc->read_reg(gc->reg_dat) & get_mask;
165 
166 	return 0;
167 }
168 
bgpio_get(struct gpio_chip * gc,unsigned int gpio)169 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
170 {
171 	return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
172 }
173 
174 /*
175  * This only works if the bits in the GPIO register are in native endianness.
176  */
bgpio_get_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)177 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
178 			      unsigned long *bits)
179 {
180 	/* Make sure we first clear any bits that are zero when we read the register */
181 	*bits &= ~*mask;
182 	*bits |= gc->read_reg(gc->reg_dat) & *mask;
183 	return 0;
184 }
185 
186 /*
187  * With big endian mirrored bit order it becomes more tedious.
188  */
bgpio_get_multiple_be(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)189 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
190 				 unsigned long *bits)
191 {
192 	unsigned long readmask = 0;
193 	unsigned long val;
194 	int bit;
195 
196 	/* Make sure we first clear any bits that are zero when we read the register */
197 	*bits &= ~*mask;
198 
199 	/* Create a mirrored mask */
200 	for_each_set_bit(bit, mask, gc->ngpio)
201 		readmask |= bgpio_line2mask(gc, bit);
202 
203 	/* Read the register */
204 	val = gc->read_reg(gc->reg_dat) & readmask;
205 
206 	/*
207 	 * Mirror the result into the "bits" result, this will give line 0
208 	 * in bit 0 ... line 31 in bit 31 for a 32bit register.
209 	 */
210 	for_each_set_bit(bit, &val, gc->ngpio)
211 		*bits |= bgpio_line2mask(gc, bit);
212 
213 	return 0;
214 }
215 
bgpio_set_none(struct gpio_chip * gc,unsigned int gpio,int val)216 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
217 {
218 }
219 
bgpio_set(struct gpio_chip * gc,unsigned int gpio,int val)220 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
221 {
222 	unsigned long mask = bgpio_line2mask(gc, gpio);
223 	unsigned long flags;
224 
225 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
226 
227 	if (val)
228 		gc->bgpio_data |= mask;
229 	else
230 		gc->bgpio_data &= ~mask;
231 
232 	gc->write_reg(gc->reg_dat, gc->bgpio_data);
233 
234 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235 }
236 
bgpio_set_with_clear(struct gpio_chip * gc,unsigned int gpio,int val)237 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
238 				 int val)
239 {
240 	unsigned long mask = bgpio_line2mask(gc, gpio);
241 
242 	if (val)
243 		gc->write_reg(gc->reg_set, mask);
244 	else
245 		gc->write_reg(gc->reg_clr, mask);
246 }
247 
bgpio_set_set(struct gpio_chip * gc,unsigned int gpio,int val)248 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
249 {
250 	unsigned long mask = bgpio_line2mask(gc, gpio);
251 	unsigned long flags;
252 
253 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
254 
255 	if (val)
256 		gc->bgpio_data |= mask;
257 	else
258 		gc->bgpio_data &= ~mask;
259 
260 	gc->write_reg(gc->reg_set, gc->bgpio_data);
261 
262 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263 }
264 
bgpio_multiple_get_masks(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits,unsigned long * set_mask,unsigned long * clear_mask)265 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
266 				     unsigned long *mask, unsigned long *bits,
267 				     unsigned long *set_mask,
268 				     unsigned long *clear_mask)
269 {
270 	int i;
271 
272 	*set_mask = 0;
273 	*clear_mask = 0;
274 
275 	for_each_set_bit(i, mask, gc->bgpio_bits) {
276 		if (test_bit(i, bits))
277 			*set_mask |= bgpio_line2mask(gc, i);
278 		else
279 			*clear_mask |= bgpio_line2mask(gc, i);
280 	}
281 }
282 
bgpio_set_multiple_single_reg(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits,void __iomem * reg)283 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
284 					  unsigned long *mask,
285 					  unsigned long *bits,
286 					  void __iomem *reg)
287 {
288 	unsigned long flags;
289 	unsigned long set_mask, clear_mask;
290 
291 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
292 
293 	bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
294 
295 	gc->bgpio_data |= set_mask;
296 	gc->bgpio_data &= ~clear_mask;
297 
298 	gc->write_reg(reg, gc->bgpio_data);
299 
300 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
301 }
302 
bgpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)303 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
304 			       unsigned long *bits)
305 {
306 	bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
307 }
308 
bgpio_set_multiple_set(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)309 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
310 				   unsigned long *bits)
311 {
312 	bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
313 }
314 
bgpio_set_multiple_with_clear(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)315 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
316 					  unsigned long *mask,
317 					  unsigned long *bits)
318 {
319 	unsigned long set_mask, clear_mask;
320 
321 	bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
322 
323 	if (set_mask)
324 		gc->write_reg(gc->reg_set, set_mask);
325 	if (clear_mask)
326 		gc->write_reg(gc->reg_clr, clear_mask);
327 }
328 
bgpio_simple_dir_in(struct gpio_chip * gc,unsigned int gpio)329 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
330 {
331 	return 0;
332 }
333 
bgpio_dir_out_err(struct gpio_chip * gc,unsigned int gpio,int val)334 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
335 				int val)
336 {
337 	return -EINVAL;
338 }
339 
bgpio_simple_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)340 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
341 				int val)
342 {
343 	gc->set(gc, gpio, val);
344 
345 	return 0;
346 }
347 
bgpio_dir_in(struct gpio_chip * gc,unsigned int gpio)348 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
349 {
350 	unsigned long flags;
351 
352 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
353 
354 	gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
355 
356 	if (gc->reg_dir_in)
357 		gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
358 	if (gc->reg_dir_out)
359 		gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
360 
361 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
362 
363 	return 0;
364 }
365 
bgpio_get_dir(struct gpio_chip * gc,unsigned int gpio)366 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
367 {
368 	/* Return 0 if output, 1 if input */
369 	if (gc->bgpio_dir_unreadable) {
370 		if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
371 			return GPIO_LINE_DIRECTION_OUT;
372 		return GPIO_LINE_DIRECTION_IN;
373 	}
374 
375 	if (gc->reg_dir_out) {
376 		if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
377 			return GPIO_LINE_DIRECTION_OUT;
378 		return GPIO_LINE_DIRECTION_IN;
379 	}
380 
381 	if (gc->reg_dir_in)
382 		if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
383 			return GPIO_LINE_DIRECTION_OUT;
384 
385 	return GPIO_LINE_DIRECTION_IN;
386 }
387 
bgpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)388 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
389 {
390 	unsigned long flags;
391 
392 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
393 
394 	gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
395 
396 	if (gc->reg_dir_in)
397 		gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
398 	if (gc->reg_dir_out)
399 		gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
400 
401 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
402 }
403 
bgpio_dir_out_dir_first(struct gpio_chip * gc,unsigned int gpio,int val)404 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
405 				   int val)
406 {
407 	bgpio_dir_out(gc, gpio, val);
408 	gc->set(gc, gpio, val);
409 	return 0;
410 }
411 
bgpio_dir_out_val_first(struct gpio_chip * gc,unsigned int gpio,int val)412 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
413 				   int val)
414 {
415 	gc->set(gc, gpio, val);
416 	bgpio_dir_out(gc, gpio, val);
417 	return 0;
418 }
419 
bgpio_setup_accessors(struct device * dev,struct gpio_chip * gc,bool byte_be)420 static int bgpio_setup_accessors(struct device *dev,
421 				 struct gpio_chip *gc,
422 				 bool byte_be)
423 {
424 
425 	switch (gc->bgpio_bits) {
426 	case 8:
427 		gc->read_reg	= bgpio_read8;
428 		gc->write_reg	= bgpio_write8;
429 		break;
430 	case 16:
431 		if (byte_be) {
432 			gc->read_reg	= bgpio_read16be;
433 			gc->write_reg	= bgpio_write16be;
434 		} else {
435 			gc->read_reg	= bgpio_read16;
436 			gc->write_reg	= bgpio_write16;
437 		}
438 		break;
439 	case 32:
440 		if (byte_be) {
441 			gc->read_reg	= bgpio_read32be;
442 			gc->write_reg	= bgpio_write32be;
443 		} else {
444 			gc->read_reg	= bgpio_read32;
445 			gc->write_reg	= bgpio_write32;
446 		}
447 		break;
448 #if BITS_PER_LONG >= 64
449 	case 64:
450 		if (byte_be) {
451 			dev_err(dev,
452 				"64 bit big endian byte order unsupported\n");
453 			return -EINVAL;
454 		} else {
455 			gc->read_reg	= bgpio_read64;
456 			gc->write_reg	= bgpio_write64;
457 		}
458 		break;
459 #endif /* BITS_PER_LONG >= 64 */
460 	default:
461 		dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
462 		return -EINVAL;
463 	}
464 
465 	return 0;
466 }
467 
468 /*
469  * Create the device and allocate the resources.  For setting GPIO's there are
470  * three supported configurations:
471  *
472  *	- single input/output register resource (named "dat").
473  *	- set/clear pair (named "set" and "clr").
474  *	- single output register resource and single input resource ("set" and
475  *	dat").
476  *
477  * For the single output register, this drives a 1 by setting a bit and a zero
478  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
479  * in the set register and clears it by setting a bit in the clear register.
480  * The configuration is detected by which resources are present.
481  *
482  * For setting the GPIO direction, there are three supported configurations:
483  *
484  *	- simple bidirection GPIO that requires no configuration.
485  *	- an output direction register (named "dirout") where a 1 bit
486  *	indicates the GPIO is an output.
487  *	- an input direction register (named "dirin") where a 1 bit indicates
488  *	the GPIO is an input.
489  */
bgpio_setup_io(struct gpio_chip * gc,void __iomem * dat,void __iomem * set,void __iomem * clr,unsigned long flags)490 static int bgpio_setup_io(struct gpio_chip *gc,
491 			  void __iomem *dat,
492 			  void __iomem *set,
493 			  void __iomem *clr,
494 			  unsigned long flags)
495 {
496 
497 	gc->reg_dat = dat;
498 	if (!gc->reg_dat)
499 		return -EINVAL;
500 
501 	if (set && clr) {
502 		gc->reg_set = set;
503 		gc->reg_clr = clr;
504 		gc->set = bgpio_set_with_clear;
505 		gc->set_multiple = bgpio_set_multiple_with_clear;
506 	} else if (set && !clr) {
507 		gc->reg_set = set;
508 		gc->set = bgpio_set_set;
509 		gc->set_multiple = bgpio_set_multiple_set;
510 	} else if (flags & BGPIOF_NO_OUTPUT) {
511 		gc->set = bgpio_set_none;
512 		gc->set_multiple = NULL;
513 	} else {
514 		gc->set = bgpio_set;
515 		gc->set_multiple = bgpio_set_multiple;
516 	}
517 
518 	if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
519 	    (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
520 		gc->get = bgpio_get_set;
521 		if (!gc->be_bits)
522 			gc->get_multiple = bgpio_get_set_multiple;
523 		/*
524 		 * We deliberately avoid assigning the ->get_multiple() call
525 		 * for big endian mirrored registers which are ALSO reflecting
526 		 * their value in the set register when used as output. It is
527 		 * simply too much complexity, let the GPIO core fall back to
528 		 * reading each line individually in that fringe case.
529 		 */
530 	} else {
531 		gc->get = bgpio_get;
532 		if (gc->be_bits)
533 			gc->get_multiple = bgpio_get_multiple_be;
534 		else
535 			gc->get_multiple = bgpio_get_multiple;
536 	}
537 
538 	return 0;
539 }
540 
bgpio_setup_direction(struct gpio_chip * gc,void __iomem * dirout,void __iomem * dirin,unsigned long flags)541 static int bgpio_setup_direction(struct gpio_chip *gc,
542 				 void __iomem *dirout,
543 				 void __iomem *dirin,
544 				 unsigned long flags)
545 {
546 	if (dirout || dirin) {
547 		gc->reg_dir_out = dirout;
548 		gc->reg_dir_in = dirin;
549 		if (flags & BGPIOF_NO_SET_ON_INPUT)
550 			gc->direction_output = bgpio_dir_out_dir_first;
551 		else
552 			gc->direction_output = bgpio_dir_out_val_first;
553 		gc->direction_input = bgpio_dir_in;
554 		gc->get_direction = bgpio_get_dir;
555 	} else {
556 		if (flags & BGPIOF_NO_OUTPUT)
557 			gc->direction_output = bgpio_dir_out_err;
558 		else
559 			gc->direction_output = bgpio_simple_dir_out;
560 		gc->direction_input = bgpio_simple_dir_in;
561 	}
562 
563 	return 0;
564 }
565 
bgpio_request(struct gpio_chip * chip,unsigned gpio_pin)566 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
567 {
568 	if (gpio_pin < chip->ngpio)
569 		return 0;
570 
571 	return -EINVAL;
572 }
573 
574 /**
575  * bgpio_init() - Initialize generic GPIO accessor functions
576  * @gc: the GPIO chip to set up
577  * @dev: the parent device of the new GPIO chip (compulsory)
578  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
579  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
580  *	is expected that a 1 in the corresponding bit in this register means the
581  *	line is asserted
582  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
583  *	expected that we write the line with 1 in this register to drive the GPIO line
584  *	high.
585  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
586  *	expected that we write the line with 1 in this register to drive the GPIO line
587  *	low. It is allowed to leave this address as NULL, in that case the SET register
588  *	will be assumed to also clear the GPIO lines, by actively writing the line
589  *	with 0.
590  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
591  *	that setting a line to 1 in this register will turn that line into an
592  *	output line. Conversely, setting the line to 0 will turn that line into
593  *	an input.
594  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
595  *	that setting a line to 1 in this register will turn that line into an
596  *	input line. Conversely, setting the line to 0 will turn that line into
597  *	an output.
598  * @flags: Different flags that will affect the behaviour of the device, such as
599  *	endianness etc.
600  */
bgpio_init(struct gpio_chip * gc,struct device * dev,unsigned long sz,void __iomem * dat,void __iomem * set,void __iomem * clr,void __iomem * dirout,void __iomem * dirin,unsigned long flags)601 int bgpio_init(struct gpio_chip *gc, struct device *dev,
602 	       unsigned long sz, void __iomem *dat, void __iomem *set,
603 	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
604 	       unsigned long flags)
605 {
606 	int ret;
607 
608 	if (!is_power_of_2(sz))
609 		return -EINVAL;
610 
611 	gc->bgpio_bits = sz * 8;
612 	if (gc->bgpio_bits > BITS_PER_LONG)
613 		return -EINVAL;
614 
615 	raw_spin_lock_init(&gc->bgpio_lock);
616 	gc->parent = dev;
617 	gc->label = dev_name(dev);
618 	gc->base = -1;
619 	gc->request = bgpio_request;
620 	gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
621 
622 	ret = gpiochip_get_ngpios(gc, dev);
623 	if (ret)
624 		gc->ngpio = gc->bgpio_bits;
625 
626 	ret = bgpio_setup_io(gc, dat, set, clr, flags);
627 	if (ret)
628 		return ret;
629 
630 	ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
631 	if (ret)
632 		return ret;
633 
634 	ret = bgpio_setup_direction(gc, dirout, dirin, flags);
635 	if (ret)
636 		return ret;
637 
638 	gc->bgpio_data = gc->read_reg(gc->reg_dat);
639 	if (gc->set == bgpio_set_set &&
640 			!(flags & BGPIOF_UNREADABLE_REG_SET))
641 		gc->bgpio_data = gc->read_reg(gc->reg_set);
642 
643 	if (flags & BGPIOF_UNREADABLE_REG_DIR)
644 		gc->bgpio_dir_unreadable = true;
645 
646 	/*
647 	 * Inspect hardware to find initial direction setting.
648 	 */
649 	if ((gc->reg_dir_out || gc->reg_dir_in) &&
650 	    !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
651 		if (gc->reg_dir_out)
652 			gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
653 		else if (gc->reg_dir_in)
654 			gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
655 		/*
656 		 * If we have two direction registers, synchronise
657 		 * input setting to output setting, the library
658 		 * can not handle a line being input and output at
659 		 * the same time.
660 		 */
661 		if (gc->reg_dir_out && gc->reg_dir_in)
662 			gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
663 	}
664 
665 	return ret;
666 }
667 EXPORT_SYMBOL_GPL(bgpio_init);
668 
669 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
670 
bgpio_map(struct platform_device * pdev,const char * name,resource_size_t sane_sz)671 static void __iomem *bgpio_map(struct platform_device *pdev,
672 			       const char *name,
673 			       resource_size_t sane_sz)
674 {
675 	struct resource *r;
676 	resource_size_t sz;
677 
678 	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
679 	if (!r)
680 		return NULL;
681 
682 	sz = resource_size(r);
683 	if (sz != sane_sz)
684 		return IOMEM_ERR_PTR(-EINVAL);
685 
686 	return devm_ioremap_resource(&pdev->dev, r);
687 }
688 
689 #ifdef CONFIG_OF
690 static const struct of_device_id bgpio_of_match[] = {
691 	{ .compatible = "brcm,bcm6345-gpio" },
692 	{ .compatible = "wd,mbl-gpio" },
693 	{ .compatible = "ni,169445-nand-gpio" },
694 	{ }
695 };
696 MODULE_DEVICE_TABLE(of, bgpio_of_match);
697 
bgpio_parse_dt(struct platform_device * pdev,unsigned long * flags)698 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
699 					  unsigned long *flags)
700 {
701 	struct bgpio_pdata *pdata;
702 
703 	if (!of_match_device(bgpio_of_match, &pdev->dev))
704 		return NULL;
705 
706 	pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
707 			     GFP_KERNEL);
708 	if (!pdata)
709 		return ERR_PTR(-ENOMEM);
710 
711 	pdata->base = -1;
712 
713 	if (of_device_is_big_endian(pdev->dev.of_node))
714 		*flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
715 
716 	if (of_property_read_bool(pdev->dev.of_node, "no-output"))
717 		*flags |= BGPIOF_NO_OUTPUT;
718 
719 	return pdata;
720 }
721 #else
bgpio_parse_dt(struct platform_device * pdev,unsigned long * flags)722 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
723 					  unsigned long *flags)
724 {
725 	return NULL;
726 }
727 #endif /* CONFIG_OF */
728 
bgpio_pdev_probe(struct platform_device * pdev)729 static int bgpio_pdev_probe(struct platform_device *pdev)
730 {
731 	struct device *dev = &pdev->dev;
732 	struct resource *r;
733 	void __iomem *dat;
734 	void __iomem *set;
735 	void __iomem *clr;
736 	void __iomem *dirout;
737 	void __iomem *dirin;
738 	unsigned long sz;
739 	unsigned long flags = 0;
740 	int err;
741 	struct gpio_chip *gc;
742 	struct bgpio_pdata *pdata;
743 
744 	pdata = bgpio_parse_dt(pdev, &flags);
745 	if (IS_ERR(pdata))
746 		return PTR_ERR(pdata);
747 
748 	if (!pdata) {
749 		pdata = dev_get_platdata(dev);
750 		flags = pdev->id_entry->driver_data;
751 	}
752 
753 	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
754 	if (!r)
755 		return -EINVAL;
756 
757 	sz = resource_size(r);
758 
759 	dat = bgpio_map(pdev, "dat", sz);
760 	if (IS_ERR(dat))
761 		return PTR_ERR(dat);
762 
763 	set = bgpio_map(pdev, "set", sz);
764 	if (IS_ERR(set))
765 		return PTR_ERR(set);
766 
767 	clr = bgpio_map(pdev, "clr", sz);
768 	if (IS_ERR(clr))
769 		return PTR_ERR(clr);
770 
771 	dirout = bgpio_map(pdev, "dirout", sz);
772 	if (IS_ERR(dirout))
773 		return PTR_ERR(dirout);
774 
775 	dirin = bgpio_map(pdev, "dirin", sz);
776 	if (IS_ERR(dirin))
777 		return PTR_ERR(dirin);
778 
779 	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
780 	if (!gc)
781 		return -ENOMEM;
782 
783 	err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
784 	if (err)
785 		return err;
786 
787 	if (pdata) {
788 		if (pdata->label)
789 			gc->label = pdata->label;
790 		gc->base = pdata->base;
791 		if (pdata->ngpio > 0)
792 			gc->ngpio = pdata->ngpio;
793 	}
794 
795 	platform_set_drvdata(pdev, gc);
796 
797 	return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
798 }
799 
800 static const struct platform_device_id bgpio_id_table[] = {
801 	{
802 		.name		= "basic-mmio-gpio",
803 		.driver_data	= 0,
804 	}, {
805 		.name		= "basic-mmio-gpio-be",
806 		.driver_data	= BGPIOF_BIG_ENDIAN,
807 	},
808 	{ }
809 };
810 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
811 
812 static struct platform_driver bgpio_driver = {
813 	.driver = {
814 		.name = "basic-mmio-gpio",
815 		.of_match_table = of_match_ptr(bgpio_of_match),
816 	},
817 	.id_table = bgpio_id_table,
818 	.probe = bgpio_pdev_probe,
819 };
820 
821 module_platform_driver(bgpio_driver);
822 
823 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
824 
825 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
826 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
827 MODULE_LICENSE("GPL");
828