xref: /openbmc/qemu/hw/sparc/sun4m.c (revision 73a143b3)
1 /*
2  * QEMU Sun4m & Sun4d & Sun4c System Emulator
3  *
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu/datadir.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "net/net.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/irq.h"
52 #include "hw/or-irq.h"
53 #include "hw/loader.h"
54 #include "elf.h"
55 #include "trace.h"
56 #include "qom/object.h"
57 
58 /*
59  * Sun4m architecture was used in the following machines:
60  *
61  * SPARCserver 6xxMP/xx
62  * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
63  * SPARCclassic X (4/10)
64  * SPARCstation LX/ZX (4/30)
65  * SPARCstation Voyager
66  * SPARCstation 10/xx, SPARCserver 10/xx
67  * SPARCstation 5, SPARCserver 5
68  * SPARCstation 20/xx, SPARCserver 20
69  * SPARCstation 4
70  *
71  * See for example: http://www.sunhelp.org/faq/sunref1.html
72  */
73 
74 #define KERNEL_LOAD_ADDR     0x00004000
75 #define CMDLINE_ADDR         0x007ff000
76 #define INITRD_LOAD_ADDR     0x00800000
77 #define PROM_SIZE_MAX        (1 * MiB)
78 #define PROM_VADDR           0xffd00000
79 #define PROM_FILENAME        "openbios-sparc32"
80 #define CFG_ADDR             0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH   (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT  (FW_CFG_ARCH_LOCAL + 0x02)
84 
85 #define MAX_CPUS 16
86 #define MAX_PILS 16
87 #define MAX_VSIMMS 4
88 
89 #define ESCC_CLOCK 4915200
90 
91 struct sun4m_hwdef {
92     hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
93     hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
94     hwaddr serial_base, fd_base;
95     hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
96     hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97     hwaddr bpp_base, dbri_base, sx_base;
98     struct {
99         hwaddr reg_base, vram_base;
100     } vsimm[MAX_VSIMMS];
101     hwaddr ecc_base;
102     uint64_t max_mem;
103     uint32_t ecc_version;
104     uint32_t iommu_version;
105     uint16_t machine_id;
106     uint8_t nvram_machine_id;
107 };
108 
109 struct Sun4mMachineClass {
110     /*< private >*/
111     MachineClass parent_obj;
112     /*< public >*/
113     const struct sun4m_hwdef *hwdef;
114 };
115 typedef struct Sun4mMachineClass Sun4mMachineClass;
116 
117 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
DECLARE_CLASS_CHECKERS(Sun4mMachineClass,SUN4M_MACHINE,TYPE_SUN4M_MACHINE)118 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE)
119 
120 const char *fw_cfg_arch_key_name(uint16_t key)
121 {
122     static const struct {
123         uint16_t key;
124         const char *name;
125     } fw_cfg_arch_wellknown_keys[] = {
126         {FW_CFG_SUN4M_DEPTH, "depth"},
127         {FW_CFG_SUN4M_WIDTH, "width"},
128         {FW_CFG_SUN4M_HEIGHT, "height"},
129     };
130 
131     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
132         if (fw_cfg_arch_wellknown_keys[i].key == key) {
133             return fw_cfg_arch_wellknown_keys[i].name;
134         }
135     }
136     return NULL;
137 }
138 
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)139 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
140                             Error **errp)
141 {
142     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
143 }
144 
nvram_init(Nvram * nvram,uint8_t * macaddr,const char * cmdline,const char * boot_devices,ram_addr_t RAM_size,uint32_t kernel_size,int width,int height,int depth,int nvram_machine_id,const char * arch)145 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
146                        const char *cmdline, const char *boot_devices,
147                        ram_addr_t RAM_size, uint32_t kernel_size,
148                        int width, int height, int depth,
149                        int nvram_machine_id, const char *arch)
150 {
151     unsigned int i;
152     int sysp_end;
153     uint8_t image[0x1ff0];
154     NvramClass *k = NVRAM_GET_CLASS(nvram);
155 
156     memset(image, '\0', sizeof(image));
157 
158     /* OpenBIOS nvram variables partition */
159     sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
160 
161     /* Free space partition */
162     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
163 
164     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
165                     nvram_machine_id);
166 
167     for (i = 0; i < sizeof(image); i++) {
168         (k->write)(nvram, i, image[i]);
169     }
170 }
171 
cpu_kick_irq(SPARCCPU * cpu)172 static void cpu_kick_irq(SPARCCPU *cpu)
173 {
174     CPUSPARCState *env = &cpu->env;
175     CPUState *cs = CPU(cpu);
176 
177     cs->halted = 0;
178     cpu_check_irqs(env);
179     qemu_cpu_kick(cs);
180 }
181 
cpu_set_irq(void * opaque,int irq,int level)182 static void cpu_set_irq(void *opaque, int irq, int level)
183 {
184     SPARCCPU *cpu = opaque;
185     CPUSPARCState *env = &cpu->env;
186 
187     if (level) {
188         trace_sun4m_cpu_set_irq_raise(irq);
189         env->pil_in |= 1 << irq;
190         cpu_kick_irq(cpu);
191     } else {
192         trace_sun4m_cpu_set_irq_lower(irq);
193         env->pil_in &= ~(1 << irq);
194         cpu_check_irqs(env);
195     }
196 }
197 
dummy_cpu_set_irq(void * opaque,int irq,int level)198 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
199 {
200 }
201 
sun4m_cpu_reset(void * opaque)202 static void sun4m_cpu_reset(void *opaque)
203 {
204     SPARCCPU *cpu = opaque;
205     CPUState *cs = CPU(cpu);
206 
207     cpu_reset(cs);
208 }
209 
cpu_halt_signal(void * opaque,int irq,int level)210 static void cpu_halt_signal(void *opaque, int irq, int level)
211 {
212     if (level && current_cpu) {
213         cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
214     }
215 }
216 
translate_kernel_address(void * opaque,uint64_t addr)217 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
218 {
219     return addr - 0xf0000000ULL;
220 }
221 
sun4m_load_kernel(const char * kernel_filename,const char * initrd_filename,ram_addr_t RAM_size,uint32_t * initrd_size)222 static unsigned long sun4m_load_kernel(const char *kernel_filename,
223                                        const char *initrd_filename,
224                                        ram_addr_t RAM_size,
225                                        uint32_t *initrd_size)
226 {
227     int linux_boot;
228     unsigned int i;
229     long kernel_size;
230     uint8_t *ptr;
231 
232     linux_boot = (kernel_filename != NULL);
233 
234     kernel_size = 0;
235     if (linux_boot) {
236         int bswap_needed;
237 
238 #ifdef BSWAP_NEEDED
239         bswap_needed = 1;
240 #else
241         bswap_needed = 0;
242 #endif
243         kernel_size = load_elf(kernel_filename, NULL,
244                                translate_kernel_address, NULL,
245                                NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
246         if (kernel_size < 0)
247             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
248                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
249                                     TARGET_PAGE_SIZE);
250         if (kernel_size < 0)
251             kernel_size = load_image_targphys(kernel_filename,
252                                               KERNEL_LOAD_ADDR,
253                                               RAM_size - KERNEL_LOAD_ADDR);
254         if (kernel_size < 0) {
255             error_report("could not load kernel '%s'", kernel_filename);
256             exit(1);
257         }
258 
259         /* load initrd */
260         *initrd_size = 0;
261         if (initrd_filename) {
262             *initrd_size = load_image_targphys(initrd_filename,
263                                                INITRD_LOAD_ADDR,
264                                                RAM_size - INITRD_LOAD_ADDR);
265             if ((int)*initrd_size < 0) {
266                 error_report("could not load initial ram disk '%s'",
267                              initrd_filename);
268                 exit(1);
269             }
270         }
271         if (*initrd_size > 0) {
272             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
273                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
274                 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
275                     stl_p(ptr + 16, INITRD_LOAD_ADDR);
276                     stl_p(ptr + 20, *initrd_size);
277                     break;
278                 }
279             }
280         }
281     }
282     return kernel_size;
283 }
284 
iommu_init(hwaddr addr,uint32_t version,qemu_irq irq)285 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
286 {
287     DeviceState *dev;
288     SysBusDevice *s;
289 
290     dev = qdev_new(TYPE_SUN4M_IOMMU);
291     qdev_prop_set_uint32(dev, "version", version);
292     s = SYS_BUS_DEVICE(dev);
293     sysbus_realize_and_unref(s, &error_fatal);
294     sysbus_connect_irq(s, 0, irq);
295     sysbus_mmio_map(s, 0, addr);
296 
297     return s;
298 }
299 
sparc32_dma_init(hwaddr dma_base,hwaddr esp_base,qemu_irq espdma_irq,hwaddr le_base,qemu_irq ledma_irq,MACAddr * mac)300 static void *sparc32_dma_init(hwaddr dma_base,
301                               hwaddr esp_base, qemu_irq espdma_irq,
302                               hwaddr le_base, qemu_irq ledma_irq,
303                               MACAddr *mac)
304 {
305     DeviceState *dma;
306     ESPDMADeviceState *espdma;
307     LEDMADeviceState *ledma;
308     SysBusESPState *esp;
309     SysBusPCNetState *lance;
310     NICInfo *nd = qemu_find_nic_info("lance", true, NULL);
311 
312     dma = qdev_new(TYPE_SPARC32_DMA);
313     espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
314                                    OBJECT(dma), "espdma"));
315 
316     esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
317 
318     ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
319                                  OBJECT(dma), "ledma"));
320 
321     lance = SYSBUS_PCNET(object_resolve_path_component(
322                          OBJECT(ledma), "lance"));
323 
324     if (nd) {
325         qdev_set_nic_properties(DEVICE(lance), nd);
326         memcpy(mac->a, nd->macaddr.a, sizeof(mac->a));
327     } else {
328         qemu_macaddr_default_if_unset(mac);
329         qdev_prop_set_macaddr(DEVICE(lance), "mac", mac->a);
330     }
331 
332     sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
333 
334     sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
335 
336     sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
337 
338     sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
339 
340     sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
341     scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
342 
343     sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
344 
345     return dma;
346 }
347 
slavio_intctl_init(hwaddr addr,hwaddr addrg,qemu_irq ** parent_irq)348 static DeviceState *slavio_intctl_init(hwaddr addr,
349                                        hwaddr addrg,
350                                        qemu_irq **parent_irq)
351 {
352     DeviceState *dev;
353     SysBusDevice *s;
354     unsigned int i, j;
355 
356     dev = qdev_new("slavio_intctl");
357 
358     s = SYS_BUS_DEVICE(dev);
359     sysbus_realize_and_unref(s, &error_fatal);
360 
361     for (i = 0; i < MAX_CPUS; i++) {
362         for (j = 0; j < MAX_PILS; j++) {
363             sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
364         }
365     }
366     sysbus_mmio_map(s, 0, addrg);
367     for (i = 0; i < MAX_CPUS; i++) {
368         sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
369     }
370 
371     return dev;
372 }
373 
374 #define SYS_TIMER_OFFSET      0x10000ULL
375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
376 
slavio_timer_init_all(hwaddr addr,qemu_irq master_irq,qemu_irq * cpu_irqs,unsigned int num_cpus)377 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
378                                   qemu_irq *cpu_irqs, unsigned int num_cpus)
379 {
380     DeviceState *dev;
381     SysBusDevice *s;
382     unsigned int i;
383 
384     dev = qdev_new("slavio_timer");
385     qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
386     s = SYS_BUS_DEVICE(dev);
387     sysbus_realize_and_unref(s, &error_fatal);
388     sysbus_connect_irq(s, 0, master_irq);
389     sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
390 
391     for (i = 0; i < MAX_CPUS; i++) {
392         sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
393         sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
394     }
395 }
396 
397 static qemu_irq  slavio_system_powerdown;
398 
slavio_powerdown_req(Notifier * n,void * opaque)399 static void slavio_powerdown_req(Notifier *n, void *opaque)
400 {
401     qemu_irq_raise(slavio_system_powerdown);
402 }
403 
404 static Notifier slavio_system_powerdown_notifier = {
405     .notify = slavio_powerdown_req
406 };
407 
408 #define MISC_LEDS 0x01600000
409 #define MISC_CFG  0x01800000
410 #define MISC_DIAG 0x01a00000
411 #define MISC_MDM  0x01b00000
412 #define MISC_SYS  0x01f00000
413 
slavio_misc_init(hwaddr base,hwaddr aux1_base,hwaddr aux2_base,qemu_irq irq,qemu_irq fdc_tc)414 static void slavio_misc_init(hwaddr base,
415                              hwaddr aux1_base,
416                              hwaddr aux2_base, qemu_irq irq,
417                              qemu_irq fdc_tc)
418 {
419     DeviceState *dev;
420     SysBusDevice *s;
421 
422     dev = qdev_new("slavio_misc");
423     s = SYS_BUS_DEVICE(dev);
424     sysbus_realize_and_unref(s, &error_fatal);
425     if (base) {
426         /* 8 bit registers */
427         /* Slavio control */
428         sysbus_mmio_map(s, 0, base + MISC_CFG);
429         /* Diagnostics */
430         sysbus_mmio_map(s, 1, base + MISC_DIAG);
431         /* Modem control */
432         sysbus_mmio_map(s, 2, base + MISC_MDM);
433         /* 16 bit registers */
434         /* ss600mp diag LEDs */
435         sysbus_mmio_map(s, 3, base + MISC_LEDS);
436         /* 32 bit registers */
437         /* System control */
438         sysbus_mmio_map(s, 4, base + MISC_SYS);
439     }
440     if (aux1_base) {
441         /* AUX 1 (Misc System Functions) */
442         sysbus_mmio_map(s, 5, aux1_base);
443     }
444     if (aux2_base) {
445         /* AUX 2 (Software Powerdown Control) */
446         sysbus_mmio_map(s, 6, aux2_base);
447     }
448     sysbus_connect_irq(s, 0, irq);
449     sysbus_connect_irq(s, 1, fdc_tc);
450     slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
451     qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
452 }
453 
ecc_init(hwaddr base,qemu_irq irq,uint32_t version)454 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
455 {
456     DeviceState *dev;
457     SysBusDevice *s;
458 
459     dev = qdev_new("eccmemctl");
460     qdev_prop_set_uint32(dev, "version", version);
461     s = SYS_BUS_DEVICE(dev);
462     sysbus_realize_and_unref(s, &error_fatal);
463     sysbus_connect_irq(s, 0, irq);
464     sysbus_mmio_map(s, 0, base);
465     if (version == 0) { // SS-600MP only
466         sysbus_mmio_map(s, 1, base + 0x1000);
467     }
468 }
469 
apc_init(hwaddr power_base,qemu_irq cpu_halt)470 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
471 {
472     DeviceState *dev;
473     SysBusDevice *s;
474 
475     dev = qdev_new("apc");
476     s = SYS_BUS_DEVICE(dev);
477     sysbus_realize_and_unref(s, &error_fatal);
478     /* Power management (APC) XXX: not a Slavio device */
479     sysbus_mmio_map(s, 0, power_base);
480     sysbus_connect_irq(s, 0, cpu_halt);
481 }
482 
tcx_init(hwaddr addr,qemu_irq irq,int vram_size,int width,int height,int depth)483 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
484                      int height, int depth)
485 {
486     DeviceState *dev;
487     SysBusDevice *s;
488 
489     dev = qdev_new("sun-tcx");
490     qdev_prop_set_uint32(dev, "vram_size", vram_size);
491     qdev_prop_set_uint16(dev, "width", width);
492     qdev_prop_set_uint16(dev, "height", height);
493     qdev_prop_set_uint16(dev, "depth", depth);
494     s = SYS_BUS_DEVICE(dev);
495     sysbus_realize_and_unref(s, &error_fatal);
496 
497     /* 10/ROM : FCode ROM */
498     sysbus_mmio_map(s, 0, addr);
499     /* 2/STIP : Stipple */
500     sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
501     /* 3/BLIT : Blitter */
502     sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
503     /* 5/RSTIP : Raw Stipple */
504     sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
505     /* 6/RBLIT : Raw Blitter */
506     sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
507     /* 7/TEC : Transform Engine */
508     sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
509     /* 8/CMAP  : DAC */
510     sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
511     /* 9/THC : */
512     if (depth == 8) {
513         sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
514     } else {
515         sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
516     }
517     /* 11/DHC : */
518     sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
519     /* 12/ALT : */
520     sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
521     /* 0/DFB8 : 8-bit plane */
522     sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
523     /* 1/DFB24 : 24bit plane */
524     sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
525     /* 4/RDFB32: Raw framebuffer. Control plane */
526     sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
527     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
528     if (depth == 8) {
529         sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
530     }
531 
532     sysbus_connect_irq(s, 0, irq);
533 }
534 
cg3_init(hwaddr addr,qemu_irq irq,int vram_size,int width,int height,int depth)535 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
536                      int height, int depth)
537 {
538     DeviceState *dev;
539     SysBusDevice *s;
540 
541     dev = qdev_new("cgthree");
542     qdev_prop_set_uint32(dev, "vram-size", vram_size);
543     qdev_prop_set_uint16(dev, "width", width);
544     qdev_prop_set_uint16(dev, "height", height);
545     qdev_prop_set_uint16(dev, "depth", depth);
546     s = SYS_BUS_DEVICE(dev);
547     sysbus_realize_and_unref(s, &error_fatal);
548 
549     /* FCode ROM */
550     sysbus_mmio_map(s, 0, addr);
551     /* DAC */
552     sysbus_mmio_map(s, 1, addr + 0x400000ULL);
553     /* 8-bit plane */
554     sysbus_mmio_map(s, 2, addr + 0x800000ULL);
555 
556     sysbus_connect_irq(s, 0, irq);
557 }
558 
559 /* NCR89C100/MACIO Internal ID register */
560 
561 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
562 
563 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
564 
idreg_init(hwaddr addr)565 static void idreg_init(hwaddr addr)
566 {
567     DeviceState *dev;
568     SysBusDevice *s;
569 
570     dev = qdev_new(TYPE_MACIO_ID_REGISTER);
571     s = SYS_BUS_DEVICE(dev);
572     sysbus_realize_and_unref(s, &error_fatal);
573 
574     sysbus_mmio_map(s, 0, addr);
575     address_space_write_rom(&address_space_memory, addr,
576                             MEMTXATTRS_UNSPECIFIED,
577                             idreg_data, sizeof(idreg_data));
578 }
579 
580 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
581 
582 struct IDRegState {
583     SysBusDevice parent_obj;
584 
585     MemoryRegion mem;
586 };
587 
idreg_realize(DeviceState * ds,Error ** errp)588 static void idreg_realize(DeviceState *ds, Error **errp)
589 {
590     IDRegState *s = MACIO_ID_REGISTER(ds);
591     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
592 
593     if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
594                                           sizeof(idreg_data), errp)) {
595         return;
596     }
597 
598     vmstate_register_ram_global(&s->mem);
599     memory_region_set_readonly(&s->mem, true);
600     sysbus_init_mmio(dev, &s->mem);
601 }
602 
idreg_class_init(ObjectClass * oc,void * data)603 static void idreg_class_init(ObjectClass *oc, void *data)
604 {
605     DeviceClass *dc = DEVICE_CLASS(oc);
606 
607     dc->realize = idreg_realize;
608 }
609 
610 static const TypeInfo idreg_info = {
611     .name          = TYPE_MACIO_ID_REGISTER,
612     .parent        = TYPE_SYS_BUS_DEVICE,
613     .instance_size = sizeof(IDRegState),
614     .class_init    = idreg_class_init,
615 };
616 
617 #define TYPE_TCX_AFX "tcx_afx"
618 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
619 
620 struct AFXState {
621     SysBusDevice parent_obj;
622 
623     MemoryRegion mem;
624 };
625 
626 /* SS-5 TCX AFX register */
afx_init(hwaddr addr)627 static void afx_init(hwaddr addr)
628 {
629     DeviceState *dev;
630     SysBusDevice *s;
631 
632     dev = qdev_new(TYPE_TCX_AFX);
633     s = SYS_BUS_DEVICE(dev);
634     sysbus_realize_and_unref(s, &error_fatal);
635 
636     sysbus_mmio_map(s, 0, addr);
637 }
638 
afx_realize(DeviceState * ds,Error ** errp)639 static void afx_realize(DeviceState *ds, Error **errp)
640 {
641     AFXState *s = TCX_AFX(ds);
642     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
643 
644     if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx",
645                                           4, errp)) {
646         return;
647     }
648 
649     vmstate_register_ram_global(&s->mem);
650     sysbus_init_mmio(dev, &s->mem);
651 }
652 
afx_class_init(ObjectClass * oc,void * data)653 static void afx_class_init(ObjectClass *oc, void *data)
654 {
655     DeviceClass *dc = DEVICE_CLASS(oc);
656 
657     dc->realize = afx_realize;
658 }
659 
660 static const TypeInfo afx_info = {
661     .name          = TYPE_TCX_AFX,
662     .parent        = TYPE_SYS_BUS_DEVICE,
663     .instance_size = sizeof(AFXState),
664     .class_init    = afx_class_init,
665 };
666 
667 #define TYPE_OPENPROM "openprom"
668 typedef struct PROMState PROMState;
669 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
670                          TYPE_OPENPROM)
671 
672 struct PROMState {
673     SysBusDevice parent_obj;
674 
675     MemoryRegion prom;
676 };
677 
678 /* Boot PROM (OpenBIOS) */
translate_prom_address(void * opaque,uint64_t addr)679 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
680 {
681     hwaddr *base_addr = (hwaddr *)opaque;
682     return addr + *base_addr - PROM_VADDR;
683 }
684 
prom_init(hwaddr addr,const char * bios_name)685 static void prom_init(hwaddr addr, const char *bios_name)
686 {
687     DeviceState *dev;
688     SysBusDevice *s;
689     char *filename;
690     int ret;
691 
692     dev = qdev_new(TYPE_OPENPROM);
693     s = SYS_BUS_DEVICE(dev);
694     sysbus_realize_and_unref(s, &error_fatal);
695 
696     sysbus_mmio_map(s, 0, addr);
697 
698     /* load boot prom */
699     if (bios_name == NULL) {
700         bios_name = PROM_FILENAME;
701     }
702     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
703     if (filename) {
704         ret = load_elf(filename, NULL,
705                        translate_prom_address, &addr, NULL,
706                        NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
707         if (ret < 0 || ret > PROM_SIZE_MAX) {
708             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
709         }
710         g_free(filename);
711     } else {
712         ret = -1;
713     }
714     if (ret < 0 || ret > PROM_SIZE_MAX) {
715         error_report("could not load prom '%s'", bios_name);
716         exit(1);
717     }
718 }
719 
prom_realize(DeviceState * ds,Error ** errp)720 static void prom_realize(DeviceState *ds, Error **errp)
721 {
722     PROMState *s = OPENPROM(ds);
723     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
724 
725     if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
726                                           PROM_SIZE_MAX, errp)) {
727         return;
728     }
729 
730     vmstate_register_ram_global(&s->prom);
731     memory_region_set_readonly(&s->prom, true);
732     sysbus_init_mmio(dev, &s->prom);
733 }
734 
735 static Property prom_properties[] = {
736     {/* end of property list */},
737 };
738 
prom_class_init(ObjectClass * klass,void * data)739 static void prom_class_init(ObjectClass *klass, void *data)
740 {
741     DeviceClass *dc = DEVICE_CLASS(klass);
742 
743     device_class_set_props(dc, prom_properties);
744     dc->realize = prom_realize;
745 }
746 
747 static const TypeInfo prom_info = {
748     .name          = TYPE_OPENPROM,
749     .parent        = TYPE_SYS_BUS_DEVICE,
750     .instance_size = sizeof(PROMState),
751     .class_init    = prom_class_init,
752 };
753 
754 #define TYPE_SUN4M_MEMORY "memory"
755 typedef struct RamDevice RamDevice;
756 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
757                          TYPE_SUN4M_MEMORY)
758 
759 struct RamDevice {
760     SysBusDevice parent_obj;
761     HostMemoryBackend *memdev;
762 };
763 
764 /* System RAM */
ram_realize(DeviceState * dev,Error ** errp)765 static void ram_realize(DeviceState *dev, Error **errp)
766 {
767     RamDevice *d = SUN4M_RAM(dev);
768     MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
769 
770     sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
771 }
772 
ram_initfn(Object * obj)773 static void ram_initfn(Object *obj)
774 {
775     RamDevice *d = SUN4M_RAM(obj);
776     object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
777                              (Object **)&d->memdev,
778                              object_property_allow_set_link,
779                              OBJ_PROP_LINK_STRONG);
780     object_property_set_description(obj, "memdev", "Set RAM backend"
781                                     "Valid value is ID of a hostmem backend");
782 }
783 
ram_class_init(ObjectClass * klass,void * data)784 static void ram_class_init(ObjectClass *klass, void *data)
785 {
786     DeviceClass *dc = DEVICE_CLASS(klass);
787 
788     dc->realize = ram_realize;
789 }
790 
791 static const TypeInfo ram_info = {
792     .name          = TYPE_SUN4M_MEMORY,
793     .parent        = TYPE_SYS_BUS_DEVICE,
794     .instance_size = sizeof(RamDevice),
795     .instance_init = ram_initfn,
796     .class_init    = ram_class_init,
797 };
798 
cpu_devinit(const char * cpu_type,unsigned int id,uint64_t prom_addr,qemu_irq ** cpu_irqs)799 static void cpu_devinit(const char *cpu_type, unsigned int id,
800                         uint64_t prom_addr, qemu_irq **cpu_irqs)
801 {
802     SPARCCPU *cpu;
803     CPUSPARCState *env;
804 
805     cpu = SPARC_CPU(object_new(cpu_type));
806     env = &cpu->env;
807 
808     qemu_register_reset(sun4m_cpu_reset, cpu);
809     object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
810                              &error_abort);
811     qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
812     cpu_sparc_set_id(env, id);
813     *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
814     env->prom_addr = prom_addr;
815 }
816 
dummy_fdc_tc(void * opaque,int irq,int level)817 static void dummy_fdc_tc(void *opaque, int irq, int level)
818 {
819 }
820 
sun4m_hw_init(MachineState * machine)821 static void sun4m_hw_init(MachineState *machine)
822 {
823     const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef;
824     DeviceState *slavio_intctl;
825     unsigned int i;
826     Nvram *nvram;
827     qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
828     qemu_irq fdc_tc;
829     unsigned long kernel_size;
830     uint32_t initrd_size;
831     DriveInfo *fd[MAX_FD];
832     FWCfgState *fw_cfg;
833     DeviceState *dev, *ms_kb_orgate, *serial_orgate;
834     SysBusDevice *s;
835     unsigned int smp_cpus = machine->smp.cpus;
836     unsigned int max_cpus = machine->smp.max_cpus;
837     HostMemoryBackend *ram_memdev = machine->memdev;
838     MACAddr hostid;
839 
840     if (machine->ram_size > hwdef->max_mem) {
841         error_report("Too much memory for this machine: %" PRId64 ","
842                      " maximum %" PRId64,
843                      machine->ram_size / MiB, hwdef->max_mem / MiB);
844         exit(1);
845     }
846 
847     /* init CPUs */
848     for(i = 0; i < smp_cpus; i++) {
849         cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
850     }
851 
852     for (i = smp_cpus; i < MAX_CPUS; i++)
853         cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
854 
855     /* Create and map RAM frontend */
856     dev = qdev_new("memory");
857     object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal);
858     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
859     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
860 
861     /* models without ECC don't trap when missing ram is accessed */
862     if (!hwdef->ecc_base) {
863         empty_slot_init("ecc", machine->ram_size,
864                         hwdef->max_mem - machine->ram_size);
865     }
866 
867     prom_init(hwdef->slavio_base, machine->firmware);
868 
869     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
870                                        hwdef->intctl_base + 0x10000ULL,
871                                        cpu_irqs);
872 
873     for (i = 0; i < 32; i++) {
874         slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
875     }
876     for (i = 0; i < MAX_CPUS; i++) {
877         slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
878     }
879 
880     if (hwdef->idreg_base) {
881         idreg_init(hwdef->idreg_base);
882     }
883 
884     if (hwdef->afx_base) {
885         afx_init(hwdef->afx_base);
886     }
887 
888     iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
889 
890     if (hwdef->iommu_pad_base) {
891         /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
892            Software shouldn't use aliased addresses, neither should it crash
893            when does. Using empty_slot instead of aliasing can help with
894            debugging such accesses */
895         empty_slot_init("iommu.alias",
896                         hwdef->iommu_pad_base, hwdef->iommu_pad_len);
897     }
898 
899     sparc32_dma_init(hwdef->dma_base,
900                      hwdef->esp_base, slavio_irq[18],
901                      hwdef->le_base, slavio_irq[16], &hostid);
902 
903     if (graphic_depth != 8 && graphic_depth != 24) {
904         error_report("Unsupported depth: %d", graphic_depth);
905         exit (1);
906     }
907     if (vga_interface_type != VGA_NONE) {
908         if (vga_interface_type == VGA_CG3) {
909             if (graphic_depth != 8) {
910                 error_report("Unsupported depth: %d", graphic_depth);
911                 exit(1);
912             }
913 
914             if (!(graphic_width == 1024 && graphic_height == 768) &&
915                 !(graphic_width == 1152 && graphic_height == 900)) {
916                 error_report("Unsupported resolution: %d x %d", graphic_width,
917                              graphic_height);
918                 exit(1);
919             }
920 
921             /* sbus irq 5 */
922             cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
923                      graphic_width, graphic_height, graphic_depth);
924             vga_interface_created = true;
925         } else {
926             /* If no display specified, default to TCX */
927             if (graphic_depth != 8 && graphic_depth != 24) {
928                 error_report("Unsupported depth: %d", graphic_depth);
929                 exit(1);
930             }
931 
932             if (!(graphic_width == 1024 && graphic_height == 768)) {
933                 error_report("Unsupported resolution: %d x %d",
934                              graphic_width, graphic_height);
935                 exit(1);
936             }
937 
938             tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
939                      graphic_width, graphic_height, graphic_depth);
940             vga_interface_created = true;
941         }
942     }
943 
944     for (i = 0; i < MAX_VSIMMS; i++) {
945         /* vsimm registers probed by OBP */
946         if (hwdef->vsimm[i].reg_base) {
947             char *name = g_strdup_printf("vsimm[%d]", i);
948             empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
949             g_free(name);
950         }
951     }
952 
953     if (hwdef->sx_base) {
954         create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000);
955     }
956 
957     dev = qdev_new("sysbus-m48t08");
958     qdev_prop_set_int32(dev, "base-year", 1968);
959     s = SYS_BUS_DEVICE(dev);
960     sysbus_realize_and_unref(s, &error_fatal);
961     sysbus_connect_irq(s, 0, slavio_irq[0]);
962     sysbus_mmio_map(s, 0, hwdef->nvram_base);
963     nvram = NVRAM(dev);
964 
965     slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
966 
967     /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
968        Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
969     dev = qdev_new(TYPE_ESCC);
970     qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
971     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
972     qdev_prop_set_uint32(dev, "it_shift", 1);
973     qdev_prop_set_chr(dev, "chrB", NULL);
974     qdev_prop_set_chr(dev, "chrA", NULL);
975     qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
976     qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
977     s = SYS_BUS_DEVICE(dev);
978     sysbus_realize_and_unref(s, &error_fatal);
979     sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
980 
981     /* Logically OR both its IRQs together */
982     ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ));
983     object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal);
984     qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal);
985     sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0));
986     sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1));
987     qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]);
988 
989     dev = qdev_new(TYPE_ESCC);
990     qdev_prop_set_uint32(dev, "disabled", 0);
991     qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
992     qdev_prop_set_uint32(dev, "it_shift", 1);
993     qdev_prop_set_chr(dev, "chrB", serial_hd(1));
994     qdev_prop_set_chr(dev, "chrA", serial_hd(0));
995     qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
996     qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
997 
998     s = SYS_BUS_DEVICE(dev);
999     sysbus_realize_and_unref(s, &error_fatal);
1000     sysbus_mmio_map(s, 0, hwdef->serial_base);
1001 
1002     /* Logically OR both its IRQs together */
1003     serial_orgate = DEVICE(object_new(TYPE_OR_IRQ));
1004     object_property_set_int(OBJECT(serial_orgate), "num-lines", 2,
1005                             &error_fatal);
1006     qdev_realize_and_unref(serial_orgate, NULL, &error_fatal);
1007     sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0));
1008     sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1));
1009     qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]);
1010 
1011     if (hwdef->apc_base) {
1012         apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1013     }
1014 
1015     if (hwdef->fd_base) {
1016         /* there is zero or one floppy drive */
1017         memset(fd, 0, sizeof(fd));
1018         fd[0] = drive_get(IF_FLOPPY, 0, 0);
1019         sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1020                           &fdc_tc);
1021     } else {
1022         fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1023     }
1024 
1025     slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1026                      slavio_irq[30], fdc_tc);
1027 
1028     if (hwdef->cs_base) {
1029         sysbus_create_simple("sun-CS4231", hwdef->cs_base,
1030                              slavio_irq[5]);
1031     }
1032 
1033     if (hwdef->dbri_base) {
1034         /* ISDN chip with attached CS4215 audio codec */
1035         /* prom space */
1036         create_unimplemented_device("sun-DBRI.prom",
1037                                     hwdef->dbri_base + 0x1000, 0x30);
1038         /* reg space */
1039         create_unimplemented_device("sun-DBRI",
1040                                     hwdef->dbri_base + 0x10000, 0x100);
1041     }
1042 
1043     if (hwdef->bpp_base) {
1044         /* parallel port */
1045         create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20);
1046     }
1047 
1048     initrd_size = 0;
1049     kernel_size = sun4m_load_kernel(machine->kernel_filename,
1050                                     machine->initrd_filename,
1051                                     machine->ram_size, &initrd_size);
1052 
1053     nvram_init(nvram, hostid.a, machine->kernel_cmdline,
1054                machine->boot_config.order, machine->ram_size, kernel_size,
1055                graphic_width, graphic_height, graphic_depth,
1056                hwdef->nvram_machine_id, "Sun4m");
1057 
1058     if (hwdef->ecc_base)
1059         ecc_init(hwdef->ecc_base, slavio_irq[28],
1060                  hwdef->ecc_version);
1061 
1062     dev = qdev_new(TYPE_FW_CFG_MEM);
1063     fw_cfg = FW_CFG(dev);
1064     qdev_prop_set_uint32(dev, "data_width", 1);
1065     qdev_prop_set_bit(dev, "dma_enabled", false);
1066     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1067                               OBJECT(fw_cfg));
1068     s = SYS_BUS_DEVICE(dev);
1069     sysbus_realize_and_unref(s, &error_fatal);
1070     sysbus_mmio_map(s, 0, CFG_ADDR);
1071     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1072 
1073     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1074     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1075     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1076     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1077     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1078     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1079     fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1080     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1081     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1082     if (machine->kernel_cmdline) {
1083         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1084         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1085                          machine->kernel_cmdline);
1086         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1087         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1088                        strlen(machine->kernel_cmdline) + 1);
1089     } else {
1090         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1091         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1092     }
1093     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1094     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1095     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
1096     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1097 }
1098 
1099 enum {
1100     ss5_id = 32,
1101     vger_id,
1102     lx_id,
1103     ss4_id,
1104     scls_id,
1105     sbook_id,
1106     ss10_id = 64,
1107     ss20_id,
1108     ss600mp_id,
1109 };
1110 
sun4m_machine_class_init(ObjectClass * oc,void * data)1111 static void sun4m_machine_class_init(ObjectClass *oc, void *data)
1112 {
1113     MachineClass *mc = MACHINE_CLASS(oc);
1114 
1115     mc->init = sun4m_hw_init;
1116     mc->block_default_type = IF_SCSI;
1117     mc->default_boot_order = "c";
1118     mc->default_display = "tcx";
1119     mc->default_ram_id = "sun4m.ram";
1120 }
1121 
ss5_class_init(ObjectClass * oc,void * data)1122 static void ss5_class_init(ObjectClass *oc, void *data)
1123 {
1124     MachineClass *mc = MACHINE_CLASS(oc);
1125     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1126     static const struct sun4m_hwdef ss5_hwdef = {
1127         .iommu_base   = 0x10000000,
1128         .iommu_pad_base = 0x10004000,
1129         .iommu_pad_len  = 0x0fffb000,
1130         .tcx_base     = 0x50000000,
1131         .cs_base      = 0x6c000000,
1132         .slavio_base  = 0x70000000,
1133         .ms_kb_base   = 0x71000000,
1134         .serial_base  = 0x71100000,
1135         .nvram_base   = 0x71200000,
1136         .fd_base      = 0x71400000,
1137         .counter_base = 0x71d00000,
1138         .intctl_base  = 0x71e00000,
1139         .idreg_base   = 0x78000000,
1140         .dma_base     = 0x78400000,
1141         .esp_base     = 0x78800000,
1142         .le_base      = 0x78c00000,
1143         .apc_base     = 0x6a000000,
1144         .afx_base     = 0x6e000000,
1145         .aux1_base    = 0x71900000,
1146         .aux2_base    = 0x71910000,
1147         .nvram_machine_id = 0x80,
1148         .machine_id = ss5_id,
1149         .iommu_version = 0x05000000,
1150         .max_mem = 0x10000000,
1151     };
1152 
1153     mc->desc = "Sun4m platform, SPARCstation 5";
1154     mc->is_default = true;
1155     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1156     smc->hwdef = &ss5_hwdef;
1157 }
1158 
ss10_class_init(ObjectClass * oc,void * data)1159 static void ss10_class_init(ObjectClass *oc, void *data)
1160 {
1161     MachineClass *mc = MACHINE_CLASS(oc);
1162     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1163     static const struct sun4m_hwdef ss10_hwdef = {
1164         .iommu_base   = 0xfe0000000ULL,
1165         .tcx_base     = 0xe20000000ULL,
1166         .slavio_base  = 0xff0000000ULL,
1167         .ms_kb_base   = 0xff1000000ULL,
1168         .serial_base  = 0xff1100000ULL,
1169         .nvram_base   = 0xff1200000ULL,
1170         .fd_base      = 0xff1700000ULL,
1171         .counter_base = 0xff1300000ULL,
1172         .intctl_base  = 0xff1400000ULL,
1173         .idreg_base   = 0xef0000000ULL,
1174         .dma_base     = 0xef0400000ULL,
1175         .esp_base     = 0xef0800000ULL,
1176         .le_base      = 0xef0c00000ULL,
1177         .apc_base     = 0xefa000000ULL, /* XXX should not exist */
1178         .aux1_base    = 0xff1800000ULL,
1179         .aux2_base    = 0xff1a01000ULL,
1180         .ecc_base     = 0xf00000000ULL,
1181         .ecc_version  = 0x10000000, /* version 0, implementation 1 */
1182         .nvram_machine_id = 0x72,
1183         .machine_id = ss10_id,
1184         .iommu_version = 0x03000000,
1185         .max_mem = 0xf00000000ULL,
1186     };
1187 
1188     mc->desc = "Sun4m platform, SPARCstation 10";
1189     mc->max_cpus = 4;
1190     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1191     smc->hwdef = &ss10_hwdef;
1192 }
1193 
ss600mp_class_init(ObjectClass * oc,void * data)1194 static void ss600mp_class_init(ObjectClass *oc, void *data)
1195 {
1196     MachineClass *mc = MACHINE_CLASS(oc);
1197     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1198     static const struct sun4m_hwdef ss600mp_hwdef = {
1199         .iommu_base   = 0xfe0000000ULL,
1200         .tcx_base     = 0xe20000000ULL,
1201         .slavio_base  = 0xff0000000ULL,
1202         .ms_kb_base   = 0xff1000000ULL,
1203         .serial_base  = 0xff1100000ULL,
1204         .nvram_base   = 0xff1200000ULL,
1205         .counter_base = 0xff1300000ULL,
1206         .intctl_base  = 0xff1400000ULL,
1207         .dma_base     = 0xef0081000ULL,
1208         .esp_base     = 0xef0080000ULL,
1209         .le_base      = 0xef0060000ULL,
1210         .apc_base     = 0xefa000000ULL, /* XXX should not exist */
1211         .aux1_base    = 0xff1800000ULL,
1212         .aux2_base    = 0xff1a01000ULL, /* XXX should not exist */
1213         .ecc_base     = 0xf00000000ULL,
1214         .ecc_version  = 0x00000000, /* version 0, implementation 0 */
1215         .nvram_machine_id = 0x71,
1216         .machine_id = ss600mp_id,
1217         .iommu_version = 0x01000000,
1218         .max_mem = 0xf00000000ULL,
1219     };
1220 
1221     mc->desc = "Sun4m platform, SPARCserver 600MP";
1222     mc->max_cpus = 4;
1223     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1224     smc->hwdef = &ss600mp_hwdef;
1225 }
1226 
ss20_class_init(ObjectClass * oc,void * data)1227 static void ss20_class_init(ObjectClass *oc, void *data)
1228 {
1229     MachineClass *mc = MACHINE_CLASS(oc);
1230     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1231     static const struct sun4m_hwdef ss20_hwdef = {
1232         .iommu_base   = 0xfe0000000ULL,
1233         .tcx_base     = 0xe20000000ULL,
1234         .slavio_base  = 0xff0000000ULL,
1235         .ms_kb_base   = 0xff1000000ULL,
1236         .serial_base  = 0xff1100000ULL,
1237         .nvram_base   = 0xff1200000ULL,
1238         .fd_base      = 0xff1700000ULL,
1239         .counter_base = 0xff1300000ULL,
1240         .intctl_base  = 0xff1400000ULL,
1241         .idreg_base   = 0xef0000000ULL,
1242         .dma_base     = 0xef0400000ULL,
1243         .esp_base     = 0xef0800000ULL,
1244         .le_base      = 0xef0c00000ULL,
1245         .bpp_base     = 0xef4800000ULL,
1246         .apc_base     = 0xefa000000ULL, /* XXX should not exist */
1247         .aux1_base    = 0xff1800000ULL,
1248         .aux2_base    = 0xff1a01000ULL,
1249         .dbri_base    = 0xee0000000ULL,
1250         .sx_base      = 0xf80000000ULL,
1251         .vsimm        = {
1252             {
1253                 .reg_base  = 0x9c000000ULL,
1254                 .vram_base = 0xfc000000ULL
1255             }, {
1256                 .reg_base  = 0x90000000ULL,
1257                 .vram_base = 0xf0000000ULL
1258             }, {
1259                 .reg_base  = 0x94000000ULL
1260             }, {
1261                 .reg_base  = 0x98000000ULL
1262             }
1263         },
1264         .ecc_base     = 0xf00000000ULL,
1265         .ecc_version  = 0x20000000, /* version 0, implementation 2 */
1266         .nvram_machine_id = 0x72,
1267         .machine_id = ss20_id,
1268         .iommu_version = 0x13000000,
1269         .max_mem = 0xf00000000ULL,
1270     };
1271 
1272     mc->desc = "Sun4m platform, SPARCstation 20";
1273     mc->max_cpus = 4;
1274     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1275     smc->hwdef = &ss20_hwdef;
1276 }
1277 
voyager_class_init(ObjectClass * oc,void * data)1278 static void voyager_class_init(ObjectClass *oc, void *data)
1279 {
1280     MachineClass *mc = MACHINE_CLASS(oc);
1281     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1282     static const struct sun4m_hwdef voyager_hwdef = {
1283         .iommu_base   = 0x10000000,
1284         .tcx_base     = 0x50000000,
1285         .slavio_base  = 0x70000000,
1286         .ms_kb_base   = 0x71000000,
1287         .serial_base  = 0x71100000,
1288         .nvram_base   = 0x71200000,
1289         .fd_base      = 0x71400000,
1290         .counter_base = 0x71d00000,
1291         .intctl_base  = 0x71e00000,
1292         .idreg_base   = 0x78000000,
1293         .dma_base     = 0x78400000,
1294         .esp_base     = 0x78800000,
1295         .le_base      = 0x78c00000,
1296         .apc_base     = 0x71300000, /* pmc */
1297         .aux1_base    = 0x71900000,
1298         .aux2_base    = 0x71910000,
1299         .nvram_machine_id = 0x80,
1300         .machine_id = vger_id,
1301         .iommu_version = 0x05000000,
1302         .max_mem = 0x10000000,
1303     };
1304 
1305     mc->desc = "Sun4m platform, SPARCstation Voyager";
1306     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1307     smc->hwdef = &voyager_hwdef;
1308 }
1309 
ss_lx_class_init(ObjectClass * oc,void * data)1310 static void ss_lx_class_init(ObjectClass *oc, void *data)
1311 {
1312     MachineClass *mc = MACHINE_CLASS(oc);
1313     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1314     static const struct sun4m_hwdef ss_lx_hwdef = {
1315         .iommu_base   = 0x10000000,
1316         .iommu_pad_base = 0x10004000,
1317         .iommu_pad_len  = 0x0fffb000,
1318         .tcx_base     = 0x50000000,
1319         .slavio_base  = 0x70000000,
1320         .ms_kb_base   = 0x71000000,
1321         .serial_base  = 0x71100000,
1322         .nvram_base   = 0x71200000,
1323         .fd_base      = 0x71400000,
1324         .counter_base = 0x71d00000,
1325         .intctl_base  = 0x71e00000,
1326         .idreg_base   = 0x78000000,
1327         .dma_base     = 0x78400000,
1328         .esp_base     = 0x78800000,
1329         .le_base      = 0x78c00000,
1330         .aux1_base    = 0x71900000,
1331         .aux2_base    = 0x71910000,
1332         .nvram_machine_id = 0x80,
1333         .machine_id = lx_id,
1334         .iommu_version = 0x04000000,
1335         .max_mem = 0x10000000,
1336     };
1337 
1338     mc->desc = "Sun4m platform, SPARCstation LX";
1339     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1340     smc->hwdef = &ss_lx_hwdef;
1341 }
1342 
ss4_class_init(ObjectClass * oc,void * data)1343 static void ss4_class_init(ObjectClass *oc, void *data)
1344 {
1345     MachineClass *mc = MACHINE_CLASS(oc);
1346     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1347     static const struct sun4m_hwdef ss4_hwdef = {
1348         .iommu_base   = 0x10000000,
1349         .tcx_base     = 0x50000000,
1350         .cs_base      = 0x6c000000,
1351         .slavio_base  = 0x70000000,
1352         .ms_kb_base   = 0x71000000,
1353         .serial_base  = 0x71100000,
1354         .nvram_base   = 0x71200000,
1355         .fd_base      = 0x71400000,
1356         .counter_base = 0x71d00000,
1357         .intctl_base  = 0x71e00000,
1358         .idreg_base   = 0x78000000,
1359         .dma_base     = 0x78400000,
1360         .esp_base     = 0x78800000,
1361         .le_base      = 0x78c00000,
1362         .apc_base     = 0x6a000000,
1363         .aux1_base    = 0x71900000,
1364         .aux2_base    = 0x71910000,
1365         .nvram_machine_id = 0x80,
1366         .machine_id = ss4_id,
1367         .iommu_version = 0x05000000,
1368         .max_mem = 0x10000000,
1369     };
1370 
1371     mc->desc = "Sun4m platform, SPARCstation 4";
1372     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1373     smc->hwdef = &ss4_hwdef;
1374 }
1375 
scls_class_init(ObjectClass * oc,void * data)1376 static void scls_class_init(ObjectClass *oc, void *data)
1377 {
1378     MachineClass *mc = MACHINE_CLASS(oc);
1379     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1380     static const struct sun4m_hwdef scls_hwdef = {
1381         .iommu_base   = 0x10000000,
1382         .tcx_base     = 0x50000000,
1383         .slavio_base  = 0x70000000,
1384         .ms_kb_base   = 0x71000000,
1385         .serial_base  = 0x71100000,
1386         .nvram_base   = 0x71200000,
1387         .fd_base      = 0x71400000,
1388         .counter_base = 0x71d00000,
1389         .intctl_base  = 0x71e00000,
1390         .idreg_base   = 0x78000000,
1391         .dma_base     = 0x78400000,
1392         .esp_base     = 0x78800000,
1393         .le_base      = 0x78c00000,
1394         .apc_base     = 0x6a000000,
1395         .aux1_base    = 0x71900000,
1396         .aux2_base    = 0x71910000,
1397         .nvram_machine_id = 0x80,
1398         .machine_id = scls_id,
1399         .iommu_version = 0x05000000,
1400         .max_mem = 0x10000000,
1401     };
1402 
1403     mc->desc = "Sun4m platform, SPARCClassic";
1404     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1405     smc->hwdef = &scls_hwdef;
1406 }
1407 
sbook_class_init(ObjectClass * oc,void * data)1408 static void sbook_class_init(ObjectClass *oc, void *data)
1409 {
1410     MachineClass *mc = MACHINE_CLASS(oc);
1411     Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1412     static const struct sun4m_hwdef sbook_hwdef = {
1413         .iommu_base   = 0x10000000,
1414         .tcx_base     = 0x50000000, /* XXX */
1415         .slavio_base  = 0x70000000,
1416         .ms_kb_base   = 0x71000000,
1417         .serial_base  = 0x71100000,
1418         .nvram_base   = 0x71200000,
1419         .fd_base      = 0x71400000,
1420         .counter_base = 0x71d00000,
1421         .intctl_base  = 0x71e00000,
1422         .idreg_base   = 0x78000000,
1423         .dma_base     = 0x78400000,
1424         .esp_base     = 0x78800000,
1425         .le_base      = 0x78c00000,
1426         .apc_base     = 0x6a000000,
1427         .aux1_base    = 0x71900000,
1428         .aux2_base    = 0x71910000,
1429         .nvram_machine_id = 0x80,
1430         .machine_id = sbook_id,
1431         .iommu_version = 0x05000000,
1432         .max_mem = 0x10000000,
1433     };
1434 
1435     mc->desc = "Sun4m platform, SPARCbook";
1436     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1437     smc->hwdef = &sbook_hwdef;
1438 }
1439 
1440 static const TypeInfo sun4m_machine_types[] = {
1441     {
1442         .name           = MACHINE_TYPE_NAME("SS-5"),
1443         .parent         = TYPE_SUN4M_MACHINE,
1444         .class_init     = ss5_class_init,
1445     }, {
1446         .name           = MACHINE_TYPE_NAME("SS-10"),
1447         .parent         = TYPE_SUN4M_MACHINE,
1448         .class_init     = ss10_class_init,
1449     }, {
1450         .name           = MACHINE_TYPE_NAME("SS-600MP"),
1451         .parent         = TYPE_SUN4M_MACHINE,
1452         .class_init     = ss600mp_class_init,
1453     }, {
1454         .name           = MACHINE_TYPE_NAME("SS-20"),
1455         .parent         = TYPE_SUN4M_MACHINE,
1456         .class_init     = ss20_class_init,
1457     }, {
1458         .name           = MACHINE_TYPE_NAME("Voyager"),
1459         .parent         = TYPE_SUN4M_MACHINE,
1460         .class_init     = voyager_class_init,
1461     }, {
1462         .name           = MACHINE_TYPE_NAME("LX"),
1463         .parent         = TYPE_SUN4M_MACHINE,
1464         .class_init     = ss_lx_class_init,
1465     }, {
1466         .name           = MACHINE_TYPE_NAME("SS-4"),
1467         .parent         = TYPE_SUN4M_MACHINE,
1468         .class_init     = ss4_class_init,
1469     }, {
1470         .name           = MACHINE_TYPE_NAME("SPARCClassic"),
1471         .parent         = TYPE_SUN4M_MACHINE,
1472         .class_init     = scls_class_init,
1473     }, {
1474         .name           = MACHINE_TYPE_NAME("SPARCbook"),
1475         .parent         = TYPE_SUN4M_MACHINE,
1476         .class_init     = sbook_class_init,
1477     }, {
1478         .name           = TYPE_SUN4M_MACHINE,
1479         .parent         = TYPE_MACHINE,
1480         .class_size     = sizeof(Sun4mMachineClass),
1481         .class_init     = sun4m_machine_class_init,
1482         .abstract       = true,
1483     }
1484 };
1485 
DEFINE_TYPES(sun4m_machine_types)1486 DEFINE_TYPES(sun4m_machine_types)
1487 
1488 static void sun4m_register_types(void)
1489 {
1490     type_register_static(&idreg_info);
1491     type_register_static(&afx_info);
1492     type_register_static(&prom_info);
1493     type_register_static(&ram_info);
1494 }
1495 
1496 type_init(sun4m_register_types)
1497