1 #ifndef CPER_SECTION_ARM_H 2 #define CPER_SECTION_ARM_H 3 4 #include <json.h> 5 #include "../edk/Cper.h" 6 7 #define ARM_ERROR_VALID_BITFIELD_NAMES \ 8 (const char *[]) \ 9 { \ 10 "mpidrValid", "errorAffinityLevelValid", "runningStateValid", \ 11 "vendorSpecificInfoValid" \ 12 } 13 #define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES \ 14 (const char *[]) \ 15 { \ 16 "multipleErrorValid", "flagsValid", "errorInformationValid", \ 17 "virtualFaultAddressValid", \ 18 "physicalFaultAddressValid" \ 19 } 20 #define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES \ 21 (const char *[]) \ 22 { \ 23 "firstErrorCaptured", "lastErrorCaptured", "propagated", \ 24 "overflow" \ 25 } 26 #define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES \ 27 (const char *[]) \ 28 { \ 29 "transactionTypeValid", "operationValid", "levelValid", \ 30 "processorContextCorruptValid", "correctedValid", \ 31 "precisePCValid", "restartablePCValid" \ 32 } 33 #define ARM_BUS_ERROR_VALID_BITFIELD_NAMES \ 34 (const char *[]) \ 35 { \ 36 "transactionTypeValid", "operationValid", "levelValid", \ 37 "processorContextCorruptValid", "correctedValid", \ 38 "precisePCValid", "restartablePCValid", \ 39 "participationTypeValid", "timedOutValid", \ 40 "addressSpaceValid", "memoryAttributesValid", \ 41 "accessModeValid" \ 42 } 43 #define ARM_ERROR_TRANSACTION_TYPES_KEYS \ 44 (int[]) \ 45 { \ 46 0, 1, 2 \ 47 } 48 #define ARM_ERROR_TRANSACTION_TYPES_VALUES \ 49 (const char *[]) \ 50 { \ 51 "Instruction", "Data Access", "Generic" \ 52 } 53 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS \ 54 (int[]) \ 55 { \ 56 0, 1, 2, 3 \ 57 } 58 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES \ 59 (const char *[]) \ 60 { \ 61 "Cache Error", "TLB Error", "Bus Error", \ 62 "Micro-Architectural Error" \ 63 } 64 #define ARM_CACHE_BUS_OPERATION_TYPES_KEYS \ 65 (int[]) \ 66 { \ 67 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 \ 68 } 69 #define ARM_CACHE_BUS_OPERATION_TYPES_VALUES \ 70 (const char *[]) \ 71 { \ 72 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 73 "Data Write", "Instruction Fetch", "Prefetch", \ 74 "Eviction", "Snooping", "Snooped", "Management" \ 75 } 76 #define ARM_TLB_OPERATION_TYPES_KEYS \ 77 (int[]) \ 78 { \ 79 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 80 } 81 #define ARM_TLB_OPERATION_TYPES_VALUES \ 82 (const char *[]) \ 83 { \ 84 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 85 "Data Write", "Instruction Fetch", "Prefetch", \ 86 "Local Management Operation", \ 87 "External Management Operation" \ 88 } 89 #define ARM_BUS_PARTICIPATION_TYPES_KEYS \ 90 (int[]) \ 91 { \ 92 0, 1, 2, 3 \ 93 } 94 #define ARM_BUS_PARTICIPATION_TYPES_VALUES \ 95 (const char *[]) \ 96 { \ 97 "Local Processor Originated Request", \ 98 "Local Processor Responded to Request", \ 99 "Local Processor Observed", "Generic" \ 100 } 101 #define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS \ 102 (int[]) \ 103 { \ 104 0, 1, 3 \ 105 } 106 #define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES \ 107 (const char *[]) \ 108 { \ 109 "External Memory Access", "Internal Memory Access", \ 110 "Device Memory Access" \ 111 } 112 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS \ 113 (int[]) \ 114 { \ 115 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 116 } 117 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES \ 118 (const char *[]) \ 119 { \ 120 "AArch32 General Purpose Registers", \ 121 "AArch32 EL1 Context Registers", \ 122 "AArch32 EL2 Context Registers", \ 123 "AArch32 Secure Context Registers", \ 124 "AArch64 General Purpose Registers", \ 125 "AArch64 EL1 Context Registers", \ 126 "AArch64 EL2 Context Registers", \ 127 "AArch64 EL3 Context Registers", \ 128 "Miscellaneous System Register Structure" \ 129 } 130 #define ARM_AARCH32_GPR_NAMES \ 131 (const char *[]) \ 132 { \ 133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 134 "r10", "r11", "r12", "r13_sp", "r14_lr", "r15_pc" \ 135 } 136 #define ARM_AARCH32_EL1_REGISTER_NAMES \ 137 (const char *[]) \ 138 { \ 139 "dfar", "dfsr", "ifar", "isr", "mair0", "mair1", "midr", \ 140 "mpidr", "nmrr", "prrr", "sctlr_ns", "spsr", \ 141 "spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc", \ 142 "spsr_und", "tpidrprw", "tpidruro", "tpidrurw", \ 143 "ttbcr", "ttbr0", "ttbr1", "dacr" \ 144 } 145 #define ARM_AARCH32_EL2_REGISTER_NAMES \ 146 (const char *[]) \ 147 { \ 148 "elr_hyp", "hamair0", "hamair1", "hcr", "hcr2", "hdfar", \ 149 "hifar", "hpfar", "hsr", "htcr", "htpidr", "httbr", \ 150 "spsr_hyp", "vtcr", "vttbr", "dacr32_el2" \ 151 } 152 #define ARM_AARCH32_SECURE_REGISTER_NAMES \ 153 (const char *[]) \ 154 { \ 155 "sctlr_s", "spsr_mon" \ 156 } 157 #define ARM_AARCH64_GPR_NAMES \ 158 (const char *[]) \ 159 { \ 160 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", \ 161 "x10", "x11", "x12", "x13", "x14", "x15", "x16", \ 162 "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 163 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp" \ 164 } 165 #define ARM_AARCH64_EL1_REGISTER_NAMES \ 166 (const char *[]) \ 167 { \ 168 "elr_el1", "esr_el1", "far_el1", "isr_el1", "mair_el1", \ 169 "midr_el1", "mpidr_el1", "sctlr_el1", "sp_el0", \ 170 "sp_el1", "spsr_el1", "tcr_el1", "tpidr_el0", \ 171 "tpidr_el1", "tpidrro_el0", "ttbr0_el1", "ttbr1_el1" \ 172 } 173 #define ARM_AARCH64_EL2_REGISTER_NAMES \ 174 (const char *[]) \ 175 { \ 176 "elr_el2", "esr_el2", "far_el2", "hacr_el2", "hcr_el2", \ 177 "hpfar_el2", "mair_el2", "sctlr_el2", "sp_el2", \ 178 "spsr_el2", "tcr_el2", "tpidr_el2", "ttbr0_el2", \ 179 "vtcr_el2", "vttbr_el2" \ 180 } 181 #define ARM_AARCH64_EL3_REGISTER_NAMES \ 182 (const char *[]) \ 183 { \ 184 "elr_el3", "esr_el3", "far_el3", "mair_el3", "sctlr_el3", \ 185 "sp_el3", "spsr_el3", "tcr_el3", "tpidr_el3", \ 186 "ttbr0_el3" \ 187 } 188 189 /// 190 /// ARM Processor Error Record 191 /// 192 typedef struct { 193 UINT32 ValidFields; 194 UINT16 ErrInfoNum; 195 UINT16 ContextInfoNum; 196 UINT32 SectionLength; 197 UINT32 ErrorAffinityLevel; 198 UINT64 MPIDR_EL1; 199 UINT64 MIDR_EL1; 200 UINT32 RunningState; 201 UINT32 PsciState; 202 } __attribute__((packed, aligned(1))) EFI_ARM_ERROR_RECORD; 203 204 /// 205 /// ARM Processor Error Information Structure 206 /// 207 #define ARM_ERROR_INFORMATION_TYPE_CACHE 0 208 #define ARM_ERROR_INFORMATION_TYPE_TLB 1 209 #define ARM_ERROR_INFORMATION_TYPE_BUS 2 210 #define ARM_ERROR_INFORMATION_TYPE_MICROARCH 3 211 212 typedef struct { 213 UINT64 ValidationBits : 16; 214 UINT64 TransactionType : 2; 215 UINT64 Operation : 4; 216 UINT64 Level : 3; 217 UINT64 ProcessorContextCorrupt : 1; 218 UINT64 Corrected : 1; 219 UINT64 PrecisePC : 1; 220 UINT64 RestartablePC : 1; 221 UINT64 Reserved : 34; 222 } EFI_ARM_CACHE_ERROR_STRUCTURE; 223 224 typedef struct { 225 UINT64 ValidationBits : 16; 226 UINT64 TransactionType : 2; 227 UINT64 Operation : 4; 228 UINT64 Level : 3; 229 UINT64 ProcessorContextCorrupt : 1; 230 UINT64 Corrected : 1; 231 UINT64 PrecisePC : 1; 232 UINT64 RestartablePC : 1; 233 UINT64 Reserved : 34; 234 } EFI_ARM_TLB_ERROR_STRUCTURE; 235 236 typedef struct { 237 UINT64 ValidationBits : 16; 238 UINT64 TransactionType : 2; 239 UINT64 Operation : 4; 240 UINT64 Level : 3; 241 UINT64 ProcessorContextCorrupt : 1; 242 UINT64 Corrected : 1; 243 UINT64 PrecisePC : 1; 244 UINT64 RestartablePC : 1; 245 UINT64 ParticipationType : 2; 246 UINT64 TimeOut : 1; 247 UINT64 AddressSpace : 2; 248 UINT64 MemoryAddressAttributes : 8; 249 UINT64 AccessMode : 1; 250 UINT64 Reserved : 19; 251 } EFI_ARM_BUS_ERROR_STRUCTURE; 252 253 typedef union { 254 UINT64 Value; 255 EFI_ARM_CACHE_ERROR_STRUCTURE CacheError; 256 EFI_ARM_TLB_ERROR_STRUCTURE TlbError; 257 EFI_ARM_BUS_ERROR_STRUCTURE BusError; 258 } EFI_ARM_ERROR_INFORMATION_STRUCTURE; 259 260 typedef struct { 261 UINT8 Version; 262 UINT8 Length; 263 UINT16 ValidationBits; 264 UINT8 Type; 265 UINT16 MultipleError; 266 UINT8 Flags; 267 EFI_ARM_ERROR_INFORMATION_STRUCTURE ErrorInformation; 268 UINT64 VirtualFaultAddress; 269 UINT64 PhysicalFaultAddress; 270 } __attribute__((packed, aligned(1))) EFI_ARM_ERROR_INFORMATION_ENTRY; 271 272 /// 273 /// ARM Processor Context Information Structure 274 /// 275 typedef struct { 276 UINT16 Version; 277 UINT16 RegisterContextType; 278 UINT32 RegisterArraySize; 279 } __attribute__((packed, aligned(1))) EFI_ARM_CONTEXT_INFORMATION_HEADER; 280 281 /// 282 /// ARM Processor Context Register Types 283 /// 284 #define EFI_ARM_CONTEXT_TYPE_AARCH32_GPR 0 285 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL1 1 286 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL2 2 287 #define EFI_ARM_CONTEXT_TYPE_AARCH32_SECURE 3 288 #define EFI_ARM_CONTEXT_TYPE_AARCH64_GPR 4 289 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL1 5 290 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL2 6 291 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL3 7 292 #define EFI_ARM_CONTEXT_TYPE_MISC 8 293 294 typedef struct { 295 UINT32 R0; 296 UINT32 R1; 297 UINT32 R2; 298 UINT32 R3; 299 UINT32 R4; 300 UINT32 R5; 301 UINT32 R6; 302 UINT32 R7; 303 UINT32 R8; 304 UINT32 R9; 305 UINT32 R10; 306 UINT32 R11; 307 UINT32 R12; 308 UINT32 R13_sp; 309 UINT32 R14_lr; 310 UINT32 R15_pc; 311 } EFI_ARM_V8_AARCH32_GPR; 312 313 typedef struct { 314 UINT32 Dfar; 315 UINT32 Dfsr; 316 UINT32 Ifar; 317 UINT32 Isr; 318 UINT32 Mair0; 319 UINT32 Mair1; 320 UINT32 Midr; 321 UINT32 Mpidr; 322 UINT32 Nmrr; 323 UINT32 Prrr; 324 UINT32 Sctlr_Ns; 325 UINT32 Spsr; 326 UINT32 Spsr_Abt; 327 UINT32 Spsr_Fiq; 328 UINT32 Spsr_Irq; 329 UINT32 Spsr_Svc; 330 UINT32 Spsr_Und; 331 UINT32 Tpidrprw; 332 UINT32 Tpidruro; 333 UINT32 Tpidrurw; 334 UINT32 Ttbcr; 335 UINT32 Ttbr0; 336 UINT32 Ttbr1; 337 UINT32 Dacr; 338 } EFI_ARM_AARCH32_EL1_CONTEXT_REGISTERS; 339 340 typedef struct { 341 UINT32 Elr_Hyp; 342 UINT32 Hamair0; 343 UINT32 Hamair1; 344 UINT32 Hcr; 345 UINT32 Hcr2; 346 UINT32 Hdfar; 347 UINT32 Hifar; 348 UINT32 Hpfar; 349 UINT32 Hsr; 350 UINT32 Htcr; 351 UINT32 Htpidr; 352 UINT32 Httbr; 353 UINT32 Spsr_Hyp; 354 UINT32 Vtcr; 355 UINT32 Vttbr; 356 UINT32 Dacr32_El2; 357 } EFI_ARM_AARCH32_EL2_CONTEXT_REGISTERS; 358 359 typedef struct { 360 UINT32 Sctlr_S; 361 UINT32 Spsr_Mon; 362 } EFI_ARM_AARCH32_SECURE_CONTEXT_REGISTERS; 363 364 typedef struct { 365 UINT64 X0; 366 UINT64 X1; 367 UINT64 X2; 368 UINT64 X3; 369 UINT64 X4; 370 UINT64 X5; 371 UINT64 X6; 372 UINT64 X7; 373 UINT64 X8; 374 UINT64 X9; 375 UINT64 X10; 376 UINT64 X11; 377 UINT64 X12; 378 UINT64 X13; 379 UINT64 X14; 380 UINT64 X15; 381 UINT64 X16; 382 UINT64 X17; 383 UINT64 X18; 384 UINT64 X19; 385 UINT64 X20; 386 UINT64 X21; 387 UINT64 X22; 388 UINT64 X23; 389 UINT64 X24; 390 UINT64 X25; 391 UINT64 X26; 392 UINT64 X27; 393 UINT64 X28; 394 UINT64 X29; 395 UINT64 X30; 396 UINT64 Sp; 397 } EFI_ARM_V8_AARCH64_GPR; 398 399 typedef struct { 400 UINT64 Elr_El1; 401 UINT64 Esr_El1; 402 UINT64 Far_El1; 403 UINT64 Isr_El1; 404 UINT64 Mair_El1; 405 UINT64 Midr_El1; 406 UINT64 Mpidr_El1; 407 UINT64 Sctlr_El1; 408 UINT64 Sp_El0; 409 UINT64 Sp_El1; 410 UINT64 Spsr_El1; 411 UINT64 Tcr_El1; 412 UINT64 Tpidr_El0; 413 UINT64 Tpidr_El1; 414 UINT64 Tpidrro_El0; 415 UINT64 Ttbr0_El1; 416 UINT64 Ttbr1_El1; 417 } EFI_ARM_AARCH64_EL1_CONTEXT_REGISTERS; 418 419 typedef struct { 420 UINT64 Elr_El2; 421 UINT64 Esr_El2; 422 UINT64 Far_El2; 423 UINT64 Hacr_El2; 424 UINT64 Hcr_El2; 425 UINT64 Hpfar_El2; 426 UINT64 Mair_El2; 427 UINT64 Sctlr_El2; 428 UINT64 Sp_El2; 429 UINT64 Spsr_El2; 430 UINT64 Tcr_El2; 431 UINT64 Tpidr_El2; 432 UINT64 Ttbr0_El2; 433 UINT64 Vtcr_El2; 434 UINT64 Vttbr_El2; 435 } EFI_ARM_AARCH64_EL2_CONTEXT_REGISTERS; 436 437 typedef struct { 438 UINT64 Elr_El3; 439 UINT64 Esr_El3; 440 UINT64 Far_El3; 441 UINT64 Mair_El3; 442 UINT64 Sctlr_El3; 443 UINT64 Sp_El3; 444 UINT64 Spsr_El3; 445 UINT64 Tcr_El3; 446 UINT64 Tpidr_El3; 447 UINT64 Ttbr0_El3; 448 } EFI_ARM_AARCH64_EL3_CONTEXT_REGISTERS; 449 450 typedef struct { 451 UINT64 MrsOp2 : 3; 452 UINT64 MrsCrm : 4; 453 UINT64 MrsCrn : 4; 454 UINT64 MrsOp1 : 3; 455 UINT64 MrsO0 : 1; 456 UINT64 Value : 64; 457 } EFI_ARM_MISC_CONTEXT_REGISTER; 458 459 json_object *cper_section_arm_to_ir(void *section); 460 void ir_section_arm_to_cper(json_object *section, FILE *out); 461 462 #endif 463