1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
4  *
5  * Copyright (c) 2013 MundoReader S.L.
6  * Author: Heiko Stuebner <heiko@sntech.de>
7  *
8  * With some ideas taken from pinctrl-samsung:
9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10  *		http://www.samsung.com
11  * Copyright (c) 2012 Linaro Ltd
12  *		https://www.linaro.org
13  *
14  * and pinctrl-at91:
15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16  */
17 
18 #ifndef _PINCTRL_ROCKCHIP_H
19 #define _PINCTRL_ROCKCHIP_H
20 
21 #define RK_GPIO0_A0	0
22 #define RK_GPIO0_A1	1
23 #define RK_GPIO0_A2	2
24 #define RK_GPIO0_A3	3
25 #define RK_GPIO0_A4	4
26 #define RK_GPIO0_A5	5
27 #define RK_GPIO0_A6	6
28 #define RK_GPIO0_A7	7
29 #define RK_GPIO0_B0	8
30 #define RK_GPIO0_B1	9
31 #define RK_GPIO0_B2	10
32 #define RK_GPIO0_B3	11
33 #define RK_GPIO0_B4	12
34 #define RK_GPIO0_B5	13
35 #define RK_GPIO0_B6	14
36 #define RK_GPIO0_B7	15
37 #define RK_GPIO0_C0	16
38 #define RK_GPIO0_C1	17
39 #define RK_GPIO0_C2	18
40 #define RK_GPIO0_C3	19
41 #define RK_GPIO0_C4	20
42 #define RK_GPIO0_C5	21
43 #define RK_GPIO0_C6	22
44 #define RK_GPIO0_C7	23
45 #define RK_GPIO0_D0	24
46 #define RK_GPIO0_D1	25
47 #define RK_GPIO0_D2	26
48 #define RK_GPIO0_D3	27
49 #define RK_GPIO0_D4	28
50 #define RK_GPIO0_D5	29
51 #define RK_GPIO0_D6	30
52 #define RK_GPIO0_D7	31
53 
54 #define RK_GPIO1_A0	32
55 #define RK_GPIO1_A1	33
56 #define RK_GPIO1_A2	34
57 #define RK_GPIO1_A3	35
58 #define RK_GPIO1_A4	36
59 #define RK_GPIO1_A5	37
60 #define RK_GPIO1_A6	38
61 #define RK_GPIO1_A7	39
62 #define RK_GPIO1_B0	40
63 #define RK_GPIO1_B1	41
64 #define RK_GPIO1_B2	42
65 #define RK_GPIO1_B3	43
66 #define RK_GPIO1_B4	44
67 #define RK_GPIO1_B5	45
68 #define RK_GPIO1_B6	46
69 #define RK_GPIO1_B7	47
70 #define RK_GPIO1_C0	48
71 #define RK_GPIO1_C1	49
72 #define RK_GPIO1_C2	50
73 #define RK_GPIO1_C3	51
74 #define RK_GPIO1_C4	52
75 #define RK_GPIO1_C5	53
76 #define RK_GPIO1_C6	54
77 #define RK_GPIO1_C7	55
78 #define RK_GPIO1_D0	56
79 #define RK_GPIO1_D1	57
80 #define RK_GPIO1_D2	58
81 #define RK_GPIO1_D3	59
82 #define RK_GPIO1_D4	60
83 #define RK_GPIO1_D5	61
84 #define RK_GPIO1_D6	62
85 #define RK_GPIO1_D7	63
86 
87 #define RK_GPIO2_A0	64
88 #define RK_GPIO2_A1	65
89 #define RK_GPIO2_A2	66
90 #define RK_GPIO2_A3	67
91 #define RK_GPIO2_A4	68
92 #define RK_GPIO2_A5	69
93 #define RK_GPIO2_A6	70
94 #define RK_GPIO2_A7	71
95 #define RK_GPIO2_B0	72
96 #define RK_GPIO2_B1	73
97 #define RK_GPIO2_B2	74
98 #define RK_GPIO2_B3	75
99 #define RK_GPIO2_B4	76
100 #define RK_GPIO2_B5	77
101 #define RK_GPIO2_B6	78
102 #define RK_GPIO2_B7	79
103 #define RK_GPIO2_C0	80
104 #define RK_GPIO2_C1	81
105 #define RK_GPIO2_C2	82
106 #define RK_GPIO2_C3	83
107 #define RK_GPIO2_C4	84
108 #define RK_GPIO2_C5	85
109 #define RK_GPIO2_C6	86
110 #define RK_GPIO2_C7	87
111 #define RK_GPIO2_D0	88
112 #define RK_GPIO2_D1	89
113 #define RK_GPIO2_D2	90
114 #define RK_GPIO2_D3	91
115 #define RK_GPIO2_D4	92
116 #define RK_GPIO2_D5	93
117 #define RK_GPIO2_D6	94
118 #define RK_GPIO2_D7	95
119 
120 #define RK_GPIO3_A0	96
121 #define RK_GPIO3_A1	97
122 #define RK_GPIO3_A2	98
123 #define RK_GPIO3_A3	99
124 #define RK_GPIO3_A4	100
125 #define RK_GPIO3_A5	101
126 #define RK_GPIO3_A6	102
127 #define RK_GPIO3_A7	103
128 #define RK_GPIO3_B0	104
129 #define RK_GPIO3_B1	105
130 #define RK_GPIO3_B2	106
131 #define RK_GPIO3_B3	107
132 #define RK_GPIO3_B4	108
133 #define RK_GPIO3_B5	109
134 #define RK_GPIO3_B6	110
135 #define RK_GPIO3_B7	111
136 #define RK_GPIO3_C0	112
137 #define RK_GPIO3_C1	113
138 #define RK_GPIO3_C2	114
139 #define RK_GPIO3_C3	115
140 #define RK_GPIO3_C4	116
141 #define RK_GPIO3_C5	117
142 #define RK_GPIO3_C6	118
143 #define RK_GPIO3_C7	119
144 #define RK_GPIO3_D0	120
145 #define RK_GPIO3_D1	121
146 #define RK_GPIO3_D2	122
147 #define RK_GPIO3_D3	123
148 #define RK_GPIO3_D4	124
149 #define RK_GPIO3_D5	125
150 #define RK_GPIO3_D6	126
151 #define RK_GPIO3_D7	127
152 
153 #define RK_GPIO4_A0	128
154 #define RK_GPIO4_A1	129
155 #define RK_GPIO4_A2	130
156 #define RK_GPIO4_A3	131
157 #define RK_GPIO4_A4	132
158 #define RK_GPIO4_A5	133
159 #define RK_GPIO4_A6	134
160 #define RK_GPIO4_A7	135
161 #define RK_GPIO4_B0	136
162 #define RK_GPIO4_B1	137
163 #define RK_GPIO4_B2	138
164 #define RK_GPIO4_B3	139
165 #define RK_GPIO4_B4	140
166 #define RK_GPIO4_B5	141
167 #define RK_GPIO4_B6	142
168 #define RK_GPIO4_B7	143
169 #define RK_GPIO4_C0	144
170 #define RK_GPIO4_C1	145
171 #define RK_GPIO4_C2	146
172 #define RK_GPIO4_C3	147
173 #define RK_GPIO4_C4	148
174 #define RK_GPIO4_C5	149
175 #define RK_GPIO4_C6	150
176 #define RK_GPIO4_C7	151
177 #define RK_GPIO4_D0	152
178 #define RK_GPIO4_D1	153
179 #define RK_GPIO4_D2	154
180 #define RK_GPIO4_D3	155
181 #define RK_GPIO4_D4	156
182 #define RK_GPIO4_D5	157
183 #define RK_GPIO4_D6	158
184 #define RK_GPIO4_D7	159
185 
186 enum rockchip_pinctrl_type {
187 	PX30,
188 	RV1108,
189 	RV1126,
190 	RK2928,
191 	RK3066B,
192 	RK3128,
193 	RK3188,
194 	RK3288,
195 	RK3308,
196 	RK3328,
197 	RK3368,
198 	RK3399,
199 	RK3568,
200 	RK3588,
201 };
202 
203 /**
204  * struct rockchip_gpio_regs
205  * @port_dr: data register
206  * @port_ddr: data direction register
207  * @int_en: interrupt enable
208  * @int_mask: interrupt mask
209  * @int_type: interrupt trigger type, such as high, low, edge trriger type.
210  * @int_polarity: interrupt polarity enable register
211  * @int_bothedge: interrupt bothedge enable register
212  * @int_status: interrupt status register
213  * @int_rawstatus: int_status = int_rawstatus & int_mask
214  * @debounce: enable debounce for interrupt signal
215  * @dbclk_div_en: enable divider for debounce clock
216  * @dbclk_div_con: setting for divider of debounce clock
217  * @port_eoi: end of interrupt of the port
218  * @ext_port: port data from external
219  * @version_id: controller version register
220  */
221 struct rockchip_gpio_regs {
222 	u32 port_dr;
223 	u32 port_ddr;
224 	u32 int_en;
225 	u32 int_mask;
226 	u32 int_type;
227 	u32 int_polarity;
228 	u32 int_bothedge;
229 	u32 int_status;
230 	u32 int_rawstatus;
231 	u32 debounce;
232 	u32 dbclk_div_en;
233 	u32 dbclk_div_con;
234 	u32 port_eoi;
235 	u32 ext_port;
236 	u32 version_id;
237 };
238 
239 /**
240  * struct rockchip_iomux
241  * @type: iomux variant using IOMUX_* constants
242  * @offset: if initialized to -1 it will be autocalculated, by specifying
243  *	    an initial offset value the relevant source offset can be reset
244  *	    to a new value for autocalculating the following iomux registers.
245  */
246 struct rockchip_iomux {
247 	int type;
248 	int offset;
249 };
250 
251 /*
252  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
253  */
254 enum rockchip_pin_drv_type {
255 	DRV_TYPE_IO_DEFAULT = 0,
256 	DRV_TYPE_IO_1V8_OR_3V0,
257 	DRV_TYPE_IO_1V8_ONLY,
258 	DRV_TYPE_IO_1V8_3V0_AUTO,
259 	DRV_TYPE_IO_3V3_ONLY,
260 	DRV_TYPE_MAX
261 };
262 
263 /*
264  * enum type index corresponding to rockchip_pull_list arrays index.
265  */
266 enum rockchip_pin_pull_type {
267 	PULL_TYPE_IO_DEFAULT = 0,
268 	PULL_TYPE_IO_1V8_ONLY,
269 	PULL_TYPE_MAX
270 };
271 
272 /**
273  * struct rockchip_drv
274  * @drv_type: drive strength variant using rockchip_perpin_drv_type
275  * @offset: if initialized to -1 it will be autocalculated, by specifying
276  *	    an initial offset value the relevant source offset can be reset
277  *	    to a new value for autocalculating the following drive strength
278  *	    registers. if used chips own cal_drv func instead to calculate
279  *	    registers offset, the variant could be ignored.
280  */
281 struct rockchip_drv {
282 	enum rockchip_pin_drv_type	drv_type;
283 	int				offset;
284 };
285 
286 /**
287  * struct rockchip_pin_bank
288  * @dev: the pinctrl device bind to the bank
289  * @reg_base: register base of the gpio bank
290  * @regmap_pull: optional separate register for additional pull settings
291  * @clk: clock of the gpio bank
292  * @db_clk: clock of the gpio debounce
293  * @irq: interrupt of the gpio bank
294  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
295  * @pin_base: first pin number
296  * @nr_pins: number of pins in this bank
297  * @name: name of the bank
298  * @bank_num: number of the bank, to account for holes
299  * @iomux: array describing the 4 iomux sources of the bank
300  * @drv: array describing the 4 drive strength sources of the bank
301  * @pull_type: array describing the 4 pull type sources of the bank
302  * @valid: is all necessary information present
303  * @of_node: dt node of this bank
304  * @drvdata: common pinctrl basedata
305  * @domain: irqdomain of the gpio bank
306  * @gpio_chip: gpiolib chip
307  * @grange: gpio range
308  * @slock: spinlock for the gpio bank
309  * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
310  * @recalced_mask: bit mask to indicate a need to recalulate the mask
311  * @route_mask: bits describing the routing pins of per bank
312  * @deferred_output: gpio output settings to be done after gpio bank probed
313  * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
314  */
315 struct rockchip_pin_bank {
316 	struct device			*dev;
317 	void __iomem			*reg_base;
318 	struct regmap			*regmap_pull;
319 	struct clk			*clk;
320 	struct clk			*db_clk;
321 	int				irq;
322 	u32				saved_masks;
323 	u32				pin_base;
324 	u8				nr_pins;
325 	char				*name;
326 	u8				bank_num;
327 	struct rockchip_iomux		iomux[4];
328 	struct rockchip_drv		drv[4];
329 	enum rockchip_pin_pull_type	pull_type[4];
330 	bool				valid;
331 	struct device_node		*of_node;
332 	struct rockchip_pinctrl		*drvdata;
333 	struct irq_domain		*domain;
334 	struct gpio_chip		gpio_chip;
335 	struct pinctrl_gpio_range	grange;
336 	raw_spinlock_t			slock;
337 	const struct rockchip_gpio_regs	*gpio_regs;
338 	u32				gpio_type;
339 	u32				toggle_edge_mode;
340 	u32				recalced_mask;
341 	u32				route_mask;
342 	struct list_head		deferred_pins;
343 	struct mutex			deferred_lock;
344 };
345 
346 /**
347  * struct rockchip_mux_recalced_data: represent a pin iomux data.
348  * @num: bank number.
349  * @pin: pin number.
350  * @bit: index at register.
351  * @reg: register offset.
352  * @mask: mask bit
353  */
354 struct rockchip_mux_recalced_data {
355 	u8 num;
356 	u8 pin;
357 	u32 reg;
358 	u8 bit;
359 	u8 mask;
360 };
361 
362 enum rockchip_mux_route_location {
363 	ROCKCHIP_ROUTE_SAME = 0,
364 	ROCKCHIP_ROUTE_PMU,
365 	ROCKCHIP_ROUTE_GRF,
366 };
367 
368 /**
369  * struct rockchip_mux_recalced_data: represent a pin iomux data.
370  * @bank_num: bank number.
371  * @pin: index at register or used to calc index.
372  * @func: the min pin.
373  * @route_location: the mux route location (same, pmu, grf).
374  * @route_offset: the max pin.
375  * @route_val: the register offset.
376  */
377 struct rockchip_mux_route_data {
378 	u8 bank_num;
379 	u8 pin;
380 	u8 func;
381 	enum rockchip_mux_route_location route_location;
382 	u32 route_offset;
383 	u32 route_val;
384 };
385 
386 struct rockchip_pin_ctrl {
387 	struct rockchip_pin_bank	*pin_banks;
388 	u32				nr_banks;
389 	u32				nr_pins;
390 	char				*label;
391 	enum rockchip_pinctrl_type	type;
392 	int				grf_mux_offset;
393 	int				pmu_mux_offset;
394 	int				grf_drv_offset;
395 	int				pmu_drv_offset;
396 	struct rockchip_mux_recalced_data *iomux_recalced;
397 	u32				niomux_recalced;
398 	struct rockchip_mux_route_data *iomux_routes;
399 	u32				niomux_routes;
400 
401 	int	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
402 				    int pin_num, struct regmap **regmap,
403 				    int *reg, u8 *bit);
404 	int	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
405 				    int pin_num, struct regmap **regmap,
406 				    int *reg, u8 *bit);
407 	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
408 				    int pin_num, struct regmap **regmap,
409 				    int *reg, u8 *bit);
410 };
411 
412 struct rockchip_pin_config {
413 	unsigned int		func;
414 	unsigned long		*configs;
415 	unsigned int		nconfigs;
416 };
417 
418 enum pin_config_param;
419 
420 struct rockchip_pin_deferred {
421 	struct list_head head;
422 	unsigned int pin;
423 	enum pin_config_param param;
424 	u32 arg;
425 };
426 
427 /**
428  * struct rockchip_pin_group: represent group of pins of a pinmux function.
429  * @name: name of the pin group, used to lookup the group.
430  * @pins: the pins included in this group.
431  * @npins: number of pins included in this group.
432  * @data: local pin configuration
433  */
434 struct rockchip_pin_group {
435 	const char			*name;
436 	unsigned int			npins;
437 	unsigned int			*pins;
438 	struct rockchip_pin_config	*data;
439 };
440 
441 /**
442  * struct rockchip_pmx_func: represent a pin function.
443  * @name: name of the pin function, used to lookup the function.
444  * @groups: one or more names of pin groups that provide this function.
445  * @ngroups: number of groups included in @groups.
446  */
447 struct rockchip_pmx_func {
448 	const char		*name;
449 	const char		**groups;
450 	u8			ngroups;
451 };
452 
453 struct rockchip_pinctrl {
454 	struct regmap			*regmap_base;
455 	int				reg_size;
456 	struct regmap			*regmap_pull;
457 	struct regmap			*regmap_pmu;
458 	struct device			*dev;
459 	struct rockchip_pin_ctrl	*ctrl;
460 	struct pinctrl_desc		pctl;
461 	struct pinctrl_dev		*pctl_dev;
462 	struct rockchip_pin_group	*groups;
463 	unsigned int			ngroups;
464 	struct rockchip_pmx_func	*functions;
465 	unsigned int			nfunctions;
466 };
467 
468 #endif
469