1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-19, Linaro Limited
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/of_net.h>
7 #include <linux/platform_device.h>
8 #include <linux/phy.h>
9 #include <linux/phy/phy.h>
10
11 #include "stmmac.h"
12 #include "stmmac_platform.h"
13
14 #define RGMII_IO_MACRO_CONFIG 0x0
15 #define SDCC_HC_REG_DLL_CONFIG 0x4
16 #define SDCC_TEST_CTL 0x8
17 #define SDCC_HC_REG_DDR_CONFIG 0xC
18 #define SDCC_HC_REG_DLL_CONFIG2 0x10
19 #define SDC4_STATUS 0x14
20 #define SDCC_USR_CTL 0x18
21 #define RGMII_IO_MACRO_CONFIG2 0x1C
22 #define RGMII_IO_MACRO_DEBUG1 0x20
23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
24 #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4
25
26 /* RGMII_IO_MACRO_CONFIG fields */
27 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
28 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
29 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
30 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
31 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
32 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
33 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
34 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
35 #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
36 #define RGMII_CONFIG_PROG_SWAP BIT(1)
37 #define RGMII_CONFIG_DDR_MODE BIT(0)
38 #define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
39
40 /* SDCC_HC_REG_DLL_CONFIG fields */
41 #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
42 #define SDCC_DLL_CONFIG_PDN BIT(29)
43 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
44 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
45 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
46 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
47 #define SDCC_DLL_CONFIG_CDR_EN BIT(17)
48 #define SDCC_DLL_CONFIG_DLL_EN BIT(16)
49 #define SDCC_DLL_MCLK_GATING_EN BIT(5)
50 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
51
52 /* SDCC_HC_REG_DDR_CONFIG fields */
53 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
56 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
57 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9)
58 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
59
60 /* SDCC_HC_REG_DLL_CONFIG2 fields */
61 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
62 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
64 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
65 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
66
67 /* SDC4_STATUS bits */
68 #define SDC4_STATUS_DLL_LOCK BIT(7)
69
70 /* RGMII_IO_MACRO_CONFIG2 fields */
71 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
72 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
73 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
74 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
75 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
76 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
77 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
78
79 /* MAC_CTRL_REG bits */
80 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
81 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
82
83 /* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */
84 #define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3)
85
86 #define SGMII_10M_RX_CLK_DVDR 0x31
87
88 struct ethqos_emac_por {
89 unsigned int offset;
90 unsigned int value;
91 };
92
93 struct ethqos_emac_driver_data {
94 const struct ethqos_emac_por *por;
95 unsigned int num_por;
96 bool rgmii_config_loopback_en;
97 bool has_emac_ge_3;
98 const char *link_clk_name;
99 bool has_integrated_pcs;
100 u32 dma_addr_width;
101 struct dwmac4_addrs dwmac4_addrs;
102 bool needs_sgmii_loopback;
103 };
104
105 struct qcom_ethqos {
106 struct platform_device *pdev;
107 void __iomem *rgmii_base;
108 void __iomem *mac_base;
109 int (*configure_func)(struct qcom_ethqos *ethqos);
110
111 unsigned int link_clk_rate;
112 struct clk *link_clk;
113 struct phy *serdes_phy;
114 unsigned int speed;
115 phy_interface_t phy_mode;
116
117 const struct ethqos_emac_por *por;
118 unsigned int num_por;
119 bool rgmii_config_loopback_en;
120 bool has_emac_ge_3;
121 bool needs_sgmii_loopback;
122 };
123
rgmii_readl(struct qcom_ethqos * ethqos,unsigned int offset)124 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
125 {
126 return readl(ethqos->rgmii_base + offset);
127 }
128
rgmii_writel(struct qcom_ethqos * ethqos,int value,unsigned int offset)129 static void rgmii_writel(struct qcom_ethqos *ethqos,
130 int value, unsigned int offset)
131 {
132 writel(value, ethqos->rgmii_base + offset);
133 }
134
rgmii_updatel(struct qcom_ethqos * ethqos,int mask,int val,unsigned int offset)135 static void rgmii_updatel(struct qcom_ethqos *ethqos,
136 int mask, int val, unsigned int offset)
137 {
138 unsigned int temp;
139
140 temp = rgmii_readl(ethqos, offset);
141 temp = (temp & ~(mask)) | val;
142 rgmii_writel(ethqos, temp, offset);
143 }
144
rgmii_dump(void * priv)145 static void rgmii_dump(void *priv)
146 {
147 struct qcom_ethqos *ethqos = priv;
148 struct device *dev = ðqos->pdev->dev;
149
150 dev_dbg(dev, "Rgmii register dump\n");
151 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n",
152 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
153 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
154 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
155 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
156 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
157 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
158 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
159 dev_dbg(dev, "SDC4_STATUS: %x\n",
160 rgmii_readl(ethqos, SDC4_STATUS));
161 dev_dbg(dev, "SDCC_USR_CTL: %x\n",
162 rgmii_readl(ethqos, SDCC_USR_CTL));
163 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
164 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
165 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
166 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
167 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
168 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
169 }
170
171 /* Clock rates */
172 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL)
173 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL)
174 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
175
176 static void
ethqos_update_link_clk(struct qcom_ethqos * ethqos,unsigned int speed)177 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
178 {
179 switch (speed) {
180 case SPEED_1000:
181 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
182 break;
183
184 case SPEED_100:
185 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
186 break;
187
188 case SPEED_10:
189 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
190 break;
191 }
192
193 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
194 }
195
196 static void
qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos * ethqos,bool enable)197 qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)
198 {
199 if (!ethqos->needs_sgmii_loopback ||
200 ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX)
201 return;
202
203 rgmii_updatel(ethqos,
204 SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN,
205 enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0,
206 EMAC_WRAPPER_SGMII_PHY_CNTRL1);
207 }
208
ethqos_set_func_clk_en(struct qcom_ethqos * ethqos)209 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
210 {
211 qcom_ethqos_set_sgmii_loopback(ethqos, true);
212 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
213 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
214 }
215
216 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
217 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
218 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
219 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
220 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
221 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
222 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
223 };
224
225 static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
226 .por = emac_v2_3_0_por,
227 .num_por = ARRAY_SIZE(emac_v2_3_0_por),
228 .rgmii_config_loopback_en = true,
229 .has_emac_ge_3 = false,
230 };
231
232 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
233 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
234 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
235 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
236 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
237 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
238 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
239 };
240
241 static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
242 .por = emac_v2_1_0_por,
243 .num_por = ARRAY_SIZE(emac_v2_1_0_por),
244 .rgmii_config_loopback_en = false,
245 .has_emac_ge_3 = false,
246 };
247
248 static const struct ethqos_emac_por emac_v3_0_0_por[] = {
249 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
250 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
251 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
252 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
253 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
254 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
255 };
256
257 static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
258 .por = emac_v3_0_0_por,
259 .num_por = ARRAY_SIZE(emac_v3_0_0_por),
260 .rgmii_config_loopback_en = false,
261 .has_emac_ge_3 = true,
262 .dwmac4_addrs = {
263 .dma_chan = 0x00008100,
264 .dma_chan_offset = 0x1000,
265 .mtl_chan = 0x00008000,
266 .mtl_chan_offset = 0x1000,
267 .mtl_ets_ctrl = 0x00008010,
268 .mtl_ets_ctrl_offset = 0x1000,
269 .mtl_txq_weight = 0x00008018,
270 .mtl_txq_weight_offset = 0x1000,
271 .mtl_send_slp_cred = 0x0000801c,
272 .mtl_send_slp_cred_offset = 0x1000,
273 .mtl_high_cred = 0x00008020,
274 .mtl_high_cred_offset = 0x1000,
275 .mtl_low_cred = 0x00008024,
276 .mtl_low_cred_offset = 0x1000,
277 },
278 };
279
280 static const struct ethqos_emac_por emac_v4_0_0_por[] = {
281 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
282 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
283 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
284 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
285 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
286 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
287 };
288
289 static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
290 .por = emac_v4_0_0_por,
291 .num_por = ARRAY_SIZE(emac_v4_0_0_por),
292 .rgmii_config_loopback_en = false,
293 .has_emac_ge_3 = true,
294 .link_clk_name = "phyaux",
295 .has_integrated_pcs = true,
296 .needs_sgmii_loopback = true,
297 .dma_addr_width = 36,
298 .dwmac4_addrs = {
299 .dma_chan = 0x00008100,
300 .dma_chan_offset = 0x1000,
301 .mtl_chan = 0x00008000,
302 .mtl_chan_offset = 0x1000,
303 .mtl_ets_ctrl = 0x00008010,
304 .mtl_ets_ctrl_offset = 0x1000,
305 .mtl_txq_weight = 0x00008018,
306 .mtl_txq_weight_offset = 0x1000,
307 .mtl_send_slp_cred = 0x0000801c,
308 .mtl_send_slp_cred_offset = 0x1000,
309 .mtl_high_cred = 0x00008020,
310 .mtl_high_cred_offset = 0x1000,
311 .mtl_low_cred = 0x00008024,
312 .mtl_low_cred_offset = 0x1000,
313 },
314 };
315
ethqos_dll_configure(struct qcom_ethqos * ethqos)316 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
317 {
318 struct device *dev = ðqos->pdev->dev;
319 unsigned int val;
320 int retry = 1000;
321
322 /* Set CDR_EN */
323 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
324 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
325
326 /* Set CDR_EXT_EN */
327 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
328 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
329
330 /* Clear CK_OUT_EN */
331 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
332 0, SDCC_HC_REG_DLL_CONFIG);
333
334 /* Set DLL_EN */
335 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
336 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
337
338 if (!ethqos->has_emac_ge_3) {
339 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
340 0, SDCC_HC_REG_DLL_CONFIG);
341
342 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
343 0, SDCC_HC_REG_DLL_CONFIG);
344 }
345
346 /* Wait for CK_OUT_EN clear */
347 do {
348 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
349 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
350 if (!val)
351 break;
352 mdelay(1);
353 retry--;
354 } while (retry > 0);
355 if (!retry)
356 dev_err(dev, "Clear CK_OUT_EN timedout\n");
357
358 /* Set CK_OUT_EN */
359 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
360 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
361
362 /* Wait for CK_OUT_EN set */
363 retry = 1000;
364 do {
365 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
366 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
367 if (val)
368 break;
369 mdelay(1);
370 retry--;
371 } while (retry > 0);
372 if (!retry)
373 dev_err(dev, "Set CK_OUT_EN timedout\n");
374
375 /* Set DDR_CAL_EN */
376 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
377 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
378
379 if (!ethqos->has_emac_ge_3) {
380 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
381 0, SDCC_HC_REG_DLL_CONFIG2);
382
383 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
384 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
385
386 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
387 BIT(2), SDCC_HC_REG_DLL_CONFIG2);
388
389 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
390 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
391 SDCC_HC_REG_DLL_CONFIG2);
392 }
393
394 return 0;
395 }
396
ethqos_rgmii_macro_init(struct qcom_ethqos * ethqos)397 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
398 {
399 struct device *dev = ðqos->pdev->dev;
400 int phase_shift;
401 int loopback;
402
403 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
404 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
405 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
406 phase_shift = 0;
407 else
408 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
409
410 /* Disable loopback mode */
411 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
412 0, RGMII_IO_MACRO_CONFIG2);
413
414 /* Determine if this platform wants loopback enabled after programming */
415 if (ethqos->rgmii_config_loopback_en)
416 loopback = RGMII_CONFIG_LOOPBACK_EN;
417 else
418 loopback = 0;
419
420 /* Select RGMII, write 0 to interface select */
421 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
422 0, RGMII_IO_MACRO_CONFIG);
423
424 switch (ethqos->speed) {
425 case SPEED_1000:
426 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
427 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
428 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
429 0, RGMII_IO_MACRO_CONFIG);
430 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
431 RGMII_CONFIG_POS_NEG_DATA_SEL,
432 RGMII_IO_MACRO_CONFIG);
433 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
434 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
435 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
436 0, RGMII_IO_MACRO_CONFIG2);
437
438 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
439 phase_shift, RGMII_IO_MACRO_CONFIG2);
440 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
441 0, RGMII_IO_MACRO_CONFIG2);
442 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
443 RGMII_CONFIG2_RX_PROG_SWAP,
444 RGMII_IO_MACRO_CONFIG2);
445
446 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
447 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
448 */
449 if (ethqos->has_emac_ge_3) {
450 /* 0.9 ns */
451 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
452 115, SDCC_HC_REG_DDR_CONFIG);
453 } else {
454 /* 1.8 ns */
455 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
456 57, SDCC_HC_REG_DDR_CONFIG);
457 }
458 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
459 SDCC_DDR_CONFIG_PRG_DLY_EN,
460 SDCC_HC_REG_DDR_CONFIG);
461 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
462 loopback, RGMII_IO_MACRO_CONFIG);
463 break;
464
465 case SPEED_100:
466 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
467 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
468 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
469 RGMII_CONFIG_BYPASS_TX_ID_EN,
470 RGMII_IO_MACRO_CONFIG);
471 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
472 0, RGMII_IO_MACRO_CONFIG);
473 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
474 0, RGMII_IO_MACRO_CONFIG);
475 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
476 0, RGMII_IO_MACRO_CONFIG2);
477 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
478 phase_shift, RGMII_IO_MACRO_CONFIG2);
479 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
480 BIT(6), RGMII_IO_MACRO_CONFIG);
481 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
482 0, RGMII_IO_MACRO_CONFIG2);
483
484 if (ethqos->has_emac_ge_3)
485 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
486 RGMII_CONFIG2_RX_PROG_SWAP,
487 RGMII_IO_MACRO_CONFIG2);
488 else
489 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
490 0, RGMII_IO_MACRO_CONFIG2);
491
492 /* Write 0x5 to PRG_RCLK_DLY_CODE */
493 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
494 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
495 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
496 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
497 SDCC_HC_REG_DDR_CONFIG);
498 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
499 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
500 SDCC_HC_REG_DDR_CONFIG);
501 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
502 loopback, RGMII_IO_MACRO_CONFIG);
503 break;
504
505 case SPEED_10:
506 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
507 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
508 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
509 RGMII_CONFIG_BYPASS_TX_ID_EN,
510 RGMII_IO_MACRO_CONFIG);
511 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
512 0, RGMII_IO_MACRO_CONFIG);
513 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
514 0, RGMII_IO_MACRO_CONFIG);
515 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
516 0, RGMII_IO_MACRO_CONFIG2);
517 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
518 phase_shift, RGMII_IO_MACRO_CONFIG2);
519 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
520 BIT(12) | GENMASK(9, 8),
521 RGMII_IO_MACRO_CONFIG);
522 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
523 0, RGMII_IO_MACRO_CONFIG2);
524 if (ethqos->has_emac_ge_3)
525 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
526 RGMII_CONFIG2_RX_PROG_SWAP,
527 RGMII_IO_MACRO_CONFIG2);
528 else
529 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
530 0, RGMII_IO_MACRO_CONFIG2);
531 /* Write 0x5 to PRG_RCLK_DLY_CODE */
532 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
533 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
534 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
535 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
536 SDCC_HC_REG_DDR_CONFIG);
537 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
538 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
539 SDCC_HC_REG_DDR_CONFIG);
540 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
541 loopback, RGMII_IO_MACRO_CONFIG);
542 break;
543 default:
544 dev_err(dev, "Invalid speed %d\n", ethqos->speed);
545 return -EINVAL;
546 }
547
548 return 0;
549 }
550
ethqos_configure_rgmii(struct qcom_ethqos * ethqos)551 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
552 {
553 struct device *dev = ðqos->pdev->dev;
554 volatile unsigned int dll_lock;
555 unsigned int i, retry = 1000;
556
557 /* Reset to POR values and enable clk */
558 for (i = 0; i < ethqos->num_por; i++)
559 rgmii_writel(ethqos, ethqos->por[i].value,
560 ethqos->por[i].offset);
561 ethqos_set_func_clk_en(ethqos);
562
563 /* Initialize the DLL first */
564
565 /* Set DLL_RST */
566 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
567 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
568
569 /* Set PDN */
570 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
571 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
572
573 if (ethqos->has_emac_ge_3) {
574 if (ethqos->speed == SPEED_1000) {
575 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
576 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
577 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
578 } else {
579 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
580 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
581 }
582 }
583
584 /* Clear DLL_RST */
585 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
586 SDCC_HC_REG_DLL_CONFIG);
587
588 /* Clear PDN */
589 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
590 SDCC_HC_REG_DLL_CONFIG);
591
592 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
593 /* Set DLL_EN */
594 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
595 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
596
597 /* Set CK_OUT_EN */
598 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
599 SDCC_DLL_CONFIG_CK_OUT_EN,
600 SDCC_HC_REG_DLL_CONFIG);
601
602 /* Set USR_CTL bit 26 with mask of 3 bits */
603 if (!ethqos->has_emac_ge_3)
604 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
605 SDCC_USR_CTL);
606
607 /* wait for DLL LOCK */
608 do {
609 mdelay(1);
610 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
611 if (dll_lock & SDC4_STATUS_DLL_LOCK)
612 break;
613 retry--;
614 } while (retry > 0);
615 if (!retry)
616 dev_err(dev, "Timeout while waiting for DLL lock\n");
617 }
618
619 if (ethqos->speed == SPEED_1000)
620 ethqos_dll_configure(ethqos);
621
622 ethqos_rgmii_macro_init(ethqos);
623
624 return 0;
625 }
626
627 /* On interface toggle MAC registers gets reset.
628 * Configure MAC block for SGMII on ethernet phy link up
629 */
ethqos_configure_sgmii(struct qcom_ethqos * ethqos)630 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
631 {
632 int val;
633
634 val = readl(ethqos->mac_base + MAC_CTRL_REG);
635
636 switch (ethqos->speed) {
637 case SPEED_1000:
638 val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
639 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
640 RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
641 RGMII_IO_MACRO_CONFIG2);
642 break;
643 case SPEED_100:
644 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
645 break;
646 case SPEED_10:
647 val |= ETHQOS_MAC_CTRL_PORT_SEL;
648 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
649 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
650 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,
651 SGMII_10M_RX_CLK_DVDR),
652 RGMII_IO_MACRO_CONFIG);
653 break;
654 }
655
656 writel(val, ethqos->mac_base + MAC_CTRL_REG);
657
658 return val;
659 }
660
ethqos_configure(struct qcom_ethqos * ethqos)661 static int ethqos_configure(struct qcom_ethqos *ethqos)
662 {
663 return ethqos->configure_func(ethqos);
664 }
665
ethqos_fix_mac_speed(void * priv,unsigned int speed,unsigned int mode)666 static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
667 {
668 struct qcom_ethqos *ethqos = priv;
669
670 qcom_ethqos_set_sgmii_loopback(ethqos, false);
671 ethqos->speed = speed;
672 ethqos_update_link_clk(ethqos, speed);
673 ethqos_configure(ethqos);
674 }
675
qcom_ethqos_serdes_powerup(struct net_device * ndev,void * priv)676 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
677 {
678 struct qcom_ethqos *ethqos = priv;
679 int ret;
680
681 ret = phy_init(ethqos->serdes_phy);
682 if (ret)
683 return ret;
684
685 ret = phy_power_on(ethqos->serdes_phy);
686 if (ret)
687 return ret;
688
689 return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
690 }
691
qcom_ethqos_serdes_powerdown(struct net_device * ndev,void * priv)692 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
693 {
694 struct qcom_ethqos *ethqos = priv;
695
696 phy_power_off(ethqos->serdes_phy);
697 phy_exit(ethqos->serdes_phy);
698 }
699
ethqos_clks_config(void * priv,bool enabled)700 static int ethqos_clks_config(void *priv, bool enabled)
701 {
702 struct qcom_ethqos *ethqos = priv;
703 int ret = 0;
704
705 if (enabled) {
706 ret = clk_prepare_enable(ethqos->link_clk);
707 if (ret) {
708 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
709 return ret;
710 }
711
712 /* Enable functional clock to prevent DMA reset to timeout due
713 * to lacking PHY clock after the hardware block has been power
714 * cycled. The actual configuration will be adjusted once
715 * ethqos_fix_mac_speed() is invoked.
716 */
717 ethqos_set_func_clk_en(ethqos);
718 } else {
719 clk_disable_unprepare(ethqos->link_clk);
720 }
721
722 return ret;
723 }
724
ethqos_clks_disable(void * data)725 static void ethqos_clks_disable(void *data)
726 {
727 ethqos_clks_config(data, false);
728 }
729
ethqos_ptp_clk_freq_config(struct stmmac_priv * priv)730 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv)
731 {
732 struct plat_stmmacenet_data *plat_dat = priv->plat;
733 int err;
734
735 if (!plat_dat->clk_ptp_ref)
736 return;
737
738 /* Max the PTP ref clock out to get the best resolution possible */
739 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX);
740 if (err)
741 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err);
742 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref);
743
744 netdev_dbg(priv->dev, "PTP rate %d\n", plat_dat->clk_ptp_rate);
745 }
746
qcom_ethqos_probe(struct platform_device * pdev)747 static int qcom_ethqos_probe(struct platform_device *pdev)
748 {
749 struct device_node *np = pdev->dev.of_node;
750 const struct ethqos_emac_driver_data *data;
751 struct plat_stmmacenet_data *plat_dat;
752 struct stmmac_resources stmmac_res;
753 struct device *dev = &pdev->dev;
754 struct qcom_ethqos *ethqos;
755 int ret;
756
757 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
758 if (ret)
759 return dev_err_probe(dev, ret,
760 "Failed to get platform resources\n");
761
762 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
763 if (IS_ERR(plat_dat)) {
764 return dev_err_probe(dev, PTR_ERR(plat_dat),
765 "dt configuration failed\n");
766 }
767
768 plat_dat->clks_config = ethqos_clks_config;
769
770 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
771 if (!ethqos)
772 return -ENOMEM;
773
774 ret = of_get_phy_mode(np, ðqos->phy_mode);
775 if (ret)
776 return dev_err_probe(dev, ret, "Failed to get phy mode\n");
777 switch (ethqos->phy_mode) {
778 case PHY_INTERFACE_MODE_RGMII:
779 case PHY_INTERFACE_MODE_RGMII_ID:
780 case PHY_INTERFACE_MODE_RGMII_RXID:
781 case PHY_INTERFACE_MODE_RGMII_TXID:
782 ethqos->configure_func = ethqos_configure_rgmii;
783 break;
784 case PHY_INTERFACE_MODE_SGMII:
785 ethqos->configure_func = ethqos_configure_sgmii;
786 break;
787 default:
788 dev_err(dev, "Unsupported phy mode %s\n",
789 phy_modes(ethqos->phy_mode));
790 return -EINVAL;
791 }
792
793 ethqos->pdev = pdev;
794 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
795 if (IS_ERR(ethqos->rgmii_base))
796 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
797 "Failed to map rgmii resource\n");
798
799 ethqos->mac_base = stmmac_res.addr;
800
801 data = of_device_get_match_data(dev);
802 ethqos->por = data->por;
803 ethqos->num_por = data->num_por;
804 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
805 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
806 ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback;
807
808 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
809 if (IS_ERR(ethqos->link_clk))
810 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
811 "Failed to get link_clk\n");
812
813 ret = ethqos_clks_config(ethqos, true);
814 if (ret)
815 return ret;
816
817 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
818 if (ret)
819 return ret;
820
821 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
822 if (IS_ERR(ethqos->serdes_phy))
823 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
824 "Failed to get serdes phy\n");
825
826 ethqos->speed = SPEED_1000;
827 ethqos_update_link_clk(ethqos, SPEED_1000);
828 ethqos_set_func_clk_en(ethqos);
829
830 plat_dat->bsp_priv = ethqos;
831 plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
832 plat_dat->dump_debug_regs = rgmii_dump;
833 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
834 plat_dat->has_gmac4 = 1;
835 if (ethqos->has_emac_ge_3)
836 plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
837 plat_dat->pmt = 1;
838 if (of_property_read_bool(np, "snps,tso"))
839 plat_dat->flags |= STMMAC_FLAG_TSO_EN;
840 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
841 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI;
842 if (data->has_integrated_pcs)
843 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS;
844 if (data->dma_addr_width)
845 plat_dat->host_dma_width = data->dma_addr_width;
846
847 if (ethqos->serdes_phy) {
848 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
849 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
850 }
851
852 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
853 }
854
855 static const struct of_device_id qcom_ethqos_match[] = {
856 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
857 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
858 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
859 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
860 { }
861 };
862 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
863
864 static struct platform_driver qcom_ethqos_driver = {
865 .probe = qcom_ethqos_probe,
866 .driver = {
867 .name = "qcom-ethqos",
868 .pm = &stmmac_pltfr_pm_ops,
869 .of_match_table = qcom_ethqos_match,
870 },
871 };
872 module_platform_driver(qcom_ethqos_driver);
873
874 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
875 MODULE_LICENSE("GPL v2");
876