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Searched refs:xgene_enet_wr_csr (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.c15 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_csr() function
236 xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data); in xgene_xgmac_set_mss()
316 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); in xgene_xgmac_init()
321 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data); in xgene_xgmac_init()
325 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); in xgene_xgmac_init()
326 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82); in xgene_xgmac_init()
327 xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0); in xgene_xgmac_init()
328 xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX); in xgene_xgmac_init()
342 xgene_enet_wr_csr(pdata, XG_RXBUF_PAUSE_THRESH, data); in xgene_xgmac_init()
422 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb); in xgene_enet_xgcle_bypass()
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H A Dxgene_enet_sgmac.c14 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) in xgene_enet_wr_csr() function
270 xgene_enet_wr_csr(p, debug_addr, value); in xgene_sgmac_set_speed()
359 xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); in xgene_sgmac_init()
369 xgene_enet_wr_csr(p, rsif_config_reg, data); in xgene_sgmac_init()
401 xgene_enet_wr_csr(p, pause_thres_reg, data1); in xgene_sgmac_init()
402 xgene_enet_wr_csr(p, pause_off_thres_reg, data2); in xgene_sgmac_init()
405 xgene_enet_wr_csr(p, pause_thres_reg, data); in xgene_sgmac_init()
412 xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); in xgene_sgmac_init()
413 xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); in xgene_sgmac_init()
499 xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); in xgene_enet_cle_bypass()
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H A Dxgene_enet_hw.c223 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, in xgene_enet_wr_csr() function
496 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); in xgene_gmac_set_speed()
503 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); in xgene_gmac_set_speed()
578 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); in xgene_gmac_init()
581 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); in xgene_gmac_init()
588 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES); in xgene_gmac_init()
589 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES); in xgene_gmac_init()
595 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); in xgene_gmac_init()
603 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); in xgene_gmac_init()
642 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); in xgene_enet_cle_bypass()
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