/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument 42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument 43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument 45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument 46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument [all …]
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H A D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument 70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument 72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument 73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument 75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument 76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument 78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument 79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument 81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument 82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument [all …]
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H A D | rs690d.h | 34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument 36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument 37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument 39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument 40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument 55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument [all …]
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H A D | rv515d.h | 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument 211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument 213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument 214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument 216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument 217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument 219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument 220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument 222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument 223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument [all …]
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H A D | r420d.h | 32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument 33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument 35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument 36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument 43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument 50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument [all …]
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H A D | r300d.h | 84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument 85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument 92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument 99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument 101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument 102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument [all …]
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H A D | r520d.h | 37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument 48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument 50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument 51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument 53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument [all …]
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H A D | r600d.h | 111 # define CB_FORMAT(x) ((x) << 2) argument 382 #define S0_X(x) ((x) << 0) argument 383 #define S0_Y(x) ((x) << 4) argument 384 #define S1_X(x) ((x) << 8) argument 385 #define S1_Y(x) ((x) << 12) argument 386 #define S2_X(x) ((x) << 16) argument 387 #define S2_Y(x) ((x) << 20) argument 388 #define S3_X(x) ((x) << 24) argument 390 #define S4_X(x) ((x) << 0) argument 391 #define S4_Y(x) ((x) << 4) argument [all …]
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H A D | rs400d.h | 33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument 34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument 47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument 54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument 56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument 57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument [all …]
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H A D | rv250d.h | 32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument 33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument 35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument 36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument 38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument 39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument 41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument 42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument 44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument 45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument [all …]
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H A D | evergreend.h | 53 #define HOST_SMC_MSG(x) ((x) << 0) argument 56 #define HOST_SMC_RESP(x) ((x) << 8) argument 99 #define CLKF(x) ((x) << 0) argument 101 #define CLKR(x) ((x) << 7) argument 103 #define CLKFRAC(x) ((x) << 12) argument 107 #define IBIAS(x) ((x) << 20) argument 226 #define CLKV(x) ((x) << 0) argument 229 #define CLKS(x) ((x) << 0) argument 277 #define STATE0(x) ((x) << 0) argument 279 #define STATE1(x) ((x) << 5) argument [all …]
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H A D | rv770d.h | 47 # define UPLL_REF_DIV(x) ((x) << 16) argument 62 # define UPLL_FB_DIV(x) ((x) << 0) argument 119 #define CLKF(x) ((x) << 0) argument 121 #define CLKR(x) ((x) << 7) argument 123 #define CLKFRAC(x) ((x) << 12) argument 127 #define IBIAS(x) ((x) << 20) argument 271 #define CLKS(x) ((x) << 4) argument 274 #define CLKV(x) ((x) << 0) argument 291 #define STATE0(x) ((x) << 0) argument 293 #define STATE1(x) ((x) << 8) argument [all …]
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/openbmc/u-boot/include/andestech/ |
H A D | andes_pcu.h | 98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument 100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument 101 #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) argument 107 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) argument 126 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) argument 127 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) argument 129 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) argument 132 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) argument 133 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) argument 134 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) argument [all …]
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/openbmc/u-boot/include/synopsys/ |
H A D | dwcddr21mctl.h | 47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument 48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument 49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument 50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument 51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument 52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument 58 #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) argument 59 #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) argument 60 #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) argument 65 #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) argument [all …]
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/openbmc/linux/drivers/media/platform/verisilicon/ |
H A D | rockchip_vpu2_regs.h | 14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument 15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument 17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument 18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument 20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument 21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument 23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument 24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument 25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument 28 #define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) argument [all …]
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H A D | hantro_g1_regs.h | 28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument 37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument 41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument 45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument 47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument 80 #define G1_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) argument 101 #define G1_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) argument 102 #define G1_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) argument 111 #define G1_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) argument 153 #define G1_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) argument [all …]
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/openbmc/linux/lib/crypto/ |
H A D | chacha.c | 24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute() 25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute() 26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute() 27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute() 29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute() 30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute() 31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute() 32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute() 34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute() 35 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 8); in chacha_permute() [all …]
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/openbmc/u-boot/board/samsung/odroid/ |
H A D | setup.h | 11 #define SDIV(x) ((x) & 0x7) argument 19 #define MUX_APLL_SEL(x) ((x) & 0x1) argument 81 #define MUX_C2C_SEL(x) ((x) & 0x1) argument 91 #define C2C_SEL(x) (((x)) & 0x7) argument 109 #define ACP_RATIO(x) ((x) & 0x7) argument 117 #define DIV_ACP(x) ((x) & 0x1) argument 159 #define UART0_SEL(x) ((x) & 0xf) argument 173 #define DIV_UART0(x) ((x) & 0x1) argument 188 #define DIV_MMC0(x) ((x) & 1) argument 205 #define DIV_MMC2(x) ((x) & 0x1) argument [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | vop_rk3288.h | 122 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument 123 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument 124 #define V_DMA_STOP(x) (((x) & 1) << 21) argument 125 #define V_MMU_EN(x) (((x) & 1) << 20) argument 133 #define V_EDPI_HALT_EN(x) (((x)&1)<<8) argument 137 #define V_DIRECT_PATH_EN(x) ((x) & 1) argument 329 #define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) argument 353 #define V_VSYNC(x) (((x)&0x1fff)<<0) argument 354 #define V_VERPRD(x) (((x)&0x1fff)<<16) argument 358 #define V_VAEP(x) (((x)&0x1fff)<<0) argument [all …]
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/openbmc/linux/drivers/phy/microchip/ |
H A D | sparx5_serdes_regs.h | 941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument 944 FIELD_GET(SD10G_LANE_LANE_DF_LOL, x) 2096 FIELD_GET(SD6G_LANE_LANE_DF_LOL, x) 2552 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument 2553 FIELD_PREP(SD_LANE_MISC_RX_ENA, x) 2554 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument 2555 FIELD_GET(SD_LANE_MISC_RX_ENA, x) 2558 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument 2559 FIELD_PREP(SD_LANE_MISC_MUX_ENA, x) 2560 #define SD_LANE_MISC_MUX_ENA_GET(x)\ argument [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/ |
H A D | regs.h | 197 #define V_DAY(x) ((x) << S_DAY) argument 202 #define V_MONTH(x) ((x) << S_MONTH) argument 252 #define V_READY(x) ((x) << S_READY) argument 304 #define V_BANKS(x) ((x) << S_BANKS) argument 328 #define V_BUSY(x) ((x) << S_BUSY) argument 459 #define V_OP(x) ((x) << S_OP) argument 613 #define V_TPIWR(x) ((x) << S_TPIWR) argument 845 #define V_SACK(x) ((x) << S_SACK) argument 850 #define V_ECN(x) ((x) << S_ECN) argument 859 #define V_MSS(x) ((x) << S_MSS) argument [all …]
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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_main_regs.h | 4418 FIELD_GET(FDMA_CTRL_NRESET, x) 4443 #define GCB_CHIP_ID_ONE_SET(x)\ argument 4444 FIELD_PREP(GCB_CHIP_ID_ONE, x) 4445 #define GCB_CHIP_ID_ONE_GET(x)\ argument 4446 FIELD_GET(GCB_CHIP_ID_ONE, x) 6322 FIELD_GET(QS_INJ_CTRL_EOF, x) 6328 FIELD_GET(QS_INJ_CTRL_SOF, x) 6391 #define QSYS_ATOP_ATOP_SET(x)\ argument 6392 FIELD_PREP(QSYS_ATOP_ATOP, x) 6393 #define QSYS_ATOP_ATOP_GET(x)\ argument [all …]
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/openbmc/u-boot/arch/m68k/include/asm/ |
H A D | m5329.h | 17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument 18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument 19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument 20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument 21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument 22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument 96 #define PACR0(x) SCM_PACRA_PACR0(x) argument 97 #define PACR1(x) SCM_PACRA_PACR1(x) argument 98 #define PACR2(x) SCM_PACRA_PACR2(x) argument 99 #define PACR8(x) SCM_PACRB_PACR8(x) argument [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/ |
H A D | regs.h | 5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument 9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument 17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument 33 #define V_FLMODE(x) ((x) << S_FLMODE) argument 82 #define V_RSPQ(x) ((x) << S_RSPQ) argument 113 #define V_CQ(x) ((x) << S_CQ) argument 804 #define V_OP(x) ((x) << S_OP) argument 822 #define V_AE(x) ((x) << S_AE) argument 828 #define V_PE(x) ((x) << S_PE) argument 833 #define V_UE(x) ((x) << S_UE) argument [all …]
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/openbmc/linux/include/soc/mscc/ |
H A D | ocelot_ana.h | 15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) argument 17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) argument 19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument 24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) argument 26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) argument 28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument 64 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) argument 76 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) argument 99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) argument 116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) argument [all …]
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