Home
last modified time | relevance | path

Searched refs:wrmsrl (Results 1 – 25 of 85) sorted by relevance

1234

/openbmc/linux/arch/x86/hyperv/
H A Dhv_init.c135 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_init()
162 wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation()
210 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb()
211 wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb()
226 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb()
261 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_die()
281 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die()
340 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
359 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume()
524 wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); in hyperv_init()
[all …]
/openbmc/linux/arch/x86/events/intel/
H A Duncore_nhmex.c202 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
207 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
[all …]
H A Duncore_snb.c262 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
264 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
269 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
275 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box()
282 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_enable_box()
289 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box()
374 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_init_box()
385 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_enable_box()
392 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box()
527 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); in rkl_uncore_msr_init_box()
[all …]
H A Dlbr.c139 wrmsrl(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable()
157 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable()
160 wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); in __intel_pmu_lbr_enable()
168 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
176 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
177 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
179 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
186 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
201 wrmsrl(MSR_LBR_SELECT, 0); in intel_pmu_lbr_reset()
284 wrmsrl(x86_pmu.lbr_from + idx, val); in wrlbr_from()
[all …]
H A Dknc.c164 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all()
173 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all()
210 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
H A Duncore_discovery.c370 wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); in intel_generic_uncore_msr_init_box()
375 wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); in intel_generic_uncore_msr_disable_box()
380 wrmsrl(uncore_msr_box_ctl(box), 0); in intel_generic_uncore_msr_enable_box()
388 wrmsrl(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
396 wrmsrl(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
/openbmc/linux/arch/x86/kernel/cpu/
H A Dtsx.c40 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
59 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
120 wrmsrl(MSR_TSX_FORCE_ABORT, msr); in tsx_clear_cpuid()
124 wrmsrl(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
153 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); in tsx_dev_mode_disable()
H A Dcommon.c568 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); in ibt_save()
582 wrmsrl(MSR_IA32_S_CET, msr); in ibt_restore()
606 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); in setup_cet()
608 wrmsrl(MSR_IA32_S_CET, 0); in setup_cet()
614 wrmsrl(MSR_IA32_S_CET, 0); in setup_cet()
625 wrmsrl(MSR_IA32_S_CET, 0); in cet_disable()
626 wrmsrl(MSR_IA32_U_CET, 0); in cet_disable()
765 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); in switch_gdt_and_percpu_base()
1753 wrmsrl(MSR_FS_BASE, 1); in detect_null_seg_behavior()
1756 wrmsrl(MSR_FS_BASE, old_base); in detect_null_seg_behavior()
[all …]
/openbmc/u-boot/arch/x86/cpu/
H A Dmtrr.c39 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN); in mtrr_open()
48 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); in mtrr_close()
71 wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type); in mtrr_commit()
72 wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID); in mtrr_commit()
78 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); in mtrr_commit()
/openbmc/linux/arch/x86/events/amd/
H A Dlbr.c64 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2, val); in amd_pmu_lbr_set_from()
69 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); in amd_pmu_lbr_set_to()
340 wrmsrl(MSR_AMD64_LBR_SELECT, 0); in amd_pmu_lbr_reset()
402 wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select); in amd_pmu_lbr_enable_all()
407 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_enable_all()
411 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_enable_all()
423 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_disable_all()
427 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_disable_all()
/openbmc/linux/arch/x86/kernel/
H A Dkvm.c302 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
328 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
362 wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init()
364 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
377 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
389 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
451 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
453 wrmsrl(MSR_KVM_MIGRATION_CONTROL, 0); in kvm_guest_cpu_offline()
615 wrmsrl(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); in setup_efi_kvm_sev_migration()
740 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_resume()
[all …]
H A Dshstk.c176 wrmsrl(MSR_IA32_PL3_SSP, addr + size); in shstk_setup()
177 wrmsrl(MSR_IA32_U_CET, CET_SHSTK_EN); in shstk_setup()
375 wrmsrl(MSR_IA32_PL3_SSP, ssp); in setup_signal_shadow_stack()
399 wrmsrl(MSR_IA32_PL3_SSP, ssp); in restore_signal_shadow_stack()
476 wrmsrl(MSR_IA32_U_CET, msrval); in wrss_control()
495 wrmsrl(MSR_IA32_U_CET, 0); in shstk_disable()
496 wrmsrl(MSR_IA32_PL3_SSP, 0); in shstk_disable()
H A Dtsc_sync.c73 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
145 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
232 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
521 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
H A Dprocess.c341 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); in set_cpuid_faulting()
558 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
575 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
585 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
594 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
604 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); in amd_set_ssb_virt_state()
711 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __switch_to_xtra()
/openbmc/linux/arch/x86/kernel/cpu/mce/
H A Dinject.c481 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
485 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
486 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
488 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
489 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
492 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
493 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
495 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
496 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
497 wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); in prepare_msrs()
H A Dintel.c178 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
316 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover()
371 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
475 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
487 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/openbmc/linux/arch/x86/power/
H A Dcpu.c58 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
210 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
233 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
256 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
/openbmc/u-boot/cmd/x86/
H A Dmtrr.c77 wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); in do_mtrr_set()
78 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); in do_mtrr_set()
95 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); in mtrr_set_valid()
/openbmc/u-boot/arch/x86/cpu/coreboot/
H A Dcoreboot.c59 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); in board_final_cleanup()
60 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); in board_final_cleanup()
/openbmc/u-boot/arch/x86/include/asm/
H A Dmsr.h127 #define wrmsrl(msr, val) \ macro
137 wrmsrl(msr, val); in msr_clrsetbits_64()
146 wrmsrl(msr, val); in msr_setbits_64()
155 wrmsrl(msr, val); in msr_clrbits_64()
/openbmc/linux/arch/x86/xen/
H A Dsuspend.c44 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
62 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
/openbmc/linux/drivers/video/fbdev/geode/
H A Dvideo_gx.c154 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
162 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); in gx_set_dclk_frequency()
166 wrmsrl(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
186 wrmsrl(MSR_GX_MSR_PADSEL, val); in gx_configure_tft()
/openbmc/linux/drivers/cpufreq/
H A Dlonghaul.c147 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
156 wrmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
197 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
202 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
215 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
220 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
234 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
/openbmc/linux/arch/x86/events/zhaoxin/
H A Dcore.c257 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); in zhaoxin_pmu_disable_all()
262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
276 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in zhaoxin_pmu_ack_status()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
/openbmc/linux/drivers/platform/x86/intel/speed_select_if/
H A Disst_if_mbox_msr.c57 wrmsrl(MSR_OS_MAILBOX_DATA, command_data); in isst_if_send_mbox_cmd()
64 wrmsrl(MSR_OS_MAILBOX_INTERFACE, data); in isst_if_send_mbox_cmd()

1234