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Searched refs:writew (Results 1 – 25 of 110) sorted by relevance

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/openbmc/u-boot/board/renesas/sh7753evb/
H A Dsh7753evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
37 writew(0x0000, &gpio->pjcr); /* SCIF4 */ in init_gpio()
[all …]
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio()
36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio()
37 writew(0x0000, &gpio->pmcr); /* RIIC */ in init_gpio()
[all …]
/openbmc/u-boot/drivers/watchdog/
H A Dimx_watchdog.c22 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
23 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
42 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); in hw_watchdog_init()
44 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | in hw_watchdog_init()
57 writew(0x5555, &wdog->wsr); in reset_cpu()
58 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/openbmc/u-boot/arch/x86/cpu/queensbay/
H A Dtnc.c128 writew(PIRQE, &rcba->d02ir); in tnc_irq_init()
129 writew(PIRQF, &rcba->d03ir); in tnc_irq_init()
130 writew(PIRQG, &rcba->d27ir); in tnc_irq_init()
131 writew(PIRQH, &rcba->d31ir); in tnc_irq_init()
132 writew(PIRQA, &rcba->d23ir); in tnc_irq_init()
133 writew(PIRQB, &rcba->d24ir); in tnc_irq_init()
134 writew(PIRQC, &rcba->d25ir); in tnc_irq_init()
135 writew(PIRQD, &rcba->d26ir); in tnc_irq_init()
/openbmc/u-boot/board/renesas/sh7763rdp/
H A Dsh7763rdp.c39 writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); in board_init()
43 writew(((dat & ~0xff00) | 0x2400), PSEL1); in board_init()
44 writew(0, PFCR); in board_init()
45 writew(0, PGCR); in board_init()
46 writew(0, PHCR); in board_init()
/openbmc/u-boot/board/renesas/r7780mp/
H A Dr7780mp.c28 writew(0x0, PHCR); in board_init()
42 writew(0x432, FPGA_CFCTL); in ide_set_reset()
44 writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); in ide_set_reset()
46 writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); in ide_set_reset()
48 writew(0x01, FPGA_CFCDINTCLR); in ide_set_reset()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dreset.c29 writew(0x0000, &regs->wcr); in reset_cpu()
32 writew(0x5555, &regs->wsr); in reset_cpu()
33 writew(0xAAAA, &regs->wsr); in reset_cpu()
36 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/
H A Dreset.c29 writew(0, &regs->wcr); in reset_cpu()
32 writew(WSR_UNLOCK1, &regs->wsr); in reset_cpu()
33 writew(WSR_UNLOCK2, &regs->wsr); in reset_cpu()
36 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_core.c27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
52 writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
85 writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); in musb_configure_ep()
89 writew(csr | MUSB_TXCSR_FLUSHFIFO, in musb_configure_ep()
98 writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); in musb_configure_ep()
102 writew(csr | MUSB_RXCSR_FLUSHFIFO, in musb_configure_ep()
H A Dmusb_hcd.c49 writew(csr, &musbr->txcsr); in write_toggle()
52 writew(csr, &musbr->txcsr); in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
63 writew(csr, &musbr->rxcsr); in write_toggle()
67 writew(csr, &musbr->rxcsr); in write_toggle()
69 writew(csr, &musbr->rxcsr); in write_toggle()
88 writew(csr, &musbr->txcsr); in check_stall()
96 writew(csr, &musbr->txcsr); in check_stall()
103 writew(csr, &musbr->rxcsr); in check_stall()
125 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
[all …]
H A Dmusb_udc.c211 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_stall()
222 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_ack_req()
231 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready()
240 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready_and_last()
249 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_last()
280 writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); in musb_peri_rx_ack()
289 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in musb_peri_tx_ready()
603 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
608 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
819 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in udc_endpoint_write()
/openbmc/u-boot/board/ronetix/pm9263/
H A Dpm9263.c180 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
181 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ in pm9263_lcd_hw_psram_init()
186 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
188 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
195 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
196 writew(0x5678, PHYS_PSRAM + 2); in pm9263_lcd_hw_psram_init()
206 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
208 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
211 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
212 writew(0x5678, PHYS_PSRAM+2); in pm9263_lcd_hw_psram_init()
/openbmc/u-boot/arch/sh/lib/
H A Dtime_sh2.c23 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
28 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
36 writew(CMT_CMCSR_INIT, CMCSR_0); in timer_init()
40 writew(CMT_TIMER_RESET, CMCOR_0); in timer_init()
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dreset.c40 writew(WDT_TCSR_PRESCALE1 | WDT_TCSR_EXT_EN, wdt_regs + WDT_TCSR); in _machine_restart()
43 writew(0, wdt_regs + WDT_TCNT); in _machine_restart()
44 writew(0, wdt_regs + WDT_TDR); in _machine_restart()
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dsh7757lcr.c93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ in init_pcie_bridge()
94 writew(0x0000, &pciebrg->cp_ctrl); in init_pcie_bridge()
95 writew(0x0000, &pciebrg->cp_addr); in init_pcie_bridge()
99 writew(tmp, &pciebrg->cp_data); in init_pcie_bridge()
102 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ in init_pcie_bridge()
117 writew(0x0100, &phy->reset); /* set reset */ in init_usb_phy()
119 writew(0x0002, &phy->portsel); in init_usb_phy()
121 writew(0x0111, &phy->reset); /* clear reset */ in init_usb_phy()
123 writew(0x4000, &common0->suspmode); in init_usb_phy()
124 writew(0x4000, &common1->suspmode); in init_usb_phy()
/openbmc/u-boot/board/ti/panda/
H A Dpanda.c81 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); in get_board_revision()
82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); in get_board_revision()
93 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
95 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
97 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
111 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
146 writew((IEN | M3), in is_panda_es_rev_b3()
/openbmc/u-boot/drivers/spi/
H A Dpl022_spi.c103 writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0); in pl022_spi_probe()
104 writew(DFLT_PRESCALE, ps->base + SSP_CPSR); in pl022_spi_probe()
126 writew(reg, ps->base + SSP_CR1); in pl022_spi_claim_bus()
144 writew(reg, ps->base + SSP_CR1); in pl022_spi_release_bus()
182 writew(value, ps->base + SSP_DR); in pl022_spi_xfer()
250 writew(best_cpsr, ps->base + SSP_CPSR); in pl022_spi_set_speed()
252 writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0); in pl022_spi_set_speed()
268 writew(reg, ps->base + SSP_CR0); in pl022_spi_set_mode()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dinit.c77 writew(0, &wdog1->wmcr); in imx_wdog_disable_powerdown()
78 writew(0, &wdog2->wmcr); in imx_wdog_disable_powerdown()
81 writew(0, &wdog3->wmcr); in imx_wdog_disable_powerdown()
83 writew(0, &wdog4->wmcr); in imx_wdog_disable_powerdown()
/openbmc/u-boot/board/compulab/common/
H A Domap3_smc911x.c38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
/openbmc/u-boot/arch/arm/cpu/arm946es/
H A Dcpu.c59 writew(0x0, 0xfffece10); in reset_cpu()
60 writew(0x8, 0xfffece10); in reset_cpu()
/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c65 writew(mask, ctrl_addr); in mxc_w1_touch_bit()
94 writew(0xFF, &regs->tx_rx); in mxc_w1_read_byte()
120 writew(byte, &regs->tx_rx); in mxc_w1_write_byte()
133 writew(MXC_W1_CONTROL_RPP, &pdata->regs->control); in mxc_w1_reset()
199 writew(clkdiv - 1, &pdata->regs->time_divider); in mxc_w1_probe()
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dsoc.c165 writew(enable, &wdog1->wmcr); in imx_set_wdog_powerdown()
166 writew(enable, &wdog2->wmcr); in imx_set_wdog_powerdown()
167 writew(enable, &wdog3->wmcr); in imx_set_wdog_powerdown()
235 writew((WCR_WDE | WCR_SRS), &wdog->wcr); in reset_cpu()
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dhelper.c40 writew(tmp32 & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
42 writew((tmp32 >> 16) & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
52 writew(tmp32 & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
54 writew((tmp32 >> 16) & 0x0000ffff, pr_to32); in ddr_load_train_firmware()
/openbmc/u-boot/board/isee/igep00x0/
H A Digep00x0.c120 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
122 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
124 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dquark.c326 writew(PIRQC, &rcba->rmu_ir); in quark_irq_init()
327 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), in quark_irq_init()
329 writew(PIRQD, &rcba->core_ir); in quark_irq_init()
330 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), in quark_irq_init()

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