Home
last modified time | relevance | path

Searched refs:wr_mask (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/hw/intc/
H A Driscv_imsic.c93 target_ulong wr_mask) in riscv_imsic_eidelivery_rmw() argument
101 wr_mask &= 0x1; in riscv_imsic_eidelivery_rmw()
102 imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eidelivery_rmw()
111 target_ulong wr_mask) in riscv_imsic_eithreshold_rmw() argument
119 wr_mask &= IMSIC_MAX_ID; in riscv_imsic_eithreshold_rmw()
120 imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eithreshold_rmw()
128 target_ulong wr_mask) in riscv_imsic_topei_rmw() argument
138 if (topei && wr_mask) { in riscv_imsic_topei_rmw()
153 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_eix_rmw() argument
182 if (wr_mask & mask) { in riscv_imsic_eix_rmw()
[all …]
/openbmc/qemu/target/riscv/
H A Dcsr.c1788 uint64_t new_val, uint64_t wr_mask) in rmw_mideleg64()
1790 uint64_t mask = wr_mask & delegable_ints; in rmw_mideleg64()
1807 target_ulong new_val, target_ulong wr_mask) in rmw_mideleg()
1812 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); in rmw_mideleg()
1823 target_ulong wr_mask) in rmw_midelegh()
1829 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); in rmw_midelegh()
1839 uint64_t new_val, uint64_t wr_mask) in rmw_mie64()
1841 uint64_t mask = wr_mask & all_ints; in rmw_mie64()
1858 target_ulong new_val, target_ulong wr_mask) in rmw_mie()
1863 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); in rmw_mie()
1783 rmw_mideleg64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_mideleg64() argument
1802 rmw_mideleg(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mideleg() argument
1818 rmw_midelegh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_midelegh() argument
1834 rmw_mie64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_mie64() argument
1853 rmw_mie(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mie() argument
1868 rmw_mieh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mieh() argument
1884 rmw_mvien64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_mvien64() argument
1899 rmw_mvien(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mvien() argument
1914 rmw_mvienh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mvienh() argument
1971 rmw_xiselect(CPURISCVState * env,int csrno,target_ulong * val,target_ulong new_val,target_ulong wr_mask) rmw_xiselect() argument
2008 rmw_iprio(target_ulong xlen,target_ulong iselect,uint8_t * iprio,target_ulong * val,target_ulong new_val,target_ulong wr_mask,int ext_irq_no) rmw_iprio() argument
2052 rmw_xireg(CPURISCVState * env,int csrno,target_ulong * val,target_ulong new_val,target_ulong wr_mask) rmw_xireg() argument
2128 rmw_xtopei(CPURISCVState * env,int csrno,target_ulong * val,target_ulong new_val,target_ulong wr_mask) rmw_xtopei() argument
2551 write_mstateen(CPURISCVState * env,int csrno,uint64_t wr_mask,target_ulong new_val) write_mstateen() argument
2564 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; write_mstateen0() local
2591 write_mstateenh(CPURISCVState * env,int csrno,uint64_t wr_mask,target_ulong new_val) write_mstateenh() argument
2606 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; write_mstateen0h() local
2635 uint64_t *reg, wr_mask; write_hstateen() local
2647 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; write_hstateen0() local
2676 uint64_t *reg, wr_mask, val; write_hstateenh() local
2690 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; write_hstateen0h() local
2720 uint64_t wr_mask; write_sstateen() local
2737 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; write_sstateen0() local
2754 rmw_mip64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_mip64() argument
2791 rmw_mip(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mip() argument
2806 rmw_miph(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_miph() argument
2833 rmw_mvip64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_mvip64() argument
2928 rmw_mvip(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mvip() argument
2943 rmw_mviph(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_mviph() argument
3013 rmw_vsie64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_vsie64() argument
3052 rmw_vsie(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_vsie() argument
3067 rmw_vsieh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_vsieh() argument
3083 rmw_sie64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_sie64() argument
3123 rmw_sie(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_sie() argument
3138 rmw_sieh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_sieh() argument
3267 rmw_vsip64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_vsip64() argument
3298 rmw_vsip(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_vsip() argument
3313 rmw_vsiph(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_vsiph() argument
3329 rmw_sip64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_sip64() argument
3353 rmw_sip(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_sip() argument
3368 rmw_siph(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_siph() argument
3593 rmw_hvien64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_hvien64() argument
3608 rmw_hvien(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hvien() argument
3623 rmw_hvienh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hvienh() argument
3639 rmw_hideleg64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_hideleg64() argument
3653 rmw_hideleg(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hideleg() argument
3668 rmw_hidelegh(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hidelegh() argument
3693 rmw_hvip64(CPURISCVState * env,int csrno,uint64_t * ret_val,uint64_t new_val,uint64_t wr_mask) rmw_hvip64() argument
3777 rmw_hvip(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hvip() argument
3792 rmw_hviph(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hviph() argument
3821 rmw_hie(CPURISCVState * env,int csrno,target_ulong * ret_val,target_ulong new_val,target_ulong wr_mask) rmw_hie() argument
[all...]
/openbmc/linux/arch/riscv/kvm/
H A Daia.c213 unsigned long wr_mask) in kvm_riscv_vcpu_aia_rmw_topei() argument
224 val, new_val, wr_mask); in kvm_riscv_vcpu_aia_rmw_topei()
334 unsigned long wr_mask) in aia_rmw_iprio() argument
357 if (wr_mask) { in aia_rmw_iprio()
358 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); in aia_rmw_iprio()
371 unsigned long wr_mask) in kvm_riscv_vcpu_aia_rmw_ireg() argument
382 return aia_rmw_iprio(vcpu, isel, val, new_val, wr_mask); in kvm_riscv_vcpu_aia_rmw_ireg()
386 wr_mask); in kvm_riscv_vcpu_aia_rmw_ireg()
H A Dvcpu_insn.c213 unsigned long wr_mask);
257 ulong val = 0, wr_mask = 0, new_val = 0; in csr_insn() local
262 wr_mask = -1UL; in csr_insn()
266 wr_mask = rs1_val; in csr_insn()
270 wr_mask = rs1_val; in csr_insn()
274 wr_mask = -1UL; in csr_insn()
278 wr_mask = rs1_num; in csr_insn()
282 wr_mask = rs1_num; in csr_insn()
296 run->riscv_csr.write_mask = wr_mask; in csr_insn()
311 rc = cfn->func(vcpu, csr_num, &val, new_val, wr_mask); in csr_insn()
H A Daia_imsic.c218 unsigned long wr_mask) in imsic_mrif_atomic_rmw() argument
229 : "r" (~wr_mask), "r" (new_val & wr_mask) in imsic_mrif_atomic_rmw()
311 unsigned long new_val, unsigned long wr_mask) in imsic_mrif_rmw() argument
320 new_val, wr_mask & 0x1); in imsic_mrif_rmw()
324 new_val, wr_mask & (IMSIC_MAX_ID - 1)); in imsic_mrif_rmw()
350 wr_mask &= ~BIT(0); in imsic_mrif_rmw()
352 old_val = imsic_mrif_atomic_rmw(mrif, ei, new_val, wr_mask); in imsic_mrif_rmw()
843 unsigned long wr_mask) in kvm_riscv_vcpu_aia_imsic_rmw() argument
858 if (topei && wr_mask) { in kvm_riscv_vcpu_aia_imsic_rmw()
869 val, new_val, wr_mask); in kvm_riscv_vcpu_aia_imsic_rmw()
[all …]
H A Dvcpu_pmu.c280 unsigned long wr_mask) in kvm_riscv_vcpu_pmu_read_hpm() argument
302 if (wr_mask) in kvm_riscv_vcpu_pmu_read_hpm()
/openbmc/linux/drivers/thermal/intel/
H A Dintel_quark_dts_thermal.c326 int wr_mask; in alloc_soc_dts() local
342 wr_mask = QRK_DTS_WR_MASK_CLR; in alloc_soc_dts()
345 wr_mask = QRK_DTS_WR_MASK_SET; in alloc_soc_dts()
374 wr_mask, in alloc_soc_dts()
/openbmc/linux/arch/riscv/include/asm/
H A Dkvm_aia.h99 unsigned long wr_mask);
143 unsigned long wr_mask);
146 unsigned long wr_mask);
H A Dkvm_vcpu_pmu.h71 unsigned long wr_mask);
98 unsigned long wr_mask) in kvm_riscv_vcpu_pmu_read_legacy() argument
/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.h93 u32 wr_mask; member
H A Ddw-edma-core.c762 irq->wr_mask |= BIT(chan->id); in dw_edma_channel_setup()
835 u32 wr_mask = 1; in dw_edma_irq_request() local
873 dw_edma_add_irq_mask(&wr_mask, *wr_alloc, dw->wr_ch_cnt); in dw_edma_irq_request()
H A Ddw-hdma-v0-core.c126 mask = dw_irq->wr_mask; in dw_hdma_v0_core_handle_int()
H A Ddw-edma-v0-core.c247 mask = dw_irq->wr_mask; in dw_edma_v0_core_handle_int()
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pci-defs.h2029 uint64_t wr_mask:8; member
2031 uint64_t wr_mask:8;
H A Dcvmx-npei-defs.h3904 uint64_t wr_mask:8; member
3906 uint64_t wr_mask:8;