Searched refs:win_ctrl_reg (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 141 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
150 win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR; in ddr3_restore_and_set_final_windows()
153 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; in ddr3_restore_and_set_final_windows()
159 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); in ddr3_restore_and_set_final_windows()
200 u32 win_ctrl_reg, win_base_reg, win_remap_reg; in ddr3_save_and_set_training_windows() local
207 win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR; in ddr3_save_and_set_training_windows()
213 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; in ddr3_save_and_set_training_windows()
226 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_plat.c | 1106 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
1110 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; in ddr3_restore_and_set_final_windows()
1115 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
1143 u32 win_ctrl_reg, win_base_reg, win_remap_reg; in ddr3_save_and_set_training_windows() local
1145 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; in ddr3_save_and_set_training_windows()
1168 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
1192 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
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