Searched refs:width_in_mb (Results 1 – 2 of 2) sorted by relevance
623 unsigned int width_in_mb = width / 16; in amdgpu_uvd_cs_msg_decode() local625 unsigned int fs_in_mb = width_in_mb * height_in_mb; in amdgpu_uvd_cs_msg_decode()673 min_dpb_size += width_in_mb * height_in_mb * 32; in amdgpu_uvd_cs_msg_decode()682 min_dpb_size += width_in_mb * height_in_mb * 128; in amdgpu_uvd_cs_msg_decode()685 min_dpb_size += width_in_mb * 64; in amdgpu_uvd_cs_msg_decode()688 min_dpb_size += width_in_mb * 128; in amdgpu_uvd_cs_msg_decode()691 tmp = max(width_in_mb, height_in_mb); in amdgpu_uvd_cs_msg_decode()707 min_dpb_size += width_in_mb * height_in_mb * 64; in amdgpu_uvd_cs_msg_decode()750 width_in_mb * height_in_mb * num_dpb_buffer * 192; in amdgpu_uvd_cs_msg_decode()753 min_dpb_size += width_in_mb * height_in_mb * 32; in amdgpu_uvd_cs_msg_decode()[all …]
364 unsigned width_in_mb = width / 16; in radeon_uvd_cs_msg_decode() local380 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; in radeon_uvd_cs_msg_decode()383 min_dpb_size += width_in_mb * height_in_mb * 32; in radeon_uvd_cs_msg_decode()392 min_dpb_size += width_in_mb * height_in_mb * 128; in radeon_uvd_cs_msg_decode()395 min_dpb_size += width_in_mb * 64; in radeon_uvd_cs_msg_decode()398 min_dpb_size += width_in_mb * 128; in radeon_uvd_cs_msg_decode()401 tmp = max(width_in_mb, height_in_mb); in radeon_uvd_cs_msg_decode()417 min_dpb_size += width_in_mb * height_in_mb * 64; in radeon_uvd_cs_msg_decode()420 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); in radeon_uvd_cs_msg_decode()