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Searched refs:vs1 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dvcrypto_helper.c429 static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) in vsha2ms_e32() argument
432 res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) + in vsha2ms_e32()
434 res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) + in vsha2ms_e32()
439 sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)]; in vsha2ms_e32()
446 static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) in vsha2ms_e64() argument
449 res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; in vsha2ms_e64()
450 res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1]; in vsha2ms_e64()
452 res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3]; in vsha2ms_e64()
459 void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, in HELPER()
471 vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4, in HELPER()
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H A Dvector_internals.h180 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
183 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
185 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
190 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
196 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
200 do_vext_vv(vd, v0, vs1, vs2, env, desc, \
H A Dvector_internals.c58 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, in do_vext_vv() argument
77 fn(vd, vs1, vs2, i); in do_vext_vv()
H A Dvector_helper.c1135 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ in RVVCALL()
1148 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ in RVVCALL()
1207 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1219 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1343 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1362 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1457 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1470 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1941 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
1943 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
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/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc388 static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1,
395 /* When vm is 0, vs1 & vs2(EEW!=1) group can't overlap v0 (EEW=1) */
396 if ((vs1 != -1 && !require_vm(vm, vs1)) ||
401 /* When eew_vs1 != eew_vs2, check whether vs1 and vs2 are overlapped */
402 if ((vs1 != -1 && vs2 != -1) && (eew_vs1 != eew_vs2) &&
403 is_overlapped(vs1, 1 << MAX(emul_vs1, 0),
429 * 3. Source (vs2, vs1) vector register number are multiples of LMUL.
432 static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
435 vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
436 require_align(vs1, s->lmul);
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/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc680 TCGReg vd, TCGReg vs2, TCGReg vs1)
682 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
714 TCGReg vs2, TCGReg vs1)
716 tcg_out32(s, encode_v(opc, vd, vs1, vs2, false));
1537 /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */