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Searched refs:vlv_punit_read (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1089 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1094 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1103 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1137 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1151 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1648 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1661 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1682 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1687 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1696 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
H A Dintel_cdclk.c531 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
614 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
618 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
698 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
702 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
H A Di9xx_wm.c103 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
112 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
126 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
3775 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
3788 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
3792 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
3799 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
H A Dintel_display_power.c1870 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; in vlv_punit_is_power_gated()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dvlv_sideband.h117 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
H A Dvlv_sideband.c127 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rps.c1272 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1299 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1310 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1320 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1359 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1419 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1461 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
2112 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in __read_cagf()
H A Dintel_gt_pm_debugfs.c367 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in intel_gt_pm_frequency_dump()
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c163 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_detect_mem_freq()