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Searched refs:virt_memmap (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/openrisc/
H A Dvirt.c75 } virt_memmap[] = { variable
497 openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size, in openrisc_virt_init()
501 openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base, in openrisc_virt_init()
502 virt_memmap[VIRT_OMPIC].size, in openrisc_virt_init()
506 openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base, in openrisc_virt_init()
507 virt_memmap[VIRT_UART].size, in openrisc_virt_init()
510 openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base, in openrisc_virt_init()
511 virt_memmap[VIRT_TEST].size); in openrisc_virt_init()
513 openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base, in openrisc_virt_init()
514 virt_memmap[VIRT_RTC].size, smp_cpus, cpus, in openrisc_virt_init()
[all …]
/openbmc/qemu/hw/mips/
H A Dloongson3_bootp.c75 s->uarts[0].uart_base = cpu_to_le64(virt_memmap[VIRT_UART].base); in init_system_loongson()
85 irq_info->pci_mem_start_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_MMIO].base); in init_irq_source()
86 irq_info->pci_mem_end_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_MMIO].base + in init_irq_source()
87 virt_memmap[VIRT_PCIE_MMIO].size - 1); in init_irq_source()
88 irq_info->pci_io_start_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_PIO].base); in init_irq_source()
H A Dloongson3_bootp.h234 extern const MemMapEntry virt_memmap[];