Searched refs:vill (Results 1 – 8 of 8) sorted by relevance
148 VMSTATE_BOOL(env.vill, RISCVCPU),
86 bool vill; member1236 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); in riscv_tr_init_disas_context()
208 bool vill; member
725 uint64_t vill; in read_vtype() 728 vill = (uint32_t)env->vill << 31; in read_vtype() 731 vill = (uint64_t)env->vill << 63; in read_vtype() 736 *val = (target_ulong)vill | env->vtype; in read_vl() 720 uint64_t vill; read_vtype() local
151 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); in cpu_get_tb_cpu_state()
44 bool vill = (s2 >> (xlen - 1)) & 0x1; in HELPER() local 60 vill = true; in HELPER() 64 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { in HELPER() 65 /* only set vill bit. */ in HELPER() 66 env->vill = 1; in HELPER() 86 env->vill = 0; in HELPER()
1025 env->vill = true; in riscv_cpu_reset_hold()
600 return !s->vill;1129 * Thus, we don't need to check vill bit. (Section 7.9)3566 * Thus, we need to check vill bit. (Section 16.6)