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Searched refs:vill (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmachine.c148 VMSTATE_BOOL(env.vill, RISCVCPU),
H A Dtranslate.c86 bool vill; member
1236 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); in riscv_tr_init_disas_context()
H A Dcpu.h208 bool vill; member
H A Dcsr.c720 uint64_t vill; in read_vtype() local
723 vill = (uint32_t)env->vill << 31; in read_vtype()
726 vill = (uint64_t)env->vill << 63; in read_vtype()
731 *val = (target_ulong)vill | env->vtype; in read_vtype()
H A Dcpu_helper.c150 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); in cpu_get_tb_cpu_state()
H A Dvector_helper.c44 bool vill = (s2 >> (xlen - 1)) & 0x1; in HELPER() local
60 vill = true; in HELPER()
64 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { in HELPER()
66 env->vill = 1; in HELPER()
86 env->vill = 0; in HELPER()
H A Dcpu.c1025 env->vill = true; in riscv_cpu_reset_hold()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc600 return !s->vill;
1129 * Thus, we don't need to check vill bit. (Section 7.9)
3566 * Thus, we need to check vill bit. (Section 16.6)