Searched refs:vidcon (Results 1 – 1 of 1) sorted by relevance
306 uint32_t vidcon[4]; /* Video main control registers 0-3 */ member1339 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) { in exynos4210_fimd_update()1352 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon); in exynos4210_fimd_reset()1393 s->vidcon[0] = val; in exynos4210_fimd_write()1398 (s->vidcon[1] & FIMD_VIDCON1_ROMASK); in exynos4210_fimd_write()1399 s->vidcon[1] = val; in exynos4210_fimd_write()1402 s->vidcon[(offset) >> 2] = val; in exynos4210_fimd_write()1695 return s->vidcon[(offset - FIMD_VIDCON0) >> 2]; in exynos4210_fimd_read()1859 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) == in exynos4210_fimd_load()1899 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),