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Searched refs:vext_ver (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c230 env->vext_ver = VEXT_VERSION_1_00_0; in riscv_cpu_validate_v()
236 } else if (env->vext_ver == 0) { in riscv_cpu_validate_v()
240 env->vext_ver = VEXT_VERSION_1_00_0; in riscv_cpu_validate_v()
975 env->vext_ver = VEXT_VERSION_1_00_0; in riscv_init_max_cpu_extensions()
/openbmc/qemu/target/riscv/
H A Dmachine.c372 VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
H A Dcpu.h168 target_ulong vext_ver; member