Home
last modified time | relevance | path

Searched refs:twr2rd (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params() local
60 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dlpddr3_stock.c44 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_params() local
59 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dddr3_1333.c44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in mctl_set_timing_params() local
63 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para() local
166 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para()
174 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
H A Ddram_sun8i_a33.c127 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ in auto_set_timing_para() local
142 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
H A Ddram_sun50i_h6.c237 u8 twr2rd = tcwl + 4 + 1 + twtr; in mctl_set_timing_lpddr3() local
247 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_lpddr3()