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Searched refs:trd2wr (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params() local
60 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dlpddr3_stock.c45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params() local
59 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dddr3_1333.c45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params() local
63 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para() local
167 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
174 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
H A Ddram_sun8i_a33.c128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para() local
142 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
H A Ddram_sun50i_h6.c238 u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; in mctl_set_timing_lpddr3() local
247 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_lpddr3()