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Searched refs:train_set (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c439 intel_dp->train_set[lane] = in intel_dp_get_adjust_train()
459 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
507 #define TRAIN_SET_VSWING_ARGS(train_set) \ argument
508 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
509 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
510 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \
511 _TRAIN_SET_VSWING_ARGS((train_set)[3])
519 _TRAIN_SET_PREEMPH_ARGS((train_set)[3])
522 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ argument
526 _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
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H A Dg4x_dp.c796 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
798 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
882 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
884 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
959 static u32 g4x_signal_levels(u8 train_set) in g4x_signal_levels() argument
978 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in g4x_signal_levels()
1002 u8 train_set = intel_dp->train_set[0]; in g4x_set_signal_levels() local
1005 signal_levels = g4x_signal_levels(train_set); in g4x_set_signal_levels()
1018 static u32 snb_cpu_edp_signal_levels(u8 train_set) in snb_cpu_edp_signal_levels() argument
1050 u8 train_set = intel_dp->train_set[0]; in snb_cpu_edp_set_signal_levels() local
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H A Dintel_ddi.c1412 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level() local
1415 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; in intel_ddi_dp_level()
1417 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
H A Dintel_display_types.h1744 u8 train_set[4]; member
H A Dintel_display_debugfs.c951 intel_dp->train_set[0]); in i915_displayport_test_data_show()
H A Dintel_dp.c2381 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
3996 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c205 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
237 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
496 u8 train_set[4]; member
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
651 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
660 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_cr()
661 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()
702 dp_info->train_set); in amdgpu_atombios_dp_link_train_ce()
713 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_ce()
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
546 u8 train_set[4]; member
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
726 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
727 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
777 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
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/openbmc/u-boot/drivers/video/rockchip/
H A Drk_edp.c41 u8 train_set[4]; member
419 u8 train_set[]) in edp_get_adjust_train() argument
456 train_set[lane] = v | p; in edp_get_adjust_train()
473 memset(edp->train_set, '\0', sizeof(edp->train_set)); in rk_edp_link_train_cr()
481 rk_edp_set_link_training(edp, edp->train_set); in rk_edp_link_train_cr()
483 edp->train_set, in rk_edp_link_train_cr()
502 if ((edp->train_set[i] & in rk_edp_link_train_cr()
525 edp->train_set); in rk_edp_link_train_cr()
557 rk_edp_set_link_training(edp, edp->train_set); in rk_edp_link_train_ce()
570 edp->train_set); in rk_edp_link_train_ce()
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/openbmc/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c318 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
607 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
629 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
647 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
655 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
713 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
718 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
726 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
856 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c267 uint8_t train_set[4]; member
1298 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1387 intel_dp->train_set, in cdv_intel_dplink_set_level()
1392 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1492 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1503 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1510 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1531 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1543 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
1576 intel_dp->train_set[0], in cdv_intel_dp_complete_link_train()
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