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Searched refs:tmp_count (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c199 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
230 tmp_count = 0; in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
252 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; in ddr3_save_and_set_training_windows()
253 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
258 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
261 tmp_count++; in ddr3_save_and_set_training_windows()
H A Dddr3_write_leveling.c187 u32 tmp_count, ecc, reg; in ddr3_wl_supplement() local
227 tmp_count = 0; in ddr3_wl_supplement()
264 tmp_count * (SDRAM_CS_SIZE + 1) + in ddr3_wl_supplement()
420 tmp_count++; in ddr3_wl_supplement()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_plat.c1142 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
1172 tmp_count = 0; in ddr3_save_and_set_training_windows()
1192 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1194 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & in ddr3_save_and_set_training_windows()
1196 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
1201 win_jump_index * tmp_count, 0); in ddr3_save_and_set_training_windows()
1203 tmp_count++; in ddr3_save_and_set_training_windows()
/openbmc/qemu/hw/timer/
H A Dallwinner-a10-pit.c166 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in a10_pit_write() local
168 s->count_lo = tmp_count; in a10_pit_write()
169 s->count_hi = tmp_count >> 32; in a10_pit_write()
/openbmc/qemu/target/hexagon/idef-parser/
H A Didef-parser.h210 unsigned tmp_count; /**< Index of the last declared TCGv temp */ member