Searched refs:tim3 (Results 1 – 4 of 4) sorted by relevance
48 u32 tim3; member68 u32 tim3; member182 regs->tim3 = fb->panel->tim3; in clcdfb_decode()
744 u32 tim3 = 0, val = 0; in get_sdram_tim_3_reg() local746 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; in get_sdram_tim_3_reg()749 tim3 |= val << EMIF_REG_T_RFC_SHIFT; in get_sdram_tim_3_reg()752 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; in get_sdram_tim_3_reg()755 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; in get_sdram_tim_3_reg()758 tim3 |= val << EMIF_REG_T_CKESR_SHIFT; in get_sdram_tim_3_reg()760 return tim3; in get_sdram_tim_3_reg()
502 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local509 tim3 = regs->sdram_tim3_shdw; in setup_temperature_sensitive_regs()521 tim3 = regs->sdram_tim3_shdw_derated; in setup_temperature_sensitive_regs()527 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); in setup_temperature_sensitive_regs()
299 writel(regs.tim3, fb->regs + CLCD_TIM3); in clcdfb_set_par()