Searched refs:tim1 (Results 1 – 5 of 5) sorted by relevance
686 u32 tim1 = 0, val = 0; in get_sdram_tim_1_reg() local688 tim1 |= val << EMIF_REG_T_WTR_SHIFT; in get_sdram_tim_1_reg()696 tim1 |= val << EMIF_REG_T_RRD_SHIFT; in get_sdram_tim_1_reg()699 tim1 |= val << EMIF_REG_T_RC_SHIFT; in get_sdram_tim_1_reg()702 tim1 |= val << EMIF_REG_T_RAS_SHIFT; in get_sdram_tim_1_reg()705 tim1 |= val << EMIF_REG_T_WR_SHIFT; in get_sdram_tim_1_reg()708 tim1 |= val << EMIF_REG_T_RCD_SHIFT; in get_sdram_tim_1_reg()711 tim1 |= val << EMIF_REG_T_RP_SHIFT; in get_sdram_tim_1_reg()713 return tim1; in get_sdram_tim_1_reg()
66 u32 tim1; member164 regs->tim1 = val; in clcdfb_decode()
502 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local508 tim1 = regs->sdram_tim1_shdw; in setup_temperature_sensitive_regs()520 tim1 = regs->sdram_tim1_shdw_derated; in setup_temperature_sensitive_regs()526 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); in setup_temperature_sensitive_regs()
530 unsigned int *tim1, unsigned int *tim2, in pci9118_calc_divisors() argument539 *div2 = *tim1 / pacer->osc_base; /* scan timer */ in pci9118_calc_divisors()552 *tim1 = *div1 * *div2 * pacer->osc_base; in pci9118_calc_divisors()
297 writel(regs.tim1, fb->regs + CLCD_TIM1); in clcdfb_set_par()