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Searched refs:tegra_dc_readl (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/tegra/
H A Dhub.c104 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
206 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
226 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
240 return tegra_dc_readl(dc, offset) & OWNER_MASK; in tegra_shared_plane_get_owner()
269 value = tegra_dc_readl(dc, offset); in tegra_shared_plane_set_owner()
896 value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
900 value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
905 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
907 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
H A Ddc.c55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
1084 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1088 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1655 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1684 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1772 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1784 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1952 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
2307 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2311 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
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H A Drgb.c112 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
H A Dsor.c2221 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2458 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2553 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2618 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2679 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2920 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
H A Ddc.h126 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) in tegra_dc_readl() function
H A Ddsi.c859 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
946 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()
H A Dhdmi.c1176 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1413 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()