Home
last modified time | relevance | path

Searched refs:tcon (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dpwm.c19 unsigned long tcon; in pwm_enable() local
21 tcon = readl(&pwm->tcon); in pwm_enable()
22 tcon |= TCON_START(pwm_id); in pwm_enable()
24 writel(tcon, &pwm->tcon); in pwm_enable()
33 unsigned long tcon; in pwm_disable() local
35 tcon = readl(&pwm->tcon); in pwm_disable()
36 tcon &= ~TCON_START(pwm_id); in pwm_disable()
38 writel(tcon, &pwm->tcon); in pwm_disable()
66 unsigned long tcon; in pwm_config() local
100 tcon = readl(&pwm->tcon); in pwm_config()
[all …]
/openbmc/u-boot/drivers/pwm/
H A Dexynos_pwm.c26 u32 tcnt, tcmp, tcon; in exynos_pwm_set_config() local
50 tcon = readl(&regs->tcon); in exynos_pwm_set_config()
51 tcon |= TCON_UPDATE(channel); in exynos_pwm_set_config()
53 tcon |= TCON_AUTO_RELOAD(channel); in exynos_pwm_set_config()
55 tcon |= TCON4_AUTO_RELOAD; in exynos_pwm_set_config()
56 writel(tcon, &regs->tcon); in exynos_pwm_set_config()
58 tcon &= ~TCON_UPDATE(channel); in exynos_pwm_set_config()
59 writel(tcon, &regs->tcon); in exynos_pwm_set_config()
75 clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0); in exynos_pwm_set_enable()
/openbmc/u-boot/drivers/video/sunxi/
H A Dlcdc.c16 static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon) in lcdc_get_clk_delay() argument
24 if (tcon == 1) in lcdc_get_clk_delay()
211 void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, in lcdc_pll_set() argument
225 if (tcon == 0) { in lcdc_pll_set()
283 if (tcon == 0 && best_n == 0) { in lcdc_pll_set()
303 if (tcon == 0) { in lcdc_pll_set()
/openbmc/qemu/hw/timer/
H A Dexynos4210_mct.c193 uint32_t tcon; member
237 uint32_t tcon; member
288 VMSTATE_UINT32(tcon, struct lregs),
320 VMSTATE_UINT32(tcon, struct gregs),
449 if (s->g_timer.reg.tcon & G_TCON_COMP_ENABLE(i)) { in exynos4210_gcomp_find()
581 if (s->g_timer.reg.tcon & G_TCON_AUTO_ICREMENT(i)) { in exynos4210_gfrc_event()
949 if (!icnto && s->reg.tcon & L_TCON_INT_START) { in exynos4210_ltick_event()
966 if (s->reg.tcon & L_TCON_INTERVAL_MODE) { in exynos4210_ltick_event()
1042 s->l_timer[i].reg.tcon = 0; in exynos4210_mct_reset()
1094 value = s->g_timer.reg.tcon; in exynos4210_mct_read()
[all …]
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dpwm.h35 unsigned int tcon; member
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dpwm.h35 unsigned int tcon; member
/openbmc/u-boot/arch/arm/dts/
H A Dsun4i-a10.dtsi300 compatible = "allwinner,sun4i-a10-tcon";
309 "tcon-ch0",
310 "tcon-ch1";
342 allwinner,tcon-channel = <1>;
349 compatible = "allwinner,sun4i-a10-tcon";
358 "tcon-ch0",
359 "tcon-ch1";
391 allwinner,tcon-channel = <1>;
H A Dsun50i-a64.dtsi295 compatible = "allwinner,sun50i-a64-tcon-lcd",
296 "allwinner,sun8i-a83t-tcon-lcd";
300 clock-names = "ahb", "tcon-ch0";
301 clock-output-names = "tcon-pixel-clock";
329 compatible = "allwinner,sun50i-a64-tcon-tv",
330 "allwinner,sun8i-a83t-tcon-tv";
334 clock-names = "ahb", "tcon-ch1";
H A Dsun5i.dtsi238 compatible = "allwinner,sun5i-a13-tcon";
247 "tcon-ch0",
248 "tcon-ch1";
249 clock-output-names = "tcon-pixel-clock";
275 allwinner,tcon-channel = <1>;
H A Dsun6i-a31.dtsi253 compatible = "allwinner,sun6i-a31-tcon";
262 "tcon-ch0",
263 "tcon-ch1";
294 allwinner,tcon-channel = <1>;
301 compatible = "allwinner,sun6i-a31-tcon";
310 "tcon-ch0",
311 "tcon-ch1";
342 allwinner,tcon-channel = <1>;
H A Dsun7i-a20.dtsi355 compatible = "allwinner,sun7i-a20-tcon";
364 "tcon-ch0",
365 "tcon-ch1";
397 allwinner,tcon-channel = <1>;
404 compatible = "allwinner,sun7i-a20-tcon";
413 "tcon-ch0",
414 "tcon-ch1";
446 allwinner,tcon-channel = <1>;
H A Dsun8i-a33.dtsi208 compatible = "allwinner,sun8i-a33-tcon";
214 "tcon-ch0";
215 clock-output-names = "tcon-pixel-clock";
H A Dsun6i-a31s.dtsi60 compatible = "allwinner,sun6i-a31s-tcon";
H A Dsun8i-a83t.dtsi422 compatible = "allwinner,sun8i-a83t-tcon-lcd";
426 clock-names = "ahb", "tcon-ch0";
427 clock-output-names = "tcon-pixel-clock";
455 compatible = "allwinner,sun8i-a83t-tcon-tv";
459 clock-names = "ahb", "tcon-ch1";
H A Dsun5i-a10s.dtsi175 allwinner,tcon-channel = <1>;
H A Dsunxi-h3-h5.dtsi171 compatible = "allwinner,sun8i-h3-tcon-tv",
172 "allwinner,sun8i-a83t-tcon-tv";
176 clock-names = "ahb", "tcon-ch1";
H A Dsun9i-a80.dtsi843 compatible = "allwinner,sun9i-a80-tcon-lcd";
847 clock-names = "ahb", "tcon-ch0";
876 compatible = "allwinner,sun9i-a80-tcon-tv";
880 clock-names = "ahb", "tcon-ch1";
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dlcdc.h126 void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,