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Searched refs:t5 (Results 1 – 23 of 23) sorted by relevance

/openbmc/u-boot/arch/riscv/cpu/
H A Dstart.S78 la t5, board_init_f
79 jr t5 /* jump to board_init_f() */
109 LREG t5, 0(t0)
111 SREG t5, 0(t1)
131 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
133 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
135 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
136 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
138 SREG t5, 0(t3)
148 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
[all …]
/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dlowlevel_init.S72 la t5, MT76XX_ROM_STATUS_REG
74 lw t2, 0(t5)
95 li t5, ~((0x0f << 8) | (0x0f << 0))
96 and t3, t3, t5
97 li t5, (10 << 8) | (1 << 0)
98 or t3, t3, t5
182 lw t5, 0x714(s2)
184 and t5, t5, t8
202 or t5, t5, t8
217 or t5, t5, t8
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
101 andi t1, t5, 0x10
136 andi t1, t5, 0x01 # t5 BOOT_STRAP
163 andi t1, t5, 0x01 # t5 BOOT_STRAP
177 andi t1, t5, 0x01 # t5 BOOT_STRAP
201 andi t1, t5, 0x01 # t5 BOOT_STRAP
/openbmc/qemu/include/exec/
H A Dhelper-gen.h.inc63 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
67 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \
72 dh_arg(t4, 4), dh_arg(t5, 5)); \
75 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \
79 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \
84 dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \
87 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
91 dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
97 dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
H A Dhelper-proto.h.inc40 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
42 dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR;
44 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \
46 dh_ctype(t4), dh_ctype(t5), \
49 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
51 dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
H A Dhelper-head.h.inc140 #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \
141 DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
142 #define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
143 DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
144 #define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
145 DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_fp0_sqrt.S8 .macro sqrt_seq r, a, y, t1, hn, h2, t5, h
20 const.s \t5, 0
23 maddn.s \t5, \y, \hn
27 maddn.s \hn, \t5, \y
/openbmc/qemu/target/mips/tcg/
H A Dmxu_translate.c1364 TCGv t0, t1, t2, t3, t4, t5, t6, t7; in gen_mxu_q8mul_mac() local
1372 t5 = tcg_temp_new(); in gen_mxu_q8mul_mac()
1400 tcg_gen_extract_tl(t5, t7, 8, 8); in gen_mxu_q8mul_mac()
1405 tcg_gen_mul_tl(t1, t1, t5); in gen_mxu_q8mul_mac()
1411 gen_load_mxu_gpr(t5, XRa); in gen_mxu_q8mul_mac()
1421 tcg_gen_extract_tl(t6, t5, 0, 16); in gen_mxu_q8mul_mac()
1422 tcg_gen_extract_tl(t7, t5, 16, 16); in gen_mxu_q8mul_mac()
1446 TCGv t0, t1, t2, t3, t4, t5, t6, t7; in gen_mxu_q8madl() local
1454 t5 = tcg_temp_new(); in gen_mxu_q8madl()
1473 tcg_gen_extract_tl(t5, t7, 8, 8); in gen_mxu_q8madl()
[all …]
/openbmc/qemu/common-user/host/mips/
H A Dsafe-syscall.inc.S70 lw t5, FRAME+28(sp)
74 sw t5, 20(sp)
/openbmc/u-boot/arch/nds32/cpu/n1213/
H A Dstart.S333 sll $t5, $t4, $t1 ! get $t5 cache line size
342 sub $p1, $p1, $t5
368 sll $t5, $t4, $t1 ! get $t5 cache line size
377 sub $p1, $p1, $t5
/openbmc/qemu/linux-user/riscv/
H A Dtarget_syscall.h42 abi_long t5; member
/openbmc/u-boot/arch/mips/include/asm/
H A Dregdef.h33 #define t5 $13 macro
/openbmc/qemu/linux-headers/asm-riscv/
H A Dptrace.h55 unsigned long t5; member
/openbmc/u-boot/arch/riscv/include/asm/
H A Dptrace.h43 unsigned long t5; member
/openbmc/qemu/tests/tcg/loongarch64/system/
H A Dregdef.h27 #define t5 $r17 macro
/openbmc/openbmc/poky/meta/recipes-sato/webkit/webkitgtk/
H A Dt6-not-declared.patch30 UNUSED_VARIABLE(t5);
/openbmc/openbmc/meta-openembedded/meta-gnome/recipes-gnome/evolution-data-server/evolution-data-server/
H A D0003-contact-Replace-the-Novell-sample-contact-with-somet.patch109 +" YdtdUADff+QCA5Q/9BQB+Xk7w9a27vpxP8g0AO9J4IYA64/qOE3m/k4WQIWWGsmJI/q0fn2P+t5\n" \
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/
H A DAdd-riscv64-support.patch217 + fn("t5", regs_[RISCV64_REG_T5]);
420 + "sd t5, 240(%[base])\n"
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/system/core/
H A DAdd-riscv64-support.patch217 + fn("t5", regs_[RISCV64_REG_T5]);
420 + "sd t5, 240(%[base])\n"
/openbmc/qemu/tcg/
H A Dtcg.c2743 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) in tcg_gen_call5() argument
2745 TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; in tcg_gen_call5()
2751 TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) in tcg_gen_call6() argument
2753 TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; in tcg_gen_call6()
2759 TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) in tcg_gen_call7() argument
2761 TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; in tcg_gen_call7()
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc62 "t5",
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc65 "t5",
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc44 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",